USB: m66592-udc: fixes some problems · tjh.dev/kernel@598f22e

+18 -18

drivers/usb/gadget/Kconfig

··· 177 177 default y if USB_ETH 178 178 default y if USB_G_SERIAL 179 179 180 + config USB_GADGET_M66592 181 + boolean "Renesas M66592 USB Peripheral Controller" 182 + select USB_GADGET_DUALSPEED 183 + help 184 + M66592 is a discrete USB peripheral controller chip that 185 + supports both full and high speed USB 2.0 data transfers. 186 + It has seven configurable endpoints, and endpoint zero. 187 + 188 + Say "y" to link the driver statically, or "m" to build a 189 + dynamically linked module called "m66592_udc" and force all 190 + gadget drivers to also be dynamically linked. 191 + 192 + config USB_M66592 193 + tristate 194 + depends on USB_GADGET_M66592 195 + default USB_GADGET 196 + select USB_GADGET_SELECTED 197 + 180 198 config USB_GADGET_GOKU 181 199 boolean "Toshiba TC86C001 'Goku-S'" 182 200 depends on PCI ··· 299 281 tristate 300 282 depends on USB_GADGET_AT91 301 283 default USB_GADGET 302 - 303 - config USB_GADGET_M66592 304 - boolean "M66592 driver" 305 - select USB_GADGET_DUALSPEED 306 - help 307 - M66592 is a USB 2.0 peripheral controller. 308 - 309 - It has seven configurable endpoints, and endpoint zero. 310 - 311 - Say "y" to link the driver statically, or "m" to build a 312 - dynamically linked module called "m66592_udc" and force all 313 - gadget drivers to also be dynamically linked. 314 - 315 - config USB_M66592 316 - tristate 317 - depends on USB_GADGET_M66592 318 - default USB_GADGET 319 - select USB_GADGET_SELECTED 320 284 321 285 config USB_GADGET_DUMMY_HCD 322 286 boolean "Dummy HCD (DEVELOPMENT)"

+1 -1

drivers/usb/gadget/gadget_chips.h

··· 211 211 else if (gadget_is_amd5536udc(gadget)) 212 212 return 0x20; 213 213 else if (gadget_is_m66592(gadget)) 214 - return 0x20; 214 + return 0x21; 215 215 return -ENOENT; 216 216 }

+127 -128

drivers/usb/gadget/m66592-udc.c

··· 21 21 */ 22 22 23 23 #include <linux/module.h> 24 - #include <linux/kernel.h> 25 - #include <linux/sched.h> 26 - #include <linux/smp_lock.h> 27 - #include <linux/errno.h> 28 - #include <linux/init.h> 29 - #include <linux/timer.h> 30 - #include <linux/delay.h> 31 - #include <linux/list.h> 32 24 #include <linux/interrupt.h> 25 + #include <linux/delay.h> 26 + #include <linux/io.h> 33 27 #include <linux/platform_device.h> 28 + 34 29 #include <linux/usb/ch9.h> 35 30 #include <linux/usb_gadget.h> 36 31 37 - #include <asm/io.h> 38 - #include <asm/irq.h> 39 - #include <asm/system.h> 40 - 41 32 #include "m66592-udc.h" 42 33 43 - MODULE_DESCRIPTION("M66592 USB gadget driiver"); 34 + 35 + MODULE_DESCRIPTION("M66592 USB gadget driver"); 44 36 MODULE_LICENSE("GPL"); 45 37 MODULE_AUTHOR("Yoshihiro Shimoda"); 46 38 ··· 41 49 /* module parameters */ 42 50 static unsigned short clock = M66592_XTAL24; 43 51 module_param(clock, ushort, 0644); 44 - MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=16384)"); 52 + MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 " 53 + "(default=16384)"); 54 + 45 55 static unsigned short vif = M66592_LDRV; 46 56 module_param(vif, ushort, 0644); 47 - MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)"); 48 - static unsigned short endian = 0; 57 + MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)"); 58 + 59 + static unsigned short endian; 49 60 module_param(endian, ushort, 0644); 50 - MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)"); 61 + MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)"); 62 + 51 63 static unsigned short irq_sense = M66592_INTL; 52 64 module_param(irq_sense, ushort, 0644); 53 - MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0(default=2)"); 65 + MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 " 66 + "(default=2)"); 54 67 55 68 static const char udc_name[] = "m66592_udc"; 56 69 static const char *m66592_ep_name[] = { ··· 69 72 gfp_t gfp_flags); 70 73 71 74 static void transfer_complete(struct m66592_ep *ep, 72 - struct m66592_request *req, 73 - int status); 75 + struct m66592_request *req, int status); 76 + 74 77 /*-------------------------------------------------------------------------*/ 75 78 static inline u16 get_usb_speed(struct m66592 *m66592) 76 79 { ··· 78 81 } 79 82 80 83 static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum, 81 - unsigned long reg) 84 + unsigned long reg) 82 85 { 83 86 u16 tmp; 84 87 85 88 tmp = m66592_read(m66592, M66592_INTENB0); 86 89 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE, 87 - M66592_INTENB0); 90 + M66592_INTENB0); 88 91 m66592_bset(m66592, (1 << pipenum), reg); 89 92 m66592_write(m66592, tmp, M66592_INTENB0); 90 93 } 91 94 92 95 static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum, 93 - unsigned long reg) 96 + unsigned long reg) 94 97 { 95 98 u16 tmp; 96 99 97 100 tmp = m66592_read(m66592, M66592_INTENB0); 98 101 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE, 99 - M66592_INTENB0); 102 + M66592_INTENB0); 100 103 m66592_bclr(m66592, (1 << pipenum), reg); 101 104 m66592_write(m66592, tmp, M66592_INTENB0); 102 105 } ··· 105 108 { 106 109 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0); 107 110 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL, 108 - M66592_INTENB0); 111 + M66592_INTENB0); 109 112 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0); 110 113 111 114 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG); 112 115 } 113 116 114 117 static void m66592_usb_disconnect(struct m66592 *m66592) 118 + __releases(m66592->lock) 119 + __acquires(m66592->lock) 115 120 { 116 121 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0); 117 122 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL, 118 - M66592_INTENB0); 123 + M66592_INTENB0); 119 124 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0); 120 125 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG); 121 126 ··· 147 148 } 148 149 149 150 static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum, 150 - u16 pid) 151 + u16 pid) 151 152 { 152 153 unsigned long offset; 153 154 ··· 249 250 } 250 251 251 252 static int pipe_buffer_setting(struct m66592 *m66592, 252 - struct m66592_pipe_info *info) 253 + struct m66592_pipe_info *info) 253 254 { 254 255 u16 bufnum = 0, buf_bsize = 0; 255 256 u16 pipecfg = 0; ··· 286 287 } 287 288 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) { 288 289 printk(KERN_ERR "m66592 pipe memory is insufficient(%d)\n", 289 - m66592->bi_bufnum); 290 + m66592->bi_bufnum); 290 291 return -ENOMEM; 291 292 } 292 293 ··· 327 328 m66592->bulk--; 328 329 } else 329 330 printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n", 330 - info->pipe); 331 + info->pipe); 331 332 } 332 333 333 334 static void pipe_initialize(struct m66592_ep *ep) ··· 349 350 } 350 351 351 352 static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep, 352 - const struct usb_endpoint_descriptor *desc, 353 - u16 pipenum, int dma) 353 + const struct usb_endpoint_descriptor *desc, 354 + u16 pipenum, int dma) 354 355 { 355 356 if ((pipenum != 0) && dma) { 356 357 if (m66592->num_dma == 0) { ··· 384 385 385 386 ep->pipectr = get_pipectr_addr(pipenum); 386 387 ep->pipenum = pipenum; 387 - ep->ep.maxpacket = desc->wMaxPacketSize; 388 + ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); 388 389 m66592->pipenum2ep[pipenum] = ep; 389 390 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep; 390 391 INIT_LIST_HEAD(&ep->queue); ··· 406 407 } 407 408 408 409 static int alloc_pipe_config(struct m66592_ep *ep, 409 - const struct usb_endpoint_descriptor *desc) 410 + const struct usb_endpoint_descriptor *desc) 410 411 { 411 412 struct m66592 *m66592 = ep->m66592; 412 413 struct m66592_pipe_info info; ··· 418 419 419 420 BUG_ON(ep->pipenum); 420 421 421 - switch(desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 422 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 422 423 case USB_ENDPOINT_XFER_BULK: 423 424 if (m66592->bulk >= M66592_MAX_NUM_BULK) { 424 425 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) { 425 426 printk(KERN_ERR "bulk pipe is insufficient\n"); 426 427 return -ENODEV; 427 428 } else { 428 - info.pipe = M66592_BASE_PIPENUM_ISOC + 429 - m66592->isochronous; 429 + info.pipe = M66592_BASE_PIPENUM_ISOC 430 + + m66592->isochronous; 430 431 counter = &m66592->isochronous; 431 432 } 432 433 } else { ··· 461 462 ep->type = info.type; 462 463 463 464 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 464 - info.maxpacket = desc->wMaxPacketSize; 465 + info.maxpacket = le16_to_cpu(desc->wMaxPacketSize); 465 466 info.interval = desc->bInterval; 466 467 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) 467 468 info.dir_in = 1; ··· 524 525 525 526 pipe_change(m66592, ep->pipenum); 526 527 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0, 527 - (M66592_ISEL | M66592_CURPIPE), 528 - M66592_CFIFOSEL); 528 + (M66592_ISEL | M66592_CURPIPE), 529 + M66592_CFIFOSEL); 529 530 m66592_write(m66592, M66592_BCLR, ep->fifoctr); 530 531 if (req->req.length == 0) { 531 532 m66592_bset(m66592, M66592_BVAL, ep->fifoctr); ··· 560 561 561 562 if (ep->pipenum == 0) { 562 563 m66592_mdfy(m66592, M66592_PIPE0, 563 - (M66592_ISEL | M66592_CURPIPE), 564 - M66592_CFIFOSEL); 564 + (M66592_ISEL | M66592_CURPIPE), 565 + M66592_CFIFOSEL); 565 566 m66592_write(m66592, M66592_BCLR, ep->fifoctr); 566 567 pipe_start(m66592, pipenum); 567 568 pipe_irq_enable(m66592, pipenum); ··· 571 572 pipe_change(m66592, pipenum); 572 573 m66592_bset(m66592, M66592_TRENB, ep->fifosel); 573 574 m66592_write(m66592, 574 - (req->req.length + ep->ep.maxpacket - 1) / 575 - ep->ep.maxpacket, ep->fifotrn); 575 + (req->req.length + ep->ep.maxpacket - 1) 576 + / ep->ep.maxpacket, 577 + ep->fifotrn); 576 578 } 577 579 pipe_start(m66592, pipenum); /* trigger once */ 578 580 pipe_irq_enable(m66592, pipenum); ··· 614 614 static void init_controller(struct m66592 *m66592) 615 615 { 616 616 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND), 617 - M66592_PINCFG); 617 + M66592_PINCFG); 618 618 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */ 619 619 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG); 620 620 ··· 634 634 635 635 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1); 636 636 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR, 637 - M66592_DMA0CFG); 637 + M66592_DMA0CFG); 638 638 } 639 639 640 640 static void disable_controller(struct m66592 *m66592) ··· 659 659 660 660 /*-------------------------------------------------------------------------*/ 661 661 static void transfer_complete(struct m66592_ep *ep, 662 - struct m66592_request *req, 663 - int status) 662 + struct m66592_request *req, int status) 663 + __releases(m66592->lock) 664 + __acquires(m66592->lock) 664 665 { 665 666 int restart = 0; 666 667 ··· 681 680 if (!list_empty(&ep->queue)) 682 681 restart = 1; 683 682 684 - if (likely(req->req.complete)) 685 - req->req.complete(&ep->ep, &req->req); 683 + spin_unlock(&ep->m66592->lock); 684 + req->req.complete(&ep->ep, &req->req); 685 + spin_lock(&ep->m66592->lock); 686 686 687 687 if (restart) { 688 688 req = list_entry(ep->queue.next, struct m66592_request, queue); ··· 695 693 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req) 696 694 { 697 695 int i; 698 - volatile u16 tmp; 696 + u16 tmp; 699 697 unsigned bufsize; 700 698 size_t size; 701 699 void *buf; ··· 733 731 req->req.actual += size; 734 732 735 733 /* check transfer finish */ 736 - if ((!req->req.zero && (req->req.actual == req->req.length)) || 737 - (size % ep->ep.maxpacket) || (size == 0)) { 734 + if ((!req->req.zero && (req->req.actual == req->req.length)) 735 + || (size % ep->ep.maxpacket) 736 + || (size == 0)) { 738 737 disable_irq_ready(m66592, pipenum); 739 738 disable_irq_empty(m66592, pipenum); 740 739 } else { ··· 771 768 /* write fifo */ 772 769 if (req->req.buf) { 773 770 m66592_write_fifo(m66592, ep->fifoaddr, buf, size); 774 - if ((size == 0) || ((size % ep->ep.maxpacket) != 0) || 775 - ((bufsize != ep->ep.maxpacket) && (bufsize > size))) 771 + if ((size == 0) 772 + || ((size % ep->ep.maxpacket) != 0) 773 + || ((bufsize != ep->ep.maxpacket) 774 + && (bufsize > size))) 776 775 m66592_bset(m66592, M66592_BVAL, ep->fifoctr); 777 776 } 778 777 779 778 /* update parameters */ 780 779 req->req.actual += size; 781 780 /* check transfer finish */ 782 - if ((!req->req.zero && (req->req.actual == req->req.length)) || 783 - (size % ep->ep.maxpacket) || (size == 0)) { 781 + if ((!req->req.zero && (req->req.actual == req->req.length)) 782 + || (size % ep->ep.maxpacket) 783 + || (size == 0)) { 784 784 disable_irq_ready(m66592, pipenum); 785 785 enable_irq_empty(m66592, pipenum); 786 786 } else { ··· 827 821 req->req.actual += size; 828 822 829 823 /* check transfer finish */ 830 - if ((!req->req.zero && (req->req.actual == req->req.length)) || 831 - (size % ep->ep.maxpacket) || (size == 0)) { 824 + if ((!req->req.zero && (req->req.actual == req->req.length)) 825 + || (size % ep->ep.maxpacket) 826 + || (size == 0)) { 832 827 pipe_stop(m66592, pipenum); 833 828 pipe_irq_disable(m66592, pipenum); 834 829 finish = 1; ··· 857 850 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) { 858 851 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS); 859 852 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE, 860 - M66592_CFIFOSEL); 853 + M66592_CFIFOSEL); 861 854 862 855 ep = &m66592->ep[0]; 863 856 req = list_entry(ep->queue.next, struct m66592_request, queue); ··· 916 909 } 917 910 918 911 static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) 912 + __releases(m66592->lock) 913 + __acquires(m66592->lock) 919 914 { 920 915 struct m66592_ep *ep; 921 916 u16 pid; 922 917 u16 status = 0; 918 + u16 w_index = le16_to_cpu(ctrl->wIndex); 923 919 924 920 switch (ctrl->bRequestType & USB_RECIP_MASK) { 925 921 case USB_RECIP_DEVICE: 926 - status = 1; /* selfpower */ 922 + status = 1 << USB_DEVICE_SELF_POWERED; 927 923 break; 928 924 case USB_RECIP_INTERFACE: 929 925 status = 0; 930 926 break; 931 927 case USB_RECIP_ENDPOINT: 932 - ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK]; 928 + ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK]; 933 929 pid = control_reg_get_pid(m66592, ep->pipenum); 934 930 if (pid == M66592_PID_STALL) 935 - status = 1; 931 + status = 1 << USB_ENDPOINT_HALT; 936 932 else 937 933 status = 0; 938 934 break; ··· 944 934 return; /* exit */ 945 935 } 946 936 947 - *m66592->ep0_buf = status; 948 - m66592->ep0_req->buf = m66592->ep0_buf; 937 + m66592->ep0_data = cpu_to_le16(status); 938 + m66592->ep0_req->buf = &m66592->ep0_data; 949 939 m66592->ep0_req->length = 2; 950 940 /* AV: what happens if we get called again before that gets through? */ 941 + spin_unlock(&m66592->lock); 951 942 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL); 943 + spin_lock(&m66592->lock); 952 944 } 953 945 954 946 static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) ··· 965 953 case USB_RECIP_ENDPOINT: { 966 954 struct m66592_ep *ep; 967 955 struct m66592_request *req; 956 + u16 w_index = le16_to_cpu(ctrl->wIndex); 968 957 969 - ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK]; 958 + ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK]; 970 959 pipe_stop(m66592, ep->pipenum); 971 960 control_reg_sqclr(m66592, ep->pipenum); 972 961 ··· 1002 989 break; 1003 990 case USB_RECIP_ENDPOINT: { 1004 991 struct m66592_ep *ep; 992 + u16 w_index = le16_to_cpu(ctrl->wIndex); 1005 993 1006 - ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK]; 994 + ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK]; 1007 995 pipe_stall(m66592, ep->pipenum); 1008 996 1009 997 control_end(m66592, 1); ··· 1080 1066 } 1081 1067 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG) 1082 1068 m66592_update_usb_speed(m66592); 1083 - if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS) && 1084 - m66592->gadget.speed == USB_SPEED_UNKNOWN) 1069 + if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS) 1070 + && m66592->gadget.speed == USB_SPEED_UNKNOWN) 1085 1071 m66592_update_usb_speed(m66592); 1086 1072 1087 1073 m66592->old_dvsq = dvsq; 1088 1074 } 1089 1075 1090 1076 static void irq_control_stage(struct m66592 *m66592) 1077 + __releases(m66592->lock) 1078 + __acquires(m66592->lock) 1091 1079 { 1092 1080 struct usb_ctrlrequest ctrl; 1093 1081 u16 ctsq; ··· 1111 1095 case M66592_CS_WRDS: 1112 1096 case M66592_CS_WRND: 1113 1097 if (setup_packet(m66592, &ctrl)) { 1098 + spin_unlock(&m66592->lock); 1114 1099 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0) 1115 1100 pipe_stall(m66592, 0); 1101 + spin_lock(&m66592->lock); 1116 1102 } 1117 1103 break; 1118 1104 case M66592_CS_RDSS: ··· 1137 1119 u16 savepipe; 1138 1120 u16 mask0; 1139 1121 1122 + spin_lock(&m66592->lock); 1123 + 1140 1124 intsts0 = m66592_read(m66592, M66592_INTSTS0); 1141 1125 intenb0 = m66592_read(m66592, M66592_INTENB0); 1142 1126 ··· 1154 1134 bempenb = m66592_read(m66592, M66592_BEMPENB); 1155 1135 1156 1136 if (mask0 & M66592_VBINT) { 1157 - m66592_write(m66592, (u16)~M66592_VBINT, 1158 - M66592_INTSTS0); 1137 + m66592_write(m66592, 0xffff & ~M66592_VBINT, 1138 + M66592_INTSTS0); 1159 1139 m66592_start_xclock(m66592); 1160 1140 1161 1141 /* start vbus sampling */ 1162 1142 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0) 1163 - & M66592_VBSTS; 1143 + & M66592_VBSTS; 1164 1144 m66592->scount = M66592_MAX_SAMPLING; 1165 1145 1166 1146 mod_timer(&m66592->timer, 1167 - jiffies + msecs_to_jiffies(50)); 1147 + jiffies + msecs_to_jiffies(50)); 1168 1148 } 1169 1149 if (intsts0 & M66592_DVSQ) 1170 1150 irq_device_state(m66592); 1171 1151 1172 - if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE) && 1173 - (brdysts & brdyenb)) { 1152 + if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE) 1153 + && (brdysts & brdyenb)) { 1174 1154 irq_pipe_ready(m66592, brdysts, brdyenb); 1175 1155 } 1176 - if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE) && 1177 - (bempsts & bempenb)) { 1156 + if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE) 1157 + && (bempsts & bempenb)) { 1178 1158 irq_pipe_empty(m66592, bempsts, bempenb); 1179 1159 } 1180 1160 ··· 1184 1164 1185 1165 m66592_write(m66592, savepipe, M66592_CFIFOSEL); 1186 1166 1167 + spin_unlock(&m66592->lock); 1187 1168 return IRQ_HANDLED; 1188 1169 } 1189 1170 ··· 1212 1191 m66592_usb_disconnect(m66592); 1213 1192 } else { 1214 1193 mod_timer(&m66592->timer, 1215 - jiffies + msecs_to_jiffies(50)); 1194 + jiffies + msecs_to_jiffies(50)); 1216 1195 } 1217 1196 } else { 1218 1197 m66592->scount = M66592_MAX_SAMPLING; 1219 1198 m66592->old_vbus = tmp; 1220 1199 mod_timer(&m66592->timer, 1221 - jiffies + msecs_to_jiffies(50)); 1200 + jiffies + msecs_to_jiffies(50)); 1222 1201 } 1223 1202 } 1224 1203 spin_unlock_irqrestore(&m66592->lock, flags); ··· 1356 1335 return ret; 1357 1336 } 1358 1337 1359 - static int m66592_fifo_status(struct usb_ep *_ep) 1360 - { 1361 - return -EOPNOTSUPP; 1362 - } 1363 - 1364 1338 static void m66592_fifo_flush(struct usb_ep *_ep) 1365 1339 { 1366 1340 struct m66592_ep *ep; ··· 1381 1365 .dequeue = m66592_dequeue, 1382 1366 1383 1367 .set_halt = m66592_set_halt, 1384 - .fifo_status = m66592_fifo_status, 1385 1368 .fifo_flush = m66592_fifo_flush, 1386 1369 }; 1387 1370 ··· 1392 1377 struct m66592 *m66592 = the_controller; 1393 1378 int retval; 1394 1379 1395 - if (!driver || 1396 - driver->speed != USB_SPEED_HIGH || 1397 - !driver->bind || 1398 - !driver->unbind || 1399 - !driver->setup) 1380 + if (!driver 1381 + || driver->speed != USB_SPEED_HIGH 1382 + || !driver->bind 1383 + || !driver->setup) 1400 1384 return -EINVAL; 1401 1385 if (!m66592) 1402 1386 return -ENODEV; ··· 1427 1413 m66592->old_vbus = m66592_read(m66592, 1428 1414 M66592_INTSTS0) & M66592_VBSTS; 1429 1415 m66592->scount = M66592_MAX_SAMPLING; 1430 - mod_timer(&m66592->timer, 1431 - jiffies + msecs_to_jiffies(50)); 1416 + mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50)); 1432 1417 } 1433 1418 1434 1419 return 0; ··· 1444 1431 { 1445 1432 struct m66592 *m66592 = the_controller; 1446 1433 unsigned long flags; 1434 + 1435 + if (driver != m66592->driver || !driver->unbind) 1436 + return -EINVAL; 1447 1437 1448 1438 spin_lock_irqsave(&m66592->lock, flags); 1449 1439 if (m66592->gadget.speed != USB_SPEED_UNKNOWN) ··· 1477 1461 .get_frame = m66592_get_frame, 1478 1462 }; 1479 1463 1480 - #if defined(CONFIG_PM) 1481 - static int m66592_suspend(struct platform_device *pdev, pm_message_t state) 1482 - { 1483 - pdev->dev.power.power_state = state; 1484 - return 0; 1485 - } 1486 - 1487 - static int m66592_resume(struct platform_device *pdev) 1488 - { 1489 - pdev->dev.power.power_state = PMSG_ON; 1490 - return 0; 1491 - } 1492 - #else /* if defined(CONFIG_PM) */ 1493 - #define m66592_suspend NULL 1494 - #define m66592_resume NULL 1495 - #endif 1496 - 1497 - static int __init_or_module m66592_remove(struct platform_device *pdev) 1464 + static int __exit m66592_remove(struct platform_device *pdev) 1498 1465 { 1499 1466 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev); 1500 1467 1501 1468 del_timer_sync(&m66592->timer); 1502 1469 iounmap(m66592->reg); 1503 1470 free_irq(platform_get_irq(pdev, 0), m66592); 1471 + m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req); 1504 1472 kfree(m66592); 1505 1473 return 0; 1506 1474 } 1507 1475 1476 + static void nop_completion(struct usb_ep *ep, struct usb_request *r) 1477 + { 1478 + } 1479 + 1508 1480 #define resource_len(r) (((r)->end - (r)->start) + 1) 1481 + 1509 1482 static int __init m66592_probe(struct platform_device *pdev) 1510 1483 { 1511 - struct resource *res = NULL; 1512 - int irq = -1; 1484 + struct resource *res; 1485 + int irq; 1513 1486 void __iomem *reg = NULL; 1514 1487 struct m66592 *m66592 = NULL; 1515 1488 int ret = 0; 1516 1489 int i; 1517 1490 1518 1491 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1519 - (char *)udc_name); 1492 + (char *)udc_name); 1520 1493 if (!res) { 1521 1494 ret = -ENODEV; 1522 1495 printk(KERN_ERR "platform_get_resource_byname error.\n"); ··· 1553 1548 m66592->bi_bufnum = M66592_BASE_BUFNUM; 1554 1549 1555 1550 ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED, 1556 - udc_name, m66592); 1551 + udc_name, m66592); 1557 1552 if (ret < 0) { 1558 1553 printk(KERN_ERR "request_irq error (%d)\n", ret); 1559 1554 goto clean_up; ··· 1568 1563 if (i != 0) { 1569 1564 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list); 1570 1565 list_add_tail(&m66592->ep[i].ep.ep_list, 1571 - &m66592->gadget.ep_list); 1566 + &m66592->gadget.ep_list); 1572 1567 } 1573 1568 ep->m66592 = m66592; 1574 1569 INIT_LIST_HEAD(&ep->queue); ··· 1588 1583 1589 1584 the_controller = m66592; 1590 1585 1591 - /* AV: leaks */ 1592 1586 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL); 1593 1587 if (m66592->ep0_req == NULL) 1594 - goto clean_up; 1595 - /* AV: leaks, and do we really need it separately allocated? */ 1596 - m66592->ep0_buf = kzalloc(2, GFP_KERNEL); 1597 - if (m66592->ep0_buf == NULL) 1598 - goto clean_up; 1588 + goto clean_up2; 1589 + m66592->ep0_req->complete = nop_completion; 1599 1590 1600 1591 init_controller(m66592); 1601 1592 1602 - printk("driver %s, %s\n", udc_name, DRIVER_VERSION); 1593 + dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION); 1603 1594 return 0; 1604 1595 1596 + clean_up2: 1597 + free_irq(irq, m66592); 1605 1598 clean_up: 1606 1599 if (m66592) { 1607 1600 if (m66592->ep0_req) ··· 1614 1611 1615 1612 /*-------------------------------------------------------------------------*/ 1616 1613 static struct platform_driver m66592_driver = { 1617 - .probe = m66592_probe, 1618 - .remove = m66592_remove, 1619 - .suspend = m66592_suspend, 1620 - .resume = m66592_resume, 1614 + .remove = __exit_p(m66592_remove), 1621 1615 .driver = { 1622 1616 .name = (char *) udc_name, 1623 1617 }, ··· 1622 1622 1623 1623 static int __init m66592_udc_init(void) 1624 1624 { 1625 - return platform_driver_register(&m66592_driver); 1625 + return platform_driver_probe(&m66592_driver, m66592_probe); 1626 1626 } 1627 1627 module_init(m66592_udc_init); 1628 1628 ··· 1631 1631 platform_driver_unregister(&m66592_driver); 1632 1632 } 1633 1633 module_exit(m66592_udc_cleanup); 1634 -

+304 -306

drivers/usb/gadget/m66592-udc.h

··· 24 24 #define __M66592_UDC_H__ 25 25 26 26 #define M66592_SYSCFG 0x00 27 - #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ 28 - #define M66592_XTAL48 0x8000 /* 48MHz */ 29 - #define M66592_XTAL24 0x4000 /* 24MHz */ 30 - #define M66592_XTAL12 0x0000 /* 12MHz */ 31 - #define M66592_XCKE 0x2000 /* b13: External clock enable */ 32 - #define M66592_RCKE 0x1000 /* b12: Register clock enable */ 33 - #define M66592_PLLC 0x0800 /* b11: PLL control */ 34 - #define M66592_SCKE 0x0400 /* b10: USB clock enable */ 35 - #define M66592_ATCKM 0x0100 /* b8: Automatic supply functional enable */ 36 - #define M66592_HSE 0x0080 /* b7: Hi-speed enable */ 37 - #define M66592_DCFM 0x0040 /* b6: Controller function select */ 38 - #define M66592_DMRPD 0x0020 /* b5: D- pull down control */ 39 - #define M66592_DPRPU 0x0010 /* b4: D+ pull up control */ 40 - #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */ 41 - #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */ 42 - #define M66592_USBE 0x0001 /* b0: USB module operation enable */ 27 + #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ 28 + #define M66592_XTAL48 0x8000 /* 48MHz */ 29 + #define M66592_XTAL24 0x4000 /* 24MHz */ 30 + #define M66592_XTAL12 0x0000 /* 12MHz */ 31 + #define M66592_XCKE 0x2000 /* b13: External clock enable */ 32 + #define M66592_RCKE 0x1000 /* b12: Register clock enable */ 33 + #define M66592_PLLC 0x0800 /* b11: PLL control */ 34 + #define M66592_SCKE 0x0400 /* b10: USB clock enable */ 35 + #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */ 36 + #define M66592_HSE 0x0080 /* b7: Hi-speed enable */ 37 + #define M66592_DCFM 0x0040 /* b6: Controller function select */ 38 + #define M66592_DMRPD 0x0020 /* b5: D- pull down control */ 39 + #define M66592_DPRPU 0x0010 /* b4: D+ pull up control */ 40 + #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */ 41 + #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */ 42 + #define M66592_USBE 0x0001 /* b0: USB module operation enable */ 43 43 44 44 #define M66592_SYSSTS 0x02 45 - #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */ 46 - #define M66592_SE1 0x0003 /* SE1 */ 47 - #define M66592_KSTS 0x0002 /* K State */ 48 - #define M66592_JSTS 0x0001 /* J State */ 49 - #define M66592_SE0 0x0000 /* SE0 */ 45 + #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */ 46 + #define M66592_SE1 0x0003 /* SE1 */ 47 + #define M66592_KSTS 0x0002 /* K State */ 48 + #define M66592_JSTS 0x0001 /* J State */ 49 + #define M66592_SE0 0x0000 /* SE0 */ 50 50 51 51 #define M66592_DVSTCTR 0x04 52 - #define M66592_WKUP 0x0100 /* b8: Remote wakeup */ 53 - #define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */ 54 - #define M66592_USBRST 0x0040 /* b6: USB reset enable */ 55 - #define M66592_RESUME 0x0020 /* b5: Resume enable */ 56 - #define M66592_UACT 0x0010 /* b4: USB bus enable */ 57 - #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */ 58 - #define M66592_HSMODE 0x0003 /* Hi-Speed mode */ 59 - #define M66592_FSMODE 0x0002 /* Full-Speed mode */ 60 - #define M66592_HSPROC 0x0001 /* HS handshake is processing */ 52 + #define M66592_WKUP 0x0100 /* b8: Remote wakeup */ 53 + #define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */ 54 + #define M66592_USBRST 0x0040 /* b6: USB reset enable */ 55 + #define M66592_RESUME 0x0020 /* b5: Resume enable */ 56 + #define M66592_UACT 0x0010 /* b4: USB bus enable */ 57 + #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */ 58 + #define M66592_HSMODE 0x0003 /* Hi-Speed mode */ 59 + #define M66592_FSMODE 0x0002 /* Full-Speed mode */ 60 + #define M66592_HSPROC 0x0001 /* HS handshake is processing */ 61 61 62 62 #define M66592_TESTMODE 0x06 63 - #define M66592_UTST 0x000F /* b4-0: Test select */ 64 - #define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */ 65 - #define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 66 - #define M66592_H_TST_K 0x000A /* HOST TEST K */ 67 - #define M66592_H_TST_J 0x0009 /* HOST TEST J */ 68 - #define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 69 - #define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */ 70 - #define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 71 - #define M66592_P_TST_K 0x0002 /* PERI TEST K */ 72 - #define M66592_P_TST_J 0x0001 /* PERI TEST J */ 73 - #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 63 + #define M66592_UTST 0x000F /* b4-0: Test select */ 64 + #define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */ 65 + #define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 66 + #define M66592_H_TST_K 0x000A /* HOST TEST K */ 67 + #define M66592_H_TST_J 0x0009 /* HOST TEST J */ 68 + #define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 69 + #define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */ 70 + #define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 71 + #define M66592_P_TST_K 0x0002 /* PERI TEST K */ 72 + #define M66592_P_TST_J 0x0001 /* PERI TEST J */ 73 + #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 74 74 75 75 #define M66592_PINCFG 0x0A 76 - #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ 77 - #define M66592_BIGEND 0x0100 /* b8: Big endian mode */ 76 + #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ 77 + #define M66592_BIGEND 0x0100 /* b8: Big endian mode */ 78 78 79 79 #define M66592_DMA0CFG 0x0C 80 80 #define M66592_DMA1CFG 0x0E 81 - #define M66592_DREQA 0x4000 /* b14: Dreq active select */ 82 - #define M66592_BURST 0x2000 /* b13: Burst mode */ 83 - #define M66592_DACKA 0x0400 /* b10: Dack active select */ 84 - #define M66592_DFORM 0x0380 /* b9-7: DMA mode select */ 85 - #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 86 - #define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 87 - #define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 88 - #define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 89 - #define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */ 90 - #define M66592_DENDA 0x0040 /* b6: Dend active select */ 91 - #define M66592_PKTM 0x0020 /* b5: Packet mode */ 92 - #define M66592_DENDE 0x0010 /* b4: Dend enable */ 93 - #define M66592_OBUS 0x0004 /* b2: OUTbus mode */ 81 + #define M66592_DREQA 0x4000 /* b14: Dreq active select */ 82 + #define M66592_BURST 0x2000 /* b13: Burst mode */ 83 + #define M66592_DACKA 0x0400 /* b10: Dack active select */ 84 + #define M66592_DFORM 0x0380 /* b9-7: DMA mode select */ 85 + #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 86 + #define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 87 + #define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 88 + #define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 89 + #define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */ 90 + #define M66592_DENDA 0x0040 /* b6: Dend active select */ 91 + #define M66592_PKTM 0x0020 /* b5: Packet mode */ 92 + #define M66592_DENDE 0x0010 /* b4: Dend enable */ 93 + #define M66592_OBUS 0x0004 /* b2: OUTbus mode */ 94 94 95 95 #define M66592_CFIFO 0x10 96 96 #define M66592_D0FIFO 0x14 ··· 99 99 #define M66592_CFIFOSEL 0x1E 100 100 #define M66592_D0FIFOSEL 0x24 101 101 #define M66592_D1FIFOSEL 0x2A 102 - #define M66592_RCNT 0x8000 /* b15: Read count mode */ 103 - #define M66592_REW 0x4000 /* b14: Buffer rewind */ 104 - #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ 105 - #define M66592_DREQE 0x1000 /* b12: DREQ output enable */ 106 - #define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO access */ 107 - #define M66592_MBW_8 0x0000 /* 8bit */ 108 - #define M66592_MBW_16 0x0400 /* 16bit */ 109 - #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ 110 - #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ 111 - #define M66592_DEZPM 0x0080 /* b7: Zero-length packet additional mode */ 112 - #define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */ 113 - #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */ 102 + #define M66592_RCNT 0x8000 /* b15: Read count mode */ 103 + #define M66592_REW 0x4000 /* b14: Buffer rewind */ 104 + #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ 105 + #define M66592_DREQE 0x1000 /* b12: DREQ output enable */ 106 + #define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */ 107 + #define M66592_MBW_8 0x0000 /* 8bit */ 108 + #define M66592_MBW_16 0x0400 /* 16bit */ 109 + #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ 110 + #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ 111 + #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ 112 + #define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */ 113 + #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */ 114 114 115 115 #define M66592_CFIFOCTR 0x20 116 116 #define M66592_D0FIFOCTR 0x26 117 117 #define M66592_D1FIFOCTR 0x2c 118 - #define M66592_BVAL 0x8000 /* b15: Buffer valid flag */ 119 - #define M66592_BCLR 0x4000 /* b14: Buffer clear */ 120 - #define M66592_FRDY 0x2000 /* b13: FIFO ready */ 121 - #define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */ 118 + #define M66592_BVAL 0x8000 /* b15: Buffer valid flag */ 119 + #define M66592_BCLR 0x4000 /* b14: Buffer clear */ 120 + #define M66592_FRDY 0x2000 /* b13: FIFO ready */ 121 + #define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */ 122 122 123 123 #define M66592_CFIFOSIE 0x22 124 - #define M66592_TGL 0x8000 /* b15: Buffer toggle */ 125 - #define M66592_SCLR 0x4000 /* b14: Buffer clear */ 126 - #define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */ 124 + #define M66592_TGL 0x8000 /* b15: Buffer toggle */ 125 + #define M66592_SCLR 0x4000 /* b14: Buffer clear */ 126 + #define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */ 127 127 128 128 #define M66592_D0FIFOTRN 0x28 129 129 #define M66592_D1FIFOTRN 0x2E 130 - #define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */ 130 + #define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */ 131 131 132 132 #define M66592_INTENB0 0x30 133 - #define M66592_VBSE 0x8000 /* b15: VBUS interrupt */ 134 - #define M66592_RSME 0x4000 /* b14: Resume interrupt */ 135 - #define M66592_SOFE 0x2000 /* b13: Frame update interrupt */ 136 - #define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */ 137 - #define M66592_CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 138 - #define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */ 139 - #define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 140 - #define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */ 141 - #define M66592_URST 0x0080 /* b7: USB reset detected interrupt */ 142 - #define M66592_SADR 0x0040 /* b6: Set address executed interrupt */ 143 - #define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */ 144 - #define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */ 145 - #define M66592_WDST 0x0008 /* b3: Control write data stage completed interrupt */ 146 - #define M66592_RDST 0x0004 /* b2: Control read data stage completed interrupt */ 147 - #define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */ 148 - #define M66592_SERR 0x0001 /* b0: Sequence error interrupt */ 133 + #define M66592_VBSE 0x8000 /* b15: VBUS interrupt */ 134 + #define M66592_RSME 0x4000 /* b14: Resume interrupt */ 135 + #define M66592_SOFE 0x2000 /* b13: Frame update interrupt */ 136 + #define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */ 137 + #define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */ 138 + #define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */ 139 + #define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 140 + #define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */ 141 + #define M66592_URST 0x0080 /* b7: USB reset detected interrupt */ 142 + #define M66592_SADR 0x0040 /* b6: Set address executed interrupt */ 143 + #define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */ 144 + #define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */ 145 + #define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */ 146 + #define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */ 147 + #define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */ 148 + #define M66592_SERR 0x0001 /* b0: Sequence error interrupt */ 149 149 150 150 #define M66592_INTENB1 0x32 151 - #define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */ 152 - #define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */ 153 - #define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 154 - #define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */ 155 - #define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */ 156 - #define M66592_INTL 0x0002 /* b1: Interrupt sense select */ 157 - #define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */ 151 + #define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */ 152 + #define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */ 153 + #define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 154 + #define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */ 155 + #define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */ 156 + #define M66592_INTL 0x0002 /* b1: Interrupt sense select */ 157 + #define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */ 158 158 159 159 #define M66592_BRDYENB 0x36 160 160 #define M66592_BRDYSTS 0x46 161 - #define M66592_BRDY7 0x0080 /* b7: PIPE7 */ 162 - #define M66592_BRDY6 0x0040 /* b6: PIPE6 */ 163 - #define M66592_BRDY5 0x0020 /* b5: PIPE5 */ 164 - #define M66592_BRDY4 0x0010 /* b4: PIPE4 */ 165 - #define M66592_BRDY3 0x0008 /* b3: PIPE3 */ 166 - #define M66592_BRDY2 0x0004 /* b2: PIPE2 */ 167 - #define M66592_BRDY1 0x0002 /* b1: PIPE1 */ 168 - #define M66592_BRDY0 0x0001 /* b1: PIPE0 */ 161 + #define M66592_BRDY7 0x0080 /* b7: PIPE7 */ 162 + #define M66592_BRDY6 0x0040 /* b6: PIPE6 */ 163 + #define M66592_BRDY5 0x0020 /* b5: PIPE5 */ 164 + #define M66592_BRDY4 0x0010 /* b4: PIPE4 */ 165 + #define M66592_BRDY3 0x0008 /* b3: PIPE3 */ 166 + #define M66592_BRDY2 0x0004 /* b2: PIPE2 */ 167 + #define M66592_BRDY1 0x0002 /* b1: PIPE1 */ 168 + #define M66592_BRDY0 0x0001 /* b1: PIPE0 */ 169 169 170 170 #define M66592_NRDYENB 0x38 171 171 #define M66592_NRDYSTS 0x48 172 - #define M66592_NRDY7 0x0080 /* b7: PIPE7 */ 173 - #define M66592_NRDY6 0x0040 /* b6: PIPE6 */ 174 - #define M66592_NRDY5 0x0020 /* b5: PIPE5 */ 175 - #define M66592_NRDY4 0x0010 /* b4: PIPE4 */ 176 - #define M66592_NRDY3 0x0008 /* b3: PIPE3 */ 177 - #define M66592_NRDY2 0x0004 /* b2: PIPE2 */ 178 - #define M66592_NRDY1 0x0002 /* b1: PIPE1 */ 179 - #define M66592_NRDY0 0x0001 /* b1: PIPE0 */ 172 + #define M66592_NRDY7 0x0080 /* b7: PIPE7 */ 173 + #define M66592_NRDY6 0x0040 /* b6: PIPE6 */ 174 + #define M66592_NRDY5 0x0020 /* b5: PIPE5 */ 175 + #define M66592_NRDY4 0x0010 /* b4: PIPE4 */ 176 + #define M66592_NRDY3 0x0008 /* b3: PIPE3 */ 177 + #define M66592_NRDY2 0x0004 /* b2: PIPE2 */ 178 + #define M66592_NRDY1 0x0002 /* b1: PIPE1 */ 179 + #define M66592_NRDY0 0x0001 /* b1: PIPE0 */ 180 180 181 181 #define M66592_BEMPENB 0x3A 182 182 #define M66592_BEMPSTS 0x4A 183 - #define M66592_BEMP7 0x0080 /* b7: PIPE7 */ 184 - #define M66592_BEMP6 0x0040 /* b6: PIPE6 */ 185 - #define M66592_BEMP5 0x0020 /* b5: PIPE5 */ 186 - #define M66592_BEMP4 0x0010 /* b4: PIPE4 */ 187 - #define M66592_BEMP3 0x0008 /* b3: PIPE3 */ 188 - #define M66592_BEMP2 0x0004 /* b2: PIPE2 */ 189 - #define M66592_BEMP1 0x0002 /* b1: PIPE1 */ 190 - #define M66592_BEMP0 0x0001 /* b0: PIPE0 */ 183 + #define M66592_BEMP7 0x0080 /* b7: PIPE7 */ 184 + #define M66592_BEMP6 0x0040 /* b6: PIPE6 */ 185 + #define M66592_BEMP5 0x0020 /* b5: PIPE5 */ 186 + #define M66592_BEMP4 0x0010 /* b4: PIPE4 */ 187 + #define M66592_BEMP3 0x0008 /* b3: PIPE3 */ 188 + #define M66592_BEMP2 0x0004 /* b2: PIPE2 */ 189 + #define M66592_BEMP1 0x0002 /* b1: PIPE1 */ 190 + #define M66592_BEMP0 0x0001 /* b0: PIPE0 */ 191 191 192 192 #define M66592_SOFCFG 0x3C 193 - #define M66592_SOFM 0x000C /* b3-2: SOF palse mode */ 194 - #define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */ 195 - #define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 196 - #define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */ 193 + #define M66592_SOFM 0x000C /* b3-2: SOF palse mode */ 194 + #define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */ 195 + #define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 196 + #define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */ 197 197 198 198 #define M66592_INTSTS0 0x40 199 - #define M66592_VBINT 0x8000 /* b15: VBUS interrupt */ 200 - #define M66592_RESM 0x4000 /* b14: Resume interrupt */ 201 - #define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */ 202 - #define M66592_DVST 0x1000 /* b12: Device state transition interrupt */ 203 - #define M66592_CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 204 - #define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */ 205 - #define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */ 206 - #define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */ 207 - #define M66592_VBSTS 0x0080 /* b7: VBUS input port */ 208 - #define M66592_DVSQ 0x0070 /* b6-4: Device state */ 209 - #define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */ 210 - #define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */ 211 - #define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */ 212 - #define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */ 213 - #define M66592_DS_SUSP 0x0040 /* Suspend */ 214 - #define M66592_DS_CNFG 0x0030 /* Configured */ 215 - #define M66592_DS_ADDS 0x0020 /* Address */ 216 - #define M66592_DS_DFLT 0x0010 /* Default */ 217 - #define M66592_DS_POWR 0x0000 /* Powered */ 218 - #define M66592_DVSQS 0x0030 /* b5-4: Device state */ 219 - #define M66592_VALID 0x0008 /* b3: Setup packet detected flag */ 220 - #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */ 221 - #define M66592_CS_SQER 0x0006 /* Sequence error */ 222 - #define M66592_CS_WRND 0x0005 /* Control write nodata status stage */ 223 - #define M66592_CS_WRSS 0x0004 /* Control write status stage */ 224 - #define M66592_CS_WRDS 0x0003 /* Control write data stage */ 225 - #define M66592_CS_RDSS 0x0002 /* Control read status stage */ 226 - #define M66592_CS_RDDS 0x0001 /* Control read data stage */ 227 - #define M66592_CS_IDST 0x0000 /* Idle or setup stage */ 199 + #define M66592_VBINT 0x8000 /* b15: VBUS interrupt */ 200 + #define M66592_RESM 0x4000 /* b14: Resume interrupt */ 201 + #define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */ 202 + #define M66592_DVST 0x1000 /* b12: Device state transition */ 203 + #define M66592_CTRT 0x0800 /* b11: Control stage transition */ 204 + #define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */ 205 + #define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */ 206 + #define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */ 207 + #define M66592_VBSTS 0x0080 /* b7: VBUS input port */ 208 + #define M66592_DVSQ 0x0070 /* b6-4: Device state */ 209 + #define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */ 210 + #define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */ 211 + #define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */ 212 + #define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */ 213 + #define M66592_DS_SUSP 0x0040 /* Suspend */ 214 + #define M66592_DS_CNFG 0x0030 /* Configured */ 215 + #define M66592_DS_ADDS 0x0020 /* Address */ 216 + #define M66592_DS_DFLT 0x0010 /* Default */ 217 + #define M66592_DS_POWR 0x0000 /* Powered */ 218 + #define M66592_DVSQS 0x0030 /* b5-4: Device state */ 219 + #define M66592_VALID 0x0008 /* b3: Setup packet detected flag */ 220 + #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */ 221 + #define M66592_CS_SQER 0x0006 /* Sequence error */ 222 + #define M66592_CS_WRND 0x0005 /* Control write nodata status */ 223 + #define M66592_CS_WRSS 0x0004 /* Control write status stage */ 224 + #define M66592_CS_WRDS 0x0003 /* Control write data stage */ 225 + #define M66592_CS_RDSS 0x0002 /* Control read status stage */ 226 + #define M66592_CS_RDDS 0x0001 /* Control read data stage */ 227 + #define M66592_CS_IDST 0x0000 /* Idle or setup stage */ 228 228 229 229 #define M66592_INTSTS1 0x42 230 - #define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */ 231 - #define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */ 232 - #define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */ 233 - #define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */ 230 + #define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */ 231 + #define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */ 232 + #define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */ 233 + #define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */ 234 234 235 235 #define M66592_FRMNUM 0x4C 236 - #define M66592_OVRN 0x8000 /* b15: Overrun error */ 237 - #define M66592_CRCE 0x4000 /* b14: Received data error */ 238 - #define M66592_SOFRM 0x0800 /* b11: SOF output mode */ 239 - #define M66592_FRNM 0x07FF /* b10-0: Frame number */ 236 + #define M66592_OVRN 0x8000 /* b15: Overrun error */ 237 + #define M66592_CRCE 0x4000 /* b14: Received data error */ 238 + #define M66592_SOFRM 0x0800 /* b11: SOF output mode */ 239 + #define M66592_FRNM 0x07FF /* b10-0: Frame number */ 240 240 241 241 #define M66592_UFRMNUM 0x4E 242 - #define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */ 242 + #define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */ 243 243 244 244 #define M66592_RECOVER 0x50 245 - #define M66592_STSRECOV 0x0700 /* Status recovery */ 246 - #define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */ 247 - #define M66592_STSR_DEFAULT 0x0100 /* Default state */ 248 - #define M66592_STSR_ADDRESS 0x0200 /* Address state */ 249 - #define M66592_STSR_CONFIG 0x0300 /* Configured state */ 250 - #define M66592_USBADDR 0x007F /* b6-0: USB address */ 245 + #define M66592_STSRECOV 0x0700 /* Status recovery */ 246 + #define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */ 247 + #define M66592_STSR_DEFAULT 0x0100 /* Default state */ 248 + #define M66592_STSR_ADDRESS 0x0200 /* Address state */ 249 + #define M66592_STSR_CONFIG 0x0300 /* Configured state */ 250 + #define M66592_USBADDR 0x007F /* b6-0: USB address */ 251 251 252 252 #define M66592_USBREQ 0x54 253 - #define M66592_bRequest 0xFF00 /* b15-8: bRequest */ 254 - #define M66592_GET_STATUS 0x0000 255 - #define M66592_CLEAR_FEATURE 0x0100 256 - #define M66592_ReqRESERVED 0x0200 257 - #define M66592_SET_FEATURE 0x0300 258 - #define M66592_ReqRESERVED1 0x0400 259 - #define M66592_SET_ADDRESS 0x0500 260 - #define M66592_GET_DESCRIPTOR 0x0600 261 - #define M66592_SET_DESCRIPTOR 0x0700 262 - #define M66592_GET_CONFIGURATION 0x0800 263 - #define M66592_SET_CONFIGURATION 0x0900 264 - #define M66592_GET_INTERFACE 0x0A00 265 - #define M66592_SET_INTERFACE 0x0B00 266 - #define M66592_SYNCH_FRAME 0x0C00 267 - #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */ 268 - #define M66592_bmRequestTypeDir 0x0080 /* b7 : Data transfer direction */ 269 - #define M66592_HOST_TO_DEVICE 0x0000 270 - #define M66592_DEVICE_TO_HOST 0x0080 271 - #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */ 272 - #define M66592_STANDARD 0x0000 273 - #define M66592_CLASS 0x0020 274 - #define M66592_VENDOR 0x0040 275 - #define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */ 276 - #define M66592_DEVICE 0x0000 277 - #define M66592_INTERFACE 0x0001 278 - #define M66592_ENDPOINT 0x0002 253 + #define M66592_bRequest 0xFF00 /* b15-8: bRequest */ 254 + #define M66592_GET_STATUS 0x0000 255 + #define M66592_CLEAR_FEATURE 0x0100 256 + #define M66592_ReqRESERVED 0x0200 257 + #define M66592_SET_FEATURE 0x0300 258 + #define M66592_ReqRESERVED1 0x0400 259 + #define M66592_SET_ADDRESS 0x0500 260 + #define M66592_GET_DESCRIPTOR 0x0600 261 + #define M66592_SET_DESCRIPTOR 0x0700 262 + #define M66592_GET_CONFIGURATION 0x0800 263 + #define M66592_SET_CONFIGURATION 0x0900 264 + #define M66592_GET_INTERFACE 0x0A00 265 + #define M66592_SET_INTERFACE 0x0B00 266 + #define M66592_SYNCH_FRAME 0x0C00 267 + #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */ 268 + #define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */ 269 + #define M66592_HOST_TO_DEVICE 0x0000 270 + #define M66592_DEVICE_TO_HOST 0x0080 271 + #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */ 272 + #define M66592_STANDARD 0x0000 273 + #define M66592_CLASS 0x0020 274 + #define M66592_VENDOR 0x0040 275 + #define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */ 276 + #define M66592_DEVICE 0x0000 277 + #define M66592_INTERFACE 0x0001 278 + #define M66592_ENDPOINT 0x0002 279 279 280 280 #define M66592_USBVAL 0x56 281 - #define M66592_wValue 0xFFFF /* b15-0: wValue */ 281 + #define M66592_wValue 0xFFFF /* b15-0: wValue */ 282 282 /* Standard Feature Selector */ 283 - #define M66592_ENDPOINT_HALT 0x0000 284 - #define M66592_DEVICE_REMOTE_WAKEUP 0x0001 285 - #define M66592_TEST_MODE 0x0002 283 + #define M66592_ENDPOINT_HALT 0x0000 284 + #define M66592_DEVICE_REMOTE_WAKEUP 0x0001 285 + #define M66592_TEST_MODE 0x0002 286 286 /* Descriptor Types */ 287 - #define M66592_DT_TYPE 0xFF00 288 - #define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8) 289 - #define M66592_DT_DEVICE 0x01 290 - #define M66592_DT_CONFIGURATION 0x02 291 - #define M66592_DT_STRING 0x03 292 - #define M66592_DT_INTERFACE 0x04 293 - #define M66592_DT_ENDPOINT 0x05 294 - #define M66592_DT_DEVICE_QUALIFIER 0x06 295 - #define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07 296 - #define M66592_DT_INTERFACE_POWER 0x08 297 - #define M66592_DT_INDEX 0x00FF 298 - #define M66592_CONF_NUM 0x00FF 299 - #define M66592_ALT_SET 0x00FF 287 + #define M66592_DT_TYPE 0xFF00 288 + #define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8) 289 + #define M66592_DT_DEVICE 0x01 290 + #define M66592_DT_CONFIGURATION 0x02 291 + #define M66592_DT_STRING 0x03 292 + #define M66592_DT_INTERFACE 0x04 293 + #define M66592_DT_ENDPOINT 0x05 294 + #define M66592_DT_DEVICE_QUALIFIER 0x06 295 + #define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07 296 + #define M66592_DT_INTERFACE_POWER 0x08 297 + #define M66592_DT_INDEX 0x00FF 298 + #define M66592_CONF_NUM 0x00FF 299 + #define M66592_ALT_SET 0x00FF 300 300 301 301 #define M66592_USBINDEX 0x58 302 - #define M66592_wIndex 0xFFFF /* b15-0: wIndex */ 303 - #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode Selectors */ 304 - #define M66592_TEST_J 0x0100 /* Test_J */ 305 - #define M66592_TEST_K 0x0200 /* Test_K */ 306 - #define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */ 307 - #define M66592_TEST_PACKET 0x0400 /* Test_Packet */ 308 - #define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */ 309 - #define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */ 310 - #define M66592_TEST_Reserved 0x4000 /* Reserved */ 311 - #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific test modes */ 312 - #define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */ 313 - #define M66592_EP_DIR_IN 0x0080 314 - #define M66592_EP_DIR_OUT 0x0000 302 + #define M66592_wIndex 0xFFFF /* b15-0: wIndex */ 303 + #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */ 304 + #define M66592_TEST_J 0x0100 /* Test_J */ 305 + #define M66592_TEST_K 0x0200 /* Test_K */ 306 + #define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */ 307 + #define M66592_TEST_PACKET 0x0400 /* Test_Packet */ 308 + #define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */ 309 + #define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */ 310 + #define M66592_TEST_Reserved 0x4000 /* Reserved */ 311 + #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */ 312 + #define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */ 313 + #define M66592_EP_DIR_IN 0x0080 314 + #define M66592_EP_DIR_OUT 0x0000 315 315 316 316 #define M66592_USBLENG 0x5A 317 - #define M66592_wLength 0xFFFF /* b15-0: wLength */ 317 + #define M66592_wLength 0xFFFF /* b15-0: wLength */ 318 318 319 319 #define M66592_DCPCFG 0x5C 320 - #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 321 - #define M66592_DIR 0x0010 /* b4: Control transfer DIR select */ 320 + #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */ 321 + #define M66592_DIR 0x0010 /* b4: Control transfer DIR select */ 322 322 323 323 #define M66592_DCPMAXP 0x5E 324 - #define M66592_DEVSEL 0xC000 /* b15-14: Device address select */ 325 - #define M66592_DEVICE_0 0x0000 /* Device address 0 */ 326 - #define M66592_DEVICE_1 0x4000 /* Device address 1 */ 327 - #define M66592_DEVICE_2 0x8000 /* Device address 2 */ 328 - #define M66592_DEVICE_3 0xC000 /* Device address 3 */ 329 - #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 324 + #define M66592_DEVSEL 0xC000 /* b15-14: Device address select */ 325 + #define M66592_DEVICE_0 0x0000 /* Device address 0 */ 326 + #define M66592_DEVICE_1 0x4000 /* Device address 1 */ 327 + #define M66592_DEVICE_2 0x8000 /* Device address 2 */ 328 + #define M66592_DEVICE_3 0xC000 /* Device address 3 */ 329 + #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */ 330 330 331 331 #define M66592_DCPCTR 0x60 332 - #define M66592_BSTS 0x8000 /* b15: Buffer status */ 333 - #define M66592_SUREQ 0x4000 /* b14: Send USB request */ 334 - #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 335 - #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 336 - #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 337 - #define M66592_CCPL 0x0004 /* b2: Enable control transfer complete */ 338 - #define M66592_PID 0x0003 /* b1-0: Response PID */ 339 - #define M66592_PID_STALL 0x0002 /* STALL */ 340 - #define M66592_PID_BUF 0x0001 /* BUF */ 341 - #define M66592_PID_NAK 0x0000 /* NAK */ 332 + #define M66592_BSTS 0x8000 /* b15: Buffer status */ 333 + #define M66592_SUREQ 0x4000 /* b14: Send USB request */ 334 + #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 335 + #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 336 + #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 337 + #define M66592_CCPL 0x0004 /* b2: control transfer complete */ 338 + #define M66592_PID 0x0003 /* b1-0: Response PID */ 339 + #define M66592_PID_STALL 0x0002 /* STALL */ 340 + #define M66592_PID_BUF 0x0001 /* BUF */ 341 + #define M66592_PID_NAK 0x0000 /* NAK */ 342 342 343 343 #define M66592_PIPESEL 0x64 344 - #define M66592_PIPENM 0x0007 /* b2-0: Pipe select */ 345 - #define M66592_PIPE0 0x0000 /* PIPE 0 */ 346 - #define M66592_PIPE1 0x0001 /* PIPE 1 */ 347 - #define M66592_PIPE2 0x0002 /* PIPE 2 */ 348 - #define M66592_PIPE3 0x0003 /* PIPE 3 */ 349 - #define M66592_PIPE4 0x0004 /* PIPE 4 */ 350 - #define M66592_PIPE5 0x0005 /* PIPE 5 */ 351 - #define M66592_PIPE6 0x0006 /* PIPE 6 */ 352 - #define M66592_PIPE7 0x0007 /* PIPE 7 */ 344 + #define M66592_PIPENM 0x0007 /* b2-0: Pipe select */ 345 + #define M66592_PIPE0 0x0000 /* PIPE 0 */ 346 + #define M66592_PIPE1 0x0001 /* PIPE 1 */ 347 + #define M66592_PIPE2 0x0002 /* PIPE 2 */ 348 + #define M66592_PIPE3 0x0003 /* PIPE 3 */ 349 + #define M66592_PIPE4 0x0004 /* PIPE 4 */ 350 + #define M66592_PIPE5 0x0005 /* PIPE 5 */ 351 + #define M66592_PIPE6 0x0006 /* PIPE 6 */ 352 + #define M66592_PIPE7 0x0007 /* PIPE 7 */ 353 353 354 354 #define M66592_PIPECFG 0x66 355 - #define M66592_TYP 0xC000 /* b15-14: Transfer type */ 356 - #define M66592_ISO 0xC000 /* Isochronous */ 357 - #define M66592_INT 0x8000 /* Interrupt */ 358 - #define M66592_BULK 0x4000 /* Bulk */ 359 - #define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ 360 - #define M66592_DBLB 0x0200 /* b9: Double buffer mode select */ 361 - #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 362 - #define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */ 363 - #define M66592_DIR 0x0010 /* b4: Transfer direction select */ 364 - #define M66592_DIR_H_OUT 0x0010 /* HOST OUT */ 365 - #define M66592_DIR_P_IN 0x0010 /* PERI IN */ 366 - #define M66592_DIR_H_IN 0x0000 /* HOST IN */ 367 - #define M66592_DIR_P_OUT 0x0000 /* PERI OUT */ 368 - #define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */ 369 - #define M66592_EP1 0x0001 370 - #define M66592_EP2 0x0002 371 - #define M66592_EP3 0x0003 372 - #define M66592_EP4 0x0004 373 - #define M66592_EP5 0x0005 374 - #define M66592_EP6 0x0006 375 - #define M66592_EP7 0x0007 376 - #define M66592_EP8 0x0008 377 - #define M66592_EP9 0x0009 378 - #define M66592_EP10 0x000A 379 - #define M66592_EP11 0x000B 380 - #define M66592_EP12 0x000C 381 - #define M66592_EP13 0x000D 382 - #define M66592_EP14 0x000E 383 - #define M66592_EP15 0x000F 355 + #define M66592_TYP 0xC000 /* b15-14: Transfer type */ 356 + #define M66592_ISO 0xC000 /* Isochronous */ 357 + #define M66592_INT 0x8000 /* Interrupt */ 358 + #define M66592_BULK 0x4000 /* Bulk */ 359 + #define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */ 360 + #define M66592_DBLB 0x0200 /* b9: Double buffer mode select */ 361 + #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */ 362 + #define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */ 363 + #define M66592_DIR 0x0010 /* b4: Transfer direction select */ 364 + #define M66592_DIR_H_OUT 0x0010 /* HOST OUT */ 365 + #define M66592_DIR_P_IN 0x0010 /* PERI IN */ 366 + #define M66592_DIR_H_IN 0x0000 /* HOST IN */ 367 + #define M66592_DIR_P_OUT 0x0000 /* PERI OUT */ 368 + #define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */ 369 + #define M66592_EP1 0x0001 370 + #define M66592_EP2 0x0002 371 + #define M66592_EP3 0x0003 372 + #define M66592_EP4 0x0004 373 + #define M66592_EP5 0x0005 374 + #define M66592_EP6 0x0006 375 + #define M66592_EP7 0x0007 376 + #define M66592_EP8 0x0008 377 + #define M66592_EP9 0x0009 378 + #define M66592_EP10 0x000A 379 + #define M66592_EP11 0x000B 380 + #define M66592_EP12 0x000C 381 + #define M66592_EP13 0x000D 382 + #define M66592_EP14 0x000E 383 + #define M66592_EP15 0x000F 384 384 385 385 #define M66592_PIPEBUF 0x68 386 - #define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 387 - #define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10) 388 - #define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */ 386 + #define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 387 + #define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10) 388 + #define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */ 389 389 390 390 #define M66592_PIPEMAXP 0x6A 391 - #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */ 391 + #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */ 392 392 393 393 #define M66592_PIPEPERI 0x6C 394 - #define M66592_IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 395 - #define M66592_IITV 0x0007 /* b2-0: Isochronous interval */ 394 + #define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */ 395 + #define M66592_IITV 0x0007 /* b2-0: ISO interval */ 396 396 397 397 #define M66592_PIPE1CTR 0x70 398 398 #define M66592_PIPE2CTR 0x72 ··· 401 401 #define M66592_PIPE5CTR 0x78 402 402 #define M66592_PIPE6CTR 0x7A 403 403 #define M66592_PIPE7CTR 0x7C 404 - #define M66592_BSTS 0x8000 /* b15: Buffer status */ 405 - #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 406 - #define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 407 - #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 408 - #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 409 - #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 410 - #define M66592_PID 0x0003 /* b1-0: Response PID */ 404 + #define M66592_BSTS 0x8000 /* b15: Buffer status */ 405 + #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */ 406 + #define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 407 + #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 408 + #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 409 + #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 410 + #define M66592_PID 0x0003 /* b1-0: Response PID */ 411 411 412 412 #define M66592_INVALID_REG 0x7E 413 413 414 - 415 - #define __iomem 416 414 417 415 #define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2) 418 416 ··· 447 449 struct m66592 *m66592; 448 450 449 451 struct list_head queue; 450 - unsigned busy:1; 452 + unsigned busy:1; 451 453 unsigned internal_ccpl:1; /* use only control */ 452 454 453 455 /* this member can able to after m66592_enable */ ··· 475 477 struct m66592_ep *epaddr2ep[16]; 476 478 477 479 struct usb_request *ep0_req; /* for internal request */ 478 - u16 *ep0_buf; /* for internal request */ 480 + u16 ep0_data; /* for internal request */ 479 481 480 482 struct timer_list timer; 481 483 ··· 525 527 } 526 528 527 529 static inline void m66592_read_fifo(struct m66592 *m66592, 528 - unsigned long offset, 529 - void *buf, unsigned long len) 530 + unsigned long offset, 531 + void *buf, unsigned long len) 530 532 { 531 533 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 532 534 ··· 541 543 } 542 544 543 545 static inline void m66592_write_fifo(struct m66592 *m66592, 544 - unsigned long offset, 545 - void *buf, unsigned long len) 546 + unsigned long offset, 547 + void *buf, unsigned long len) 546 548 { 547 549 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 548 550 unsigned long odd = len & 0x0001; ··· 556 558 } 557 559 558 560 static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, 559 - unsigned long offset) 561 + unsigned long offset) 560 562 { 561 563 u16 tmp; 562 564 tmp = m66592_read(m66592, offset);