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Documentation: Add device tree bindings for Freescale i.MX GPC

The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

authored by

Philipp Zabel and committed by
Shawn Guo
58e4a668 52c47b63

+59
+59
Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
··· 1 + Freescale i.MX General Power Controller 2 + ======================================= 3 + 4 + The i.MX6Q General Power Control (GPC) block contains DVFS load tracking 5 + counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power 6 + domains. 7 + 8 + Required properties: 9 + - compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc" 10 + - reg: should be register base and length as documented in the 11 + datasheet 12 + - interrupts: Should contain GPC interrupt request 1 13 + - pu-supply: Link to the LDO regulator powering the PU power domain 14 + - clocks: Clock phandles to devices in the PU power domain that need 15 + to be enabled during domain power-up for reset propagation. 16 + - #power-domain-cells: Should be 1, see below: 17 + 18 + The gpc node is a power-controller as documented by the generic power domain 19 + bindings in Documentation/devicetree/bindings/power/power_domain.txt. 20 + 21 + Example: 22 + 23 + gpc: gpc@020dc000 { 24 + compatible = "fsl,imx6q-gpc"; 25 + reg = <0x020dc000 0x4000>; 26 + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, 27 + <0 90 IRQ_TYPE_LEVEL_HIGH>; 28 + pu-supply = <&reg_pu>; 29 + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 30 + <&clks IMX6QDL_CLK_GPU3D_SHADER>, 31 + <&clks IMX6QDL_CLK_GPU2D_CORE>, 32 + <&clks IMX6QDL_CLK_GPU2D_AXI>, 33 + <&clks IMX6QDL_CLK_OPENVG_AXI>, 34 + <&clks IMX6QDL_CLK_VPU_AXI>; 35 + #power-domain-cells = <1>; 36 + }; 37 + 38 + 39 + Specifying power domain for IP modules 40 + ====================================== 41 + 42 + IP cores belonging to a power domain should contain a 'power-domains' property 43 + that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying 44 + the power domain the device belongs to. 45 + 46 + Example of a device that is part of the PU power domain: 47 + 48 + vpu: vpu@02040000 { 49 + reg = <0x02040000 0x3c000>; 50 + /* ... */ 51 + power-domains = <&gpc 1>; 52 + /* ... */ 53 + }; 54 + 55 + The following DOMAIN_INDEX values are valid for i.MX6Q: 56 + ARM_DOMAIN 0 57 + PU_DOMAIN 1 58 + The following additional DOMAIN_INDEX value is valid for i.MX6SL: 59 + DISPLAY_DOMAIN 2