tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Revert "staging: tidspbridge - remove hw directory"
This reverts commit 053fdb85f56e84bff64a65601be7f72608f016da.
Signed-off-by: Felipe Contreras <felipe.contreras@gmail.com>
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
authored by
Felipe Contreras
and committed by
Omar Ramirez Luna
58c1ceb1
f5bd96bb
+1148
-2
+2
-1
drivers/staging/tidspbridge/Makefile
+2
-1
drivers/staging/tidspbridge/Makefile
···
11
11
rmgr/nldr.o rmgr/drv_interface.o
12
12
libdload = dynload/cload.o dynload/getsection.o dynload/reloc.o \
13
13
dynload/tramp.o
14
+
libhw = hw/hw_mmu.o
14
15
15
16
bridgedriver-y := $(libgen) $(libservices) $(libcore) $(libpmgr) $(librmgr) \
16
-
$(libdload)
17
+
$(libdload) $(libhw)
17
18
18
19
#Machine dependent
19
20
ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \
+1
drivers/staging/tidspbridge/core/_tiomap.h
+1
drivers/staging/tidspbridge/core/_tiomap.h
+4
drivers/staging/tidspbridge/core/io_sm.c
+4
drivers/staging/tidspbridge/core/io_sm.c
+4
drivers/staging/tidspbridge/core/tiomap3430.c
+4
drivers/staging/tidspbridge/core/tiomap3430.c
···
34
34
#include <dspbridge/drv.h>
35
35
#include <dspbridge/sync.h>
36
36
37
+
/* ------------------------------------ Hardware Abstraction Layer */
38
+
#include <hw_defs.h>
39
+
#include <hw_mmu.h>
40
+
37
41
/* ----------------------------------- Link Driver */
38
42
#include <dspbridge/dspdefs.h>
39
43
#include <dspbridge/dspchnl.h>
+4
drivers/staging/tidspbridge/core/tiomap3430_pwr.c
+4
drivers/staging/tidspbridge/core/tiomap3430_pwr.c
···
31
31
#include <dspbridge/dev.h>
32
32
#include <dspbridge/iodefs.h>
33
33
34
+
/* ------------------------------------ Hardware Abstraction Layer */
35
+
#include <hw_defs.h>
36
+
#include <hw_mmu.h>
37
+
34
38
#include <dspbridge/pwr_sh.h>
35
39
36
40
/* ----------------------------------- Bridge Driver */
+1
-1
drivers/staging/tidspbridge/core/tiomap_io.c
+1
-1
drivers/staging/tidspbridge/core/tiomap_io.c
···
143
143
ul_shm_base_virt - ul_tlb_base_virt;
144
144
ul_shm_offset_virt +=
145
145
PG_ALIGN_HIGH(ul_ext_end - ul_dyn_ext_base +
146
-
1, PAGE_SIZE * 16);
146
+
1, HW_PAGE_SIZE64KB);
147
147
dw_ext_prog_virt_mem -= ul_shm_offset_virt;
148
148
dw_ext_prog_virt_mem +=
149
149
(ul_ext_base - ul_dyn_ext_base);
+41
drivers/staging/tidspbridge/hw/EasiGlobal.h
+41
drivers/staging/tidspbridge/hw/EasiGlobal.h
···
1
+
/*
2
+
* EasiGlobal.h
3
+
*
4
+
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
5
+
*
6
+
* Copyright (C) 2007 Texas Instruments, Inc.
7
+
*
8
+
* This package is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License version 2 as
10
+
* published by the Free Software Foundation.
11
+
*
12
+
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
13
+
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
14
+
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
+
*/
16
+
17
+
#ifndef _EASIGLOBAL_H
18
+
#define _EASIGLOBAL_H
19
+
#include <linux/types.h>
20
+
21
+
/*
22
+
* DEFINE: READ_ONLY, WRITE_ONLY & READ_WRITE
23
+
*
24
+
* DESCRIPTION: Defines used to describe register types for EASI-checker tests.
25
+
*/
26
+
27
+
#define READ_ONLY 1
28
+
#define WRITE_ONLY 2
29
+
#define READ_WRITE 3
30
+
31
+
/*
32
+
* MACRO: _DEBUG_LEVEL1_EASI
33
+
*
34
+
* DESCRIPTION: A MACRO which can be used to indicate that a particular beach
35
+
* register access function was called.
36
+
*
37
+
* NOTE: We currently dont use this functionality.
38
+
*/
39
+
#define _DEBUG_LEVEL1_EASI(easi_num) ((void)0)
40
+
41
+
#endif /* _EASIGLOBAL_H */
+76
drivers/staging/tidspbridge/hw/MMUAccInt.h
+76
drivers/staging/tidspbridge/hw/MMUAccInt.h
···
1
+
/*
2
+
* MMUAccInt.h
3
+
*
4
+
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
5
+
*
6
+
* Copyright (C) 2007 Texas Instruments, Inc.
7
+
*
8
+
* This package is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License version 2 as
10
+
* published by the Free Software Foundation.
11
+
*
12
+
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
13
+
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
14
+
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
+
*/
16
+
17
+
#ifndef _MMU_ACC_INT_H
18
+
#define _MMU_ACC_INT_H
19
+
20
+
/* Mappings of level 1 EASI function numbers to function names */
21
+
22
+
#define EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32 (MMU_BASE_EASIL1 + 3)
23
+
#define EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32 (MMU_BASE_EASIL1 + 17)
24
+
#define EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32 (MMU_BASE_EASIL1 + 39)
25
+
#define EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 51)
26
+
#define EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32 (MMU_BASE_EASIL1 + 102)
27
+
#define EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 103)
28
+
#define EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32 (MMU_BASE_EASIL1 + 156)
29
+
#define EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32 (MMU_BASE_EASIL1 + 174)
30
+
#define EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 180)
31
+
#define EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 190)
32
+
#define EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32 (MMU_BASE_EASIL1 + 194)
33
+
#define EASIL1_MMUMMU_TTB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 198)
34
+
#define EASIL1_MMUMMU_LOCK_READ_REGISTER32 (MMU_BASE_EASIL1 + 203)
35
+
#define EASIL1_MMUMMU_LOCK_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 204)
36
+
#define EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32 (MMU_BASE_EASIL1 + 205)
37
+
#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32 (MMU_BASE_EASIL1 + 209)
38
+
#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32 (MMU_BASE_EASIL1 + 211)
39
+
#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32 (MMU_BASE_EASIL1 + 212)
40
+
#define EASIL1_MMUMMU_LD_TLB_READ_REGISTER32 (MMU_BASE_EASIL1 + 213)
41
+
#define EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 214)
42
+
#define EASIL1_MMUMMU_CAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 226)
43
+
#define EASIL1_MMUMMU_RAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 268)
44
+
#define EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 322)
45
+
46
+
/* Register offset address definitions */
47
+
#define MMU_MMU_SYSCONFIG_OFFSET 0x10
48
+
#define MMU_MMU_IRQSTATUS_OFFSET 0x18
49
+
#define MMU_MMU_IRQENABLE_OFFSET 0x1c
50
+
#define MMU_MMU_WALKING_ST_OFFSET 0x40
51
+
#define MMU_MMU_CNTL_OFFSET 0x44
52
+
#define MMU_MMU_FAULT_AD_OFFSET 0x48
53
+
#define MMU_MMU_TTB_OFFSET 0x4c
54
+
#define MMU_MMU_LOCK_OFFSET 0x50
55
+
#define MMU_MMU_LD_TLB_OFFSET 0x54
56
+
#define MMU_MMU_CAM_OFFSET 0x58
57
+
#define MMU_MMU_RAM_OFFSET 0x5c
58
+
#define MMU_MMU_GFLUSH_OFFSET 0x60
59
+
#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
60
+
/* Bitfield mask and offset declarations */
61
+
#define MMU_MMU_SYSCONFIG_IDLE_MODE_MASK 0x18
62
+
#define MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET 3
63
+
#define MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK 0x1
64
+
#define MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET 0
65
+
#define MMU_MMU_WALKING_ST_TWL_RUNNING_MASK 0x1
66
+
#define MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET 0
67
+
#define MMU_MMU_CNTL_TWL_ENABLE_MASK 0x4
68
+
#define MMU_MMU_CNTL_TWL_ENABLE_OFFSET 2
69
+
#define MMU_MMU_CNTL_MMU_ENABLE_MASK 0x2
70
+
#define MMU_MMU_CNTL_MMU_ENABLE_OFFSET 1
71
+
#define MMU_MMU_LOCK_BASE_VALUE_MASK 0xfc00
72
+
#define MMU_MMU_LOCK_BASE_VALUE_OFFSET 10
73
+
#define MMU_MMU_LOCK_CURRENT_VICTIM_MASK 0x3f0
74
+
#define MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET 4
75
+
76
+
#endif /* _MMU_ACC_INT_H */
+225
drivers/staging/tidspbridge/hw/MMURegAcM.h
+225
drivers/staging/tidspbridge/hw/MMURegAcM.h
···
1
+
/*
2
+
* MMURegAcM.h
3
+
*
4
+
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
5
+
*
6
+
* Copyright (C) 2007 Texas Instruments, Inc.
7
+
*
8
+
* This package is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License version 2 as
10
+
* published by the Free Software Foundation.
11
+
*
12
+
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
13
+
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
14
+
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
+
*/
16
+
17
+
#ifndef _MMU_REG_ACM_H
18
+
#define _MMU_REG_ACM_H
19
+
20
+
#include <linux/io.h>
21
+
#include <EasiGlobal.h>
22
+
23
+
#include "MMUAccInt.h"
24
+
25
+
#if defined(USE_LEVEL_1_MACROS)
26
+
27
+
#define MMUMMU_SYSCONFIG_READ_REGISTER32(base_address)\
28
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32),\
29
+
__raw_readl((base_address)+MMU_MMU_SYSCONFIG_OFFSET))
30
+
31
+
#define MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32(base_address, value)\
32
+
{\
33
+
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
34
+
register u32 data = __raw_readl((base_address)+offset);\
35
+
register u32 new_value = (value);\
36
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32);\
37
+
data &= ~(MMU_MMU_SYSCONFIG_IDLE_MODE_MASK);\
38
+
new_value <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\
39
+
new_value &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\
40
+
new_value |= data;\
41
+
__raw_writel(new_value, base_address+offset);\
42
+
}
43
+
44
+
#define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(base_address, value)\
45
+
{\
46
+
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
47
+
register u32 data = __raw_readl((base_address)+offset);\
48
+
register u32 new_value = (value);\
49
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32);\
50
+
data &= ~(MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK);\
51
+
new_value <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\
52
+
new_value &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\
53
+
new_value |= data;\
54
+
__raw_writel(new_value, base_address+offset);\
55
+
}
56
+
57
+
#define MMUMMU_IRQSTATUS_READ_REGISTER32(base_address)\
58
+
(_DEBUG_LEVEL1_EASI(easil1_mmummu_irqstatus_read_register32),\
59
+
__raw_readl((base_address)+MMU_MMU_IRQSTATUS_OFFSET))
60
+
61
+
#define MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, value)\
62
+
{\
63
+
const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
64
+
register u32 new_value = (value);\
65
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32);\
66
+
__raw_writel(new_value, (base_address)+offset);\
67
+
}
68
+
69
+
#define MMUMMU_IRQENABLE_READ_REGISTER32(base_address)\
70
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32),\
71
+
__raw_readl((base_address)+MMU_MMU_IRQENABLE_OFFSET))
72
+
73
+
#define MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, value)\
74
+
{\
75
+
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
76
+
register u32 new_value = (value);\
77
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32);\
78
+
__raw_writel(new_value, (base_address)+offset);\
79
+
}
80
+
81
+
#define MMUMMU_WALKING_STTWL_RUNNING_READ32(base_address)\
82
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32),\
83
+
(((__raw_readl(((base_address)+(MMU_MMU_WALKING_ST_OFFSET))))\
84
+
& MMU_MMU_WALKING_ST_TWL_RUNNING_MASK) >>\
85
+
MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET))
86
+
87
+
#define MMUMMU_CNTLTWL_ENABLE_READ32(base_address)\
88
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32),\
89
+
(((__raw_readl(((base_address)+(MMU_MMU_CNTL_OFFSET)))) &\
90
+
MMU_MMU_CNTL_TWL_ENABLE_MASK) >>\
91
+
MMU_MMU_CNTL_TWL_ENABLE_OFFSET))
92
+
93
+
#define MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, value)\
94
+
{\
95
+
const u32 offset = MMU_MMU_CNTL_OFFSET;\
96
+
register u32 data = __raw_readl((base_address)+offset);\
97
+
register u32 new_value = (value);\
98
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32);\
99
+
data &= ~(MMU_MMU_CNTL_TWL_ENABLE_MASK);\
100
+
new_value <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\
101
+
new_value &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\
102
+
new_value |= data;\
103
+
__raw_writel(new_value, base_address+offset);\
104
+
}
105
+
106
+
#define MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, value)\
107
+
{\
108
+
const u32 offset = MMU_MMU_CNTL_OFFSET;\
109
+
register u32 data = __raw_readl((base_address)+offset);\
110
+
register u32 new_value = (value);\
111
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32);\
112
+
data &= ~(MMU_MMU_CNTL_MMU_ENABLE_MASK);\
113
+
new_value <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\
114
+
new_value &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\
115
+
new_value |= data;\
116
+
__raw_writel(new_value, base_address+offset);\
117
+
}
118
+
119
+
#define MMUMMU_FAULT_AD_READ_REGISTER32(base_address)\
120
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32),\
121
+
__raw_readl((base_address)+MMU_MMU_FAULT_AD_OFFSET))
122
+
123
+
#define MMUMMU_TTB_WRITE_REGISTER32(base_address, value)\
124
+
{\
125
+
const u32 offset = MMU_MMU_TTB_OFFSET;\
126
+
register u32 new_value = (value);\
127
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_TTB_WRITE_REGISTER32);\
128
+
__raw_writel(new_value, (base_address)+offset);\
129
+
}
130
+
131
+
#define MMUMMU_LOCK_READ_REGISTER32(base_address)\
132
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_READ_REGISTER32),\
133
+
__raw_readl((base_address)+MMU_MMU_LOCK_OFFSET))
134
+
135
+
#define MMUMMU_LOCK_WRITE_REGISTER32(base_address, value)\
136
+
{\
137
+
const u32 offset = MMU_MMU_LOCK_OFFSET;\
138
+
register u32 new_value = (value);\
139
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_WRITE_REGISTER32);\
140
+
__raw_writel(new_value, (base_address)+offset);\
141
+
}
142
+
143
+
#define MMUMMU_LOCK_BASE_VALUE_READ32(base_address)\
144
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32),\
145
+
(((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
146
+
MMU_MMU_LOCK_BASE_VALUE_MASK) >>\
147
+
MMU_MMU_LOCK_BASE_VALUE_OFFSET))
148
+
149
+
#define MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, value)\
150
+
{\
151
+
const u32 offset = MMU_MMU_LOCK_OFFSET;\
152
+
register u32 data = __raw_readl((base_address)+offset);\
153
+
register u32 new_value = (value);\
154
+
_DEBUG_LEVEL1_EASI(easil1_mmummu_lock_base_value_write32);\
155
+
data &= ~(MMU_MMU_LOCK_BASE_VALUE_MASK);\
156
+
new_value <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\
157
+
new_value &= MMU_MMU_LOCK_BASE_VALUE_MASK;\
158
+
new_value |= data;\
159
+
__raw_writel(new_value, base_address+offset);\
160
+
}
161
+
162
+
#define MMUMMU_LOCK_CURRENT_VICTIM_READ32(base_address)\
163
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32),\
164
+
(((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
165
+
MMU_MMU_LOCK_CURRENT_VICTIM_MASK) >>\
166
+
MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET))
167
+
168
+
#define MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, value)\
169
+
{\
170
+
const u32 offset = MMU_MMU_LOCK_OFFSET;\
171
+
register u32 data = __raw_readl((base_address)+offset);\
172
+
register u32 new_value = (value);\
173
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32);\
174
+
data &= ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK);\
175
+
new_value <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\
176
+
new_value &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\
177
+
new_value |= data;\
178
+
__raw_writel(new_value, base_address+offset);\
179
+
}
180
+
181
+
#define MMUMMU_LOCK_CURRENT_VICTIM_SET32(var, value)\
182
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32),\
183
+
(((var) & ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK)) |\
184
+
(((value) << MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET) &\
185
+
MMU_MMU_LOCK_CURRENT_VICTIM_MASK)))
186
+
187
+
#define MMUMMU_LD_TLB_READ_REGISTER32(base_address)\
188
+
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_READ_REGISTER32),\
189
+
__raw_readl((base_address)+MMU_MMU_LD_TLB_OFFSET))
190
+
191
+
#define MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, value)\
192
+
{\
193
+
const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
194
+
register u32 new_value = (value);\
195
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32);\
196
+
__raw_writel(new_value, (base_address)+offset);\
197
+
}
198
+
199
+
#define MMUMMU_CAM_WRITE_REGISTER32(base_address, value)\
200
+
{\
201
+
const u32 offset = MMU_MMU_CAM_OFFSET;\
202
+
register u32 new_value = (value);\
203
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CAM_WRITE_REGISTER32);\
204
+
__raw_writel(new_value, (base_address)+offset);\
205
+
}
206
+
207
+
#define MMUMMU_RAM_WRITE_REGISTER32(base_address, value)\
208
+
{\
209
+
const u32 offset = MMU_MMU_RAM_OFFSET;\
210
+
register u32 new_value = (value);\
211
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_RAM_WRITE_REGISTER32);\
212
+
__raw_writel(new_value, (base_address)+offset);\
213
+
}
214
+
215
+
#define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, value)\
216
+
{\
217
+
const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
218
+
register u32 new_value = (value);\
219
+
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32);\
220
+
__raw_writel(new_value, (base_address)+offset);\
221
+
}
222
+
223
+
#endif /* USE_LEVEL_1_MACROS */
224
+
225
+
#endif /* _MMU_REG_ACM_H */
+58
drivers/staging/tidspbridge/hw/hw_defs.h
+58
drivers/staging/tidspbridge/hw/hw_defs.h
···
1
+
/*
2
+
* hw_defs.h
3
+
*
4
+
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
5
+
*
6
+
* Global HW definitions
7
+
*
8
+
* Copyright (C) 2007 Texas Instruments, Inc.
9
+
*
10
+
* This package is free software; you can redistribute it and/or modify
11
+
* it under the terms of the GNU General Public License version 2 as
12
+
* published by the Free Software Foundation.
13
+
*
14
+
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15
+
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16
+
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17
+
*/
18
+
19
+
#ifndef _HW_DEFS_H
20
+
#define _HW_DEFS_H
21
+
22
+
/* Page size */
23
+
#define HW_PAGE_SIZE4KB 0x1000
24
+
#define HW_PAGE_SIZE64KB 0x10000
25
+
#define HW_PAGE_SIZE1MB 0x100000
26
+
#define HW_PAGE_SIZE16MB 0x1000000
27
+
28
+
/* hw_status: return type for HW API */
29
+
typedef long hw_status;
30
+
31
+
/* Macro used to set and clear any bit */
32
+
#define HW_CLEAR 0
33
+
#define HW_SET 1
34
+
35
+
/* hw_endianism_t: Enumerated Type used to specify the endianism
36
+
* Do NOT change these values. They are used as bit fields. */
37
+
enum hw_endianism_t {
38
+
HW_LITTLE_ENDIAN,
39
+
HW_BIG_ENDIAN
40
+
};
41
+
42
+
/* hw_element_size_t: Enumerated Type used to specify the element size
43
+
* Do NOT change these values. They are used as bit fields. */
44
+
enum hw_element_size_t {
45
+
HW_ELEM_SIZE8BIT,
46
+
HW_ELEM_SIZE16BIT,
47
+
HW_ELEM_SIZE32BIT,
48
+
HW_ELEM_SIZE64BIT
49
+
};
50
+
51
+
/* hw_idle_mode_t: Enumerated Type used to specify Idle modes */
52
+
enum hw_idle_mode_t {
53
+
HW_FORCE_IDLE,
54
+
HW_NO_IDLE,
55
+
HW_SMART_IDLE
56
+
};
57
+
58
+
#endif /* _HW_DEFS_H */
+562
drivers/staging/tidspbridge/hw/hw_mmu.c
+562
drivers/staging/tidspbridge/hw/hw_mmu.c
···
1
+
/*
2
+
* hw_mmu.c
3
+
*
4
+
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
5
+
*
6
+
* API definitions to setup MMU TLB and PTE
7
+
*
8
+
* Copyright (C) 2007 Texas Instruments, Inc.
9
+
*
10
+
* This package is free software; you can redistribute it and/or modify
11
+
* it under the terms of the GNU General Public License version 2 as
12
+
* published by the Free Software Foundation.
13
+
*
14
+
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15
+
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16
+
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17
+
*/
18
+
19
+
#include <linux/io.h>
20
+
#include "MMURegAcM.h"
21
+
#include <hw_defs.h>
22
+
#include <hw_mmu.h>
23
+
#include <linux/types.h>
24
+
#include <linux/err.h>
25
+
26
+
#define MMU_BASE_VAL_MASK 0xFC00
27
+
#define MMU_PAGE_MAX 3
28
+
#define MMU_ELEMENTSIZE_MAX 3
29
+
#define MMU_ADDR_MASK 0xFFFFF000
30
+
#define MMU_TTB_MASK 0xFFFFC000
31
+
#define MMU_SECTION_ADDR_MASK 0xFFF00000
32
+
#define MMU_SSECTION_ADDR_MASK 0xFF000000
33
+
#define MMU_PAGE_TABLE_MASK 0xFFFFFC00
34
+
#define MMU_LARGE_PAGE_MASK 0xFFFF0000
35
+
#define MMU_SMALL_PAGE_MASK 0xFFFFF000
36
+
37
+
#define MMU_LOAD_TLB 0x00000001
38
+
#define MMU_GFLUSH 0x60
39
+
40
+
/*
41
+
* hw_mmu_page_size_t: Enumerated Type used to specify the MMU Page Size(SLSS)
42
+
*/
43
+
enum hw_mmu_page_size_t {
44
+
HW_MMU_SECTION,
45
+
HW_MMU_LARGE_PAGE,
46
+
HW_MMU_SMALL_PAGE,
47
+
HW_MMU_SUPERSECTION
48
+
};
49
+
50
+
/*
51
+
* FUNCTION : mmu_flush_entry
52
+
*
53
+
* INPUTS:
54
+
*
55
+
* Identifier : base_address
56
+
* Type : const u32
57
+
* Description : Base Address of instance of MMU module
58
+
*
59
+
* RETURNS:
60
+
*
61
+
* Type : hw_status
62
+
* Description : 0 -- No errors occured
63
+
* RET_BAD_NULL_PARAM -- A Pointer
64
+
* Paramater was set to NULL
65
+
*
66
+
* PURPOSE: : Flush the TLB entry pointed by the
67
+
* lock counter register
68
+
* even if this entry is set protected
69
+
*
70
+
* METHOD: : Check the Input parameter and Flush a
71
+
* single entry in the TLB.
72
+
*/
73
+
static hw_status mmu_flush_entry(const void __iomem *base_address);
74
+
75
+
/*
76
+
* FUNCTION : mmu_set_cam_entry
77
+
*
78
+
* INPUTS:
79
+
*
80
+
* Identifier : base_address
81
+
* TypE : const u32
82
+
* Description : Base Address of instance of MMU module
83
+
*
84
+
* Identifier : page_sz
85
+
* TypE : const u32
86
+
* Description : It indicates the page size
87
+
*
88
+
* Identifier : preserved_bit
89
+
* Type : const u32
90
+
* Description : It indicates the TLB entry is preserved entry
91
+
* or not
92
+
*
93
+
* Identifier : valid_bit
94
+
* Type : const u32
95
+
* Description : It indicates the TLB entry is valid entry or not
96
+
*
97
+
*
98
+
* Identifier : virtual_addr_tag
99
+
* Type : const u32
100
+
* Description : virtual Address
101
+
*
102
+
* RETURNS:
103
+
*
104
+
* Type : hw_status
105
+
* Description : 0 -- No errors occured
106
+
* RET_BAD_NULL_PARAM -- A Pointer Paramater
107
+
* was set to NULL
108
+
* RET_PARAM_OUT_OF_RANGE -- Input Parameter out
109
+
* of Range
110
+
*
111
+
* PURPOSE: : Set MMU_CAM reg
112
+
*
113
+
* METHOD: : Check the Input parameters and set the CAM entry.
114
+
*/
115
+
static hw_status mmu_set_cam_entry(const void __iomem *base_address,
116
+
const u32 page_sz,
117
+
const u32 preserved_bit,
118
+
const u32 valid_bit,
119
+
const u32 virtual_addr_tag);
120
+
121
+
/*
122
+
* FUNCTION : mmu_set_ram_entry
123
+
*
124
+
* INPUTS:
125
+
*
126
+
* Identifier : base_address
127
+
* Type : const u32
128
+
* Description : Base Address of instance of MMU module
129
+
*
130
+
* Identifier : physical_addr
131
+
* Type : const u32
132
+
* Description : Physical Address to which the corresponding
133
+
* virtual Address shouldpoint
134
+
*
135
+
* Identifier : endianism
136
+
* Type : hw_endianism_t
137
+
* Description : endianism for the given page
138
+
*
139
+
* Identifier : element_size
140
+
* Type : hw_element_size_t
141
+
* Description : The element size ( 8,16, 32 or 64 bit)
142
+
*
143
+
* Identifier : mixed_size
144
+
* Type : hw_mmu_mixed_size_t
145
+
* Description : Element Size to follow CPU or TLB
146
+
*
147
+
* RETURNS:
148
+
*
149
+
* Type : hw_status
150
+
* Description : 0 -- No errors occured
151
+
* RET_BAD_NULL_PARAM -- A Pointer Paramater
152
+
* was set to NULL
153
+
* RET_PARAM_OUT_OF_RANGE -- Input Parameter
154
+
* out of Range
155
+
*
156
+
* PURPOSE: : Set MMU_CAM reg
157
+
*
158
+
* METHOD: : Check the Input parameters and set the RAM entry.
159
+
*/
160
+
static hw_status mmu_set_ram_entry(const void __iomem *base_address,
161
+
const u32 physical_addr,
162
+
enum hw_endianism_t endianism,
163
+
enum hw_element_size_t element_size,
164
+
enum hw_mmu_mixed_size_t mixed_size);
165
+
166
+
/* HW FUNCTIONS */
167
+
168
+
hw_status hw_mmu_enable(const void __iomem *base_address)
169
+
{
170
+
hw_status status = 0;
171
+
172
+
MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_SET);
173
+
174
+
return status;
175
+
}
176
+
177
+
hw_status hw_mmu_disable(const void __iomem *base_address)
178
+
{
179
+
hw_status status = 0;
180
+
181
+
MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_CLEAR);
182
+
183
+
return status;
184
+
}
185
+
186
+
hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
187
+
u32 num_locked_entries)
188
+
{
189
+
hw_status status = 0;
190
+
191
+
MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, num_locked_entries);
192
+
193
+
return status;
194
+
}
195
+
196
+
hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
197
+
u32 victim_entry_num)
198
+
{
199
+
hw_status status = 0;
200
+
201
+
MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, victim_entry_num);
202
+
203
+
return status;
204
+
}
205
+
206
+
hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
207
+
{
208
+
hw_status status = 0;
209
+
210
+
MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irq_mask);
211
+
212
+
return status;
213
+
}
214
+
215
+
hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
216
+
{
217
+
hw_status status = 0;
218
+
u32 irq_reg;
219
+
220
+
irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
221
+
222
+
MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg & ~irq_mask);
223
+
224
+
return status;
225
+
}
226
+
227
+
hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
228
+
{
229
+
hw_status status = 0;
230
+
u32 irq_reg;
231
+
232
+
irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
233
+
234
+
MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg | irq_mask);
235
+
236
+
return status;
237
+
}
238
+
239
+
hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
240
+
{
241
+
hw_status status = 0;
242
+
243
+
*irq_mask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address);
244
+
245
+
return status;
246
+
}
247
+
248
+
hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
249
+
{
250
+
hw_status status = 0;
251
+
252
+
/* read values from register */
253
+
*addr = MMUMMU_FAULT_AD_READ_REGISTER32(base_address);
254
+
255
+
return status;
256
+
}
257
+
258
+
hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
259
+
{
260
+
hw_status status = 0;
261
+
u32 load_ttb;
262
+
263
+
load_ttb = ttb_phys_addr & ~0x7FUL;
264
+
/* write values to register */
265
+
MMUMMU_TTB_WRITE_REGISTER32(base_address, load_ttb);
266
+
267
+
return status;
268
+
}
269
+
270
+
hw_status hw_mmu_twl_enable(const void __iomem *base_address)
271
+
{
272
+
hw_status status = 0;
273
+
274
+
MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_SET);
275
+
276
+
return status;
277
+
}
278
+
279
+
hw_status hw_mmu_twl_disable(const void __iomem *base_address)
280
+
{
281
+
hw_status status = 0;
282
+
283
+
MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_CLEAR);
284
+
285
+
return status;
286
+
}
287
+
288
+
hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr,
289
+
u32 page_sz)
290
+
{
291
+
hw_status status = 0;
292
+
u32 virtual_addr_tag;
293
+
enum hw_mmu_page_size_t pg_size_bits;
294
+
295
+
switch (page_sz) {
296
+
case HW_PAGE_SIZE4KB:
297
+
pg_size_bits = HW_MMU_SMALL_PAGE;
298
+
break;
299
+
300
+
case HW_PAGE_SIZE64KB:
301
+
pg_size_bits = HW_MMU_LARGE_PAGE;
302
+
break;
303
+
304
+
case HW_PAGE_SIZE1MB:
305
+
pg_size_bits = HW_MMU_SECTION;
306
+
break;
307
+
308
+
case HW_PAGE_SIZE16MB:
309
+
pg_size_bits = HW_MMU_SUPERSECTION;
310
+
break;
311
+
312
+
default:
313
+
return -EINVAL;
314
+
}
315
+
316
+
/* Generate the 20-bit tag from virtual address */
317
+
virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
318
+
319
+
mmu_set_cam_entry(base_address, pg_size_bits, 0, 0, virtual_addr_tag);
320
+
321
+
mmu_flush_entry(base_address);
322
+
323
+
return status;
324
+
}
325
+
326
+
hw_status hw_mmu_tlb_add(const void __iomem *base_address,
327
+
u32 physical_addr,
328
+
u32 virtual_addr,
329
+
u32 page_sz,
330
+
u32 entry_num,
331
+
struct hw_mmu_map_attrs_t *map_attrs,
332
+
s8 preserved_bit, s8 valid_bit)
333
+
{
334
+
hw_status status = 0;
335
+
u32 lock_reg;
336
+
u32 virtual_addr_tag;
337
+
enum hw_mmu_page_size_t mmu_pg_size;
338
+
339
+
/*Check the input Parameters */
340
+
switch (page_sz) {
341
+
case HW_PAGE_SIZE4KB:
342
+
mmu_pg_size = HW_MMU_SMALL_PAGE;
343
+
break;
344
+
345
+
case HW_PAGE_SIZE64KB:
346
+
mmu_pg_size = HW_MMU_LARGE_PAGE;
347
+
break;
348
+
349
+
case HW_PAGE_SIZE1MB:
350
+
mmu_pg_size = HW_MMU_SECTION;
351
+
break;
352
+
353
+
case HW_PAGE_SIZE16MB:
354
+
mmu_pg_size = HW_MMU_SUPERSECTION;
355
+
break;
356
+
357
+
default:
358
+
return -EINVAL;
359
+
}
360
+
361
+
lock_reg = MMUMMU_LOCK_READ_REGISTER32(base_address);
362
+
363
+
/* Generate the 20-bit tag from virtual address */
364
+
virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
365
+
366
+
/* Write the fields in the CAM Entry Register */
367
+
mmu_set_cam_entry(base_address, mmu_pg_size, preserved_bit, valid_bit,
368
+
virtual_addr_tag);
369
+
370
+
/* Write the different fields of the RAM Entry Register */
371
+
/* endianism of the page,Element Size of the page (8, 16, 32, 64 bit) */
372
+
mmu_set_ram_entry(base_address, physical_addr, map_attrs->endianism,
373
+
map_attrs->element_size, map_attrs->mixed_size);
374
+
375
+
/* Update the MMU Lock Register */
376
+
/* currentVictim between lockedBaseValue and (MMU_Entries_Number - 1) */
377
+
MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, entry_num);
378
+
379
+
/* Enable loading of an entry in TLB by writing 1
380
+
into LD_TLB_REG register */
381
+
MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, MMU_LOAD_TLB);
382
+
383
+
MMUMMU_LOCK_WRITE_REGISTER32(base_address, lock_reg);
384
+
385
+
return status;
386
+
}
387
+
388
+
hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
389
+
u32 physical_addr,
390
+
u32 virtual_addr,
391
+
u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs)
392
+
{
393
+
hw_status status = 0;
394
+
u32 pte_addr, pte_val;
395
+
s32 num_entries = 1;
396
+
397
+
switch (page_sz) {
398
+
case HW_PAGE_SIZE4KB:
399
+
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
400
+
virtual_addr &
401
+
MMU_SMALL_PAGE_MASK);
402
+
pte_val =
403
+
((physical_addr & MMU_SMALL_PAGE_MASK) |
404
+
(map_attrs->endianism << 9) | (map_attrs->
405
+
element_size << 4) |
406
+
(map_attrs->mixed_size << 11) | 2);
407
+
break;
408
+
409
+
case HW_PAGE_SIZE64KB:
410
+
num_entries = 16;
411
+
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
412
+
virtual_addr &
413
+
MMU_LARGE_PAGE_MASK);
414
+
pte_val =
415
+
((physical_addr & MMU_LARGE_PAGE_MASK) |
416
+
(map_attrs->endianism << 9) | (map_attrs->
417
+
element_size << 4) |
418
+
(map_attrs->mixed_size << 11) | 1);
419
+
break;
420
+
421
+
case HW_PAGE_SIZE1MB:
422
+
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
423
+
virtual_addr &
424
+
MMU_SECTION_ADDR_MASK);
425
+
pte_val =
426
+
((((physical_addr & MMU_SECTION_ADDR_MASK) |
427
+
(map_attrs->endianism << 15) | (map_attrs->
428
+
element_size << 10) |
429
+
(map_attrs->mixed_size << 17)) & ~0x40000) | 0x2);
430
+
break;
431
+
432
+
case HW_PAGE_SIZE16MB:
433
+
num_entries = 16;
434
+
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
435
+
virtual_addr &
436
+
MMU_SSECTION_ADDR_MASK);
437
+
pte_val =
438
+
(((physical_addr & MMU_SSECTION_ADDR_MASK) |
439
+
(map_attrs->endianism << 15) | (map_attrs->
440
+
element_size << 10) |
441
+
(map_attrs->mixed_size << 17)
442
+
) | 0x40000 | 0x2);
443
+
break;
444
+
445
+
case HW_MMU_COARSE_PAGE_SIZE:
446
+
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
447
+
virtual_addr &
448
+
MMU_SECTION_ADDR_MASK);
449
+
pte_val = (physical_addr & MMU_PAGE_TABLE_MASK) | 1;
450
+
break;
451
+
452
+
default:
453
+
return -EINVAL;
454
+
}
455
+
456
+
while (--num_entries >= 0)
457
+
((u32 *) pte_addr)[num_entries] = pte_val;
458
+
459
+
return status;
460
+
}
461
+
462
+
hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size)
463
+
{
464
+
hw_status status = 0;
465
+
u32 pte_addr;
466
+
s32 num_entries = 1;
467
+
468
+
switch (page_size) {
469
+
case HW_PAGE_SIZE4KB:
470
+
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
471
+
virtual_addr &
472
+
MMU_SMALL_PAGE_MASK);
473
+
break;
474
+
475
+
case HW_PAGE_SIZE64KB:
476
+
num_entries = 16;
477
+
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
478
+
virtual_addr &
479
+
MMU_LARGE_PAGE_MASK);
480
+
break;
481
+
482
+
case HW_PAGE_SIZE1MB:
483
+
case HW_MMU_COARSE_PAGE_SIZE:
484
+
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
485
+
virtual_addr &
486
+
MMU_SECTION_ADDR_MASK);
487
+
break;
488
+
489
+
case HW_PAGE_SIZE16MB:
490
+
num_entries = 16;
491
+
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
492
+
virtual_addr &
493
+
MMU_SSECTION_ADDR_MASK);
494
+
break;
495
+
496
+
default:
497
+
return -EINVAL;
498
+
}
499
+
500
+
while (--num_entries >= 0)
501
+
((u32 *) pte_addr)[num_entries] = 0;
502
+
503
+
return status;
504
+
}
505
+
506
+
/* mmu_flush_entry */
507
+
static hw_status mmu_flush_entry(const void __iomem *base_address)
508
+
{
509
+
hw_status status = 0;
510
+
u32 flush_entry_data = 0x1;
511
+
512
+
/* write values to register */
513
+
MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, flush_entry_data);
514
+
515
+
return status;
516
+
}
517
+
518
+
/* mmu_set_cam_entry */
519
+
static hw_status mmu_set_cam_entry(const void __iomem *base_address,
520
+
const u32 page_sz,
521
+
const u32 preserved_bit,
522
+
const u32 valid_bit,
523
+
const u32 virtual_addr_tag)
524
+
{
525
+
hw_status status = 0;
526
+
u32 mmu_cam_reg;
527
+
528
+
mmu_cam_reg = (virtual_addr_tag << 12);
529
+
mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (valid_bit << 2) |
530
+
(preserved_bit << 3);
531
+
532
+
/* write values to register */
533
+
MMUMMU_CAM_WRITE_REGISTER32(base_address, mmu_cam_reg);
534
+
535
+
return status;
536
+
}
537
+
538
+
/* mmu_set_ram_entry */
539
+
static hw_status mmu_set_ram_entry(const void __iomem *base_address,
540
+
const u32 physical_addr,
541
+
enum hw_endianism_t endianism,
542
+
enum hw_element_size_t element_size,
543
+
enum hw_mmu_mixed_size_t mixed_size)
544
+
{
545
+
hw_status status = 0;
546
+
u32 mmu_ram_reg;
547
+
548
+
mmu_ram_reg = (physical_addr & MMU_ADDR_MASK);
549
+
mmu_ram_reg = (mmu_ram_reg) | ((endianism << 9) | (element_size << 7) |
550
+
(mixed_size << 6));
551
+
552
+
/* write values to register */
553
+
MMUMMU_RAM_WRITE_REGISTER32(base_address, mmu_ram_reg);
554
+
555
+
return status;
556
+
557
+
}
558
+
559
+
void hw_mmu_tlb_flush_all(const void __iomem *base)
560
+
{
561
+
__raw_writeb(1, base + MMU_GFLUSH);
562
+
}
+163
drivers/staging/tidspbridge/hw/hw_mmu.h
+163
drivers/staging/tidspbridge/hw/hw_mmu.h
···
1
+
/*
2
+
* hw_mmu.h
3
+
*
4
+
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
5
+
*
6
+
* MMU types and API declarations
7
+
*
8
+
* Copyright (C) 2007 Texas Instruments, Inc.
9
+
*
10
+
* This package is free software; you can redistribute it and/or modify
11
+
* it under the terms of the GNU General Public License version 2 as
12
+
* published by the Free Software Foundation.
13
+
*
14
+
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15
+
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16
+
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17
+
*/
18
+
19
+
#ifndef _HW_MMU_H
20
+
#define _HW_MMU_H
21
+
22
+
#include <linux/types.h>
23
+
24
+
/* Bitmasks for interrupt sources */
25
+
#define HW_MMU_TRANSLATION_FAULT 0x2
26
+
#define HW_MMU_ALL_INTERRUPTS 0x1F
27
+
28
+
#define HW_MMU_COARSE_PAGE_SIZE 0x400
29
+
30
+
/* hw_mmu_mixed_size_t: Enumerated Type used to specify whether to follow
31
+
CPU/TLB Element size */
32
+
enum hw_mmu_mixed_size_t {
33
+
HW_MMU_TLBES,
34
+
HW_MMU_CPUES
35
+
};
36
+
37
+
/* hw_mmu_map_attrs_t: Struct containing MMU mapping attributes */
38
+
struct hw_mmu_map_attrs_t {
39
+
enum hw_endianism_t endianism;
40
+
enum hw_element_size_t element_size;
41
+
enum hw_mmu_mixed_size_t mixed_size;
42
+
bool donotlockmpupage;
43
+
};
44
+
45
+
extern hw_status hw_mmu_enable(const void __iomem *base_address);
46
+
47
+
extern hw_status hw_mmu_disable(const void __iomem *base_address);
48
+
49
+
extern hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
50
+
u32 num_locked_entries);
51
+
52
+
extern hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
53
+
u32 victim_entry_num);
54
+
55
+
/* For MMU faults */
56
+
extern hw_status hw_mmu_event_ack(const void __iomem *base_address,
57
+
u32 irq_mask);
58
+
59
+
extern hw_status hw_mmu_event_disable(const void __iomem *base_address,
60
+
u32 irq_mask);
61
+
62
+
extern hw_status hw_mmu_event_enable(const void __iomem *base_address,
63
+
u32 irq_mask);
64
+
65
+
extern hw_status hw_mmu_event_status(const void __iomem *base_address,
66
+
u32 *irq_mask);
67
+
68
+
extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address,
69
+
u32 *addr);
70
+
71
+
/* Set the TT base address */
72
+
extern hw_status hw_mmu_ttb_set(const void __iomem *base_address,
73
+
u32 ttb_phys_addr);
74
+
75
+
extern hw_status hw_mmu_twl_enable(const void __iomem *base_address);
76
+
77
+
extern hw_status hw_mmu_twl_disable(const void __iomem *base_address);
78
+
79
+
extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address,
80
+
u32 virtual_addr, u32 page_sz);
81
+
82
+
extern hw_status hw_mmu_tlb_add(const void __iomem *base_address,
83
+
u32 physical_addr,
84
+
u32 virtual_addr,
85
+
u32 page_sz,
86
+
u32 entry_num,
87
+
struct hw_mmu_map_attrs_t *map_attrs,
88
+
s8 preserved_bit, s8 valid_bit);
89
+
90
+
/* For PTEs */
91
+
extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
92
+
u32 physical_addr,
93
+
u32 virtual_addr,
94
+
u32 page_sz,
95
+
struct hw_mmu_map_attrs_t *map_attrs);
96
+
97
+
extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,
98
+
u32 virtual_addr, u32 page_size);
99
+
100
+
void hw_mmu_tlb_flush_all(const void __iomem *base);
101
+
102
+
static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
103
+
{
104
+
u32 pte_addr;
105
+
u32 va31_to20;
106
+
107
+
va31_to20 = va >> (20 - 2); /* Left-shift by 2 here itself */
108
+
va31_to20 &= 0xFFFFFFFCUL;
109
+
pte_addr = l1_base + va31_to20;
110
+
111
+
return pte_addr;
112
+
}
113
+
114
+
static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va)
115
+
{
116
+
u32 pte_addr;
117
+
118
+
pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
119
+
120
+
return pte_addr;
121
+
}
122
+
123
+
static inline u32 hw_mmu_pte_coarse_l1(u32 pte_val)
124
+
{
125
+
u32 pte_coarse;
126
+
127
+
pte_coarse = pte_val & 0xFFFFFC00;
128
+
129
+
return pte_coarse;
130
+
}
131
+
132
+
static inline u32 hw_mmu_pte_size_l1(u32 pte_val)
133
+
{
134
+
u32 pte_size = 0;
135
+
136
+
if ((pte_val & 0x3) == 0x1) {
137
+
/* Points to L2 PT */
138
+
pte_size = HW_MMU_COARSE_PAGE_SIZE;
139
+
}
140
+
141
+
if ((pte_val & 0x3) == 0x2) {
142
+
if (pte_val & (1 << 18))
143
+
pte_size = HW_PAGE_SIZE16MB;
144
+
else
145
+
pte_size = HW_PAGE_SIZE1MB;
146
+
}
147
+
148
+
return pte_size;
149
+
}
150
+
151
+
static inline u32 hw_mmu_pte_size_l2(u32 pte_val)
152
+
{
153
+
u32 pte_size = 0;
154
+
155
+
if (pte_val & 0x2)
156
+
pte_size = HW_PAGE_SIZE4KB;
157
+
else if (pte_val & 0x1)
158
+
pte_size = HW_PAGE_SIZE64KB;
159
+
160
+
return pte_size;
161
+
}
162
+
163
+
#endif /* _HW_MMU_H */
+7
drivers/staging/tidspbridge/include/dspbridge/dspioctl.h
+7
drivers/staging/tidspbridge/include/dspbridge/dspioctl.h
···
19
19
#ifndef DSPIOCTL_
20
20
#define DSPIOCTL_
21
21
22
+
/* ------------------------------------ Hardware Abstraction Layer */
23
+
#include <hw_defs.h>
24
+
#include <hw_mmu.h>
25
+
22
26
/*
23
27
* Any IOCTLS at or above this value are reserved for standard Bridge driver
24
28
* interfaces.
···
65
61
/* GPP virtual address. __va does not work for ioremapped addresses */
66
62
u32 ul_gpp_va;
67
63
u32 ul_size; /* Size of the mapped memory in bytes */
64
+
enum hw_endianism_t endianism;
65
+
enum hw_mmu_mixed_size_t mixed_mode;
66
+
enum hw_element_size_t elem_size;
68
67
};
69
68
70
69
#endif /* DSPIOCTL_ */