Merge branch 'pci/field-get' · tjh.dev/kernel@5897c17

tjh.dev / kernel

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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

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Merge branch 'pci/field-get'

- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo
Järvinen, Bjorn Helgaas)

- Rework DPC control programming for clarity (Ilpo Järvinen)

* pci/field-get:
PCI/portdrv: Use FIELD_GET()
PCI/VC: Use FIELD_GET()
PCI/PTM: Use FIELD_GET()
PCI/PME: Use FIELD_GET()
PCI/ATS: Use FIELD_GET()
PCI/ATS: Show PASID Capability register width in bitmasks
PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk
PCI: Use FIELD_GET()
PCI/MSI: Use FIELD_GET/PREP()
PCI/DPC: Use defines with DPC reason fields
PCI/DPC: Use defined fields with DPC_CTL register
PCI/DPC: Use FIELD_GET()
PCI: hotplug: Use FIELD_GET/PREP()
PCI: dwc: Use FIELD_GET/PREP()
PCI: cadence: Use FIELD_GET()
PCI: Use FIELD_GET() to extract Link Width
PCI: mvebu: Use FIELD_PREP() with Link Width
PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields

# Conflicts:
# drivers/pci/controller/dwc/pcie-tegra194.c

Bjorn Helgaas 2 years ago 5897c174 65de3fd8

+128 -96

19 changed files

expand all collapse all

drivers

pci

ats.c

controller

cadence

pcie-cadence-ep.c

dwc

pcie-designware-ep.c

pcie-tegra194.c

pci-mvebu.c

hotplug

pciehp_core.c

pciehp_hpc.c

pnv_php.c

msi

msi.c

pci-sysfs.c

pci.c

pcie

dpc.c

pme.c

portdrv.c

ptm.c

probe.c

quirks.c

vc.c

include

uapi

linux

pci_regs.h

+2 -5

drivers/pci/ats.c

reviewed

··· 9 9 * Copyright (C) 2011 Advanced Micro Devices, 10 10 */ 11 11 12 12 + #include <linux/bitfield.h> 12 13 #include <linux/export.h> 13 14 #include <linux/pci-ats.h> 14 15 #include <linux/pci.h> ··· 481 480 } 482 481 EXPORT_SYMBOL_GPL(pci_pasid_features); 483 482 484 484 - #define PASID_NUMBER_SHIFT 8 485 485 - #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) 486 483 /** 487 484 * pci_max_pasids - Get maximum number of PASIDs supported by device 488 485 * @pdev: PCI device structure ··· 502 503 503 504 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported); 504 505 505 505 - supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT; 506 506 - 507 507 - return (1 << supported); 506 506 + return (1 << FIELD_GET(PCI_PASID_CAP_WIDTH, supported)); 508 507 } 509 508 EXPORT_SYMBOL_GPL(pci_max_pasids); 510 509 #endif /* CONFIG_PCI_PASID */

+5 -4

drivers/pci/controller/cadence/pcie-cadence-ep.c

reviewed

··· 3 3 // Cadence PCIe endpoint controller driver. 4 4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> 5 5 6 6 + #include <linux/bitfield.h> 6 7 #include <linux/delay.h> 7 8 #include <linux/kernel.h> 8 9 #include <linux/of.h> ··· 263 262 * Get the Multiple Message Enable bitfield from the Message Control 264 263 * register. 265 264 */ 266 266 - mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 265 265 + mme = FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); 267 266 268 267 return mme; 269 268 } ··· 395 394 return -EINVAL; 396 395 397 396 /* Get the number of enabled MSIs */ 398 398 - mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 397 397 + mme = FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); 399 398 msi_count = 1 << mme; 400 399 if (!interrupt_num || interrupt_num > msi_count) 401 400 return -EINVAL; ··· 450 449 return -EINVAL; 451 450 452 451 /* Get the number of enabled MSIs */ 453 453 - mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4; 452 452 + mme = FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); 454 453 msi_count = 1 << mme; 455 454 if (!interrupt_num || interrupt_num > msi_count) 456 455 return -EINVAL; ··· 507 506 508 507 reg = cap + PCI_MSIX_TABLE; 509 508 tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg); 510 510 - bir = tbl_offset & PCI_MSIX_TABLE_BIR; 509 509 + bir = FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); 511 510 tbl_offset &= PCI_MSIX_TABLE_OFFSET; 512 511 513 512 msix_tbl = epf->epf_bar[bir]->addr + tbl_offset;

+4 -3

drivers/pci/controller/dwc/pcie-designware-ep.c

reviewed

··· 6 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 7 */ 8 8 9 9 + #include <linux/bitfield.h> 9 10 #include <linux/of.h> 10 11 #include <linux/platform_device.h> 11 12 ··· 351 350 if (!(val & PCI_MSI_FLAGS_ENABLE)) 352 351 return -EINVAL; 353 352 354 354 - val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; 353 353 + val = FIELD_GET(PCI_MSI_FLAGS_QSIZE, val); 355 354 356 355 return val; 357 356 } ··· 374 373 reg = ep_func->msi_cap + func_offset + PCI_MSI_FLAGS; 375 374 val = dw_pcie_readw_dbi(pci, reg); 376 375 val &= ~PCI_MSI_FLAGS_QMASK; 377 377 - val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; 376 376 + val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, interrupts); 378 377 dw_pcie_dbi_ro_wr_en(pci); 379 378 dw_pcie_writew_dbi(pci, reg, val); 380 379 dw_pcie_dbi_ro_wr_dis(pci); ··· 601 600 602 601 reg = ep_func->msix_cap + func_offset + PCI_MSIX_TABLE; 603 602 tbl_offset = dw_pcie_readl_dbi(pci, reg); 604 604 - bir = (tbl_offset & PCI_MSIX_TABLE_BIR); 603 603 + bir = FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); 605 604 tbl_offset &= PCI_MSIX_TABLE_OFFSET; 606 605 607 606 msix_tbl = ep->epf_bar[bir]->addr + tbl_offset;

+10 -7

drivers/pci/controller/dwc/pcie-tegra194.c

reviewed

··· 9 9 * Author: Vidya Sagar <vidyas@nvidia.com> 10 10 */ 11 11 12 12 + #include <linux/bitfield.h> 12 13 #include <linux/clk.h> 13 14 #include <linux/debugfs.h> 14 15 #include <linux/delay.h> ··· 126 125 127 126 #define APPL_LTR_MSG_1 0xC4 128 127 #define LTR_MSG_REQ BIT(15) 129 129 - #define LTR_MST_NO_SNOOP_SHIFT 16 128 128 + #define LTR_NOSNOOP_MSG_REQ BIT(31) 130 129 131 130 #define APPL_LTR_MSG_2 0xC8 132 131 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3) ··· 347 346 */ 348 347 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); 349 348 if (val & PCI_EXP_LNKSTA_LBMS) { 350 350 - current_link_width = (val & PCI_EXP_LNKSTA_NLW) >> 351 351 - PCI_EXP_LNKSTA_NLW_SHIFT; 349 349 + current_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val); 352 350 if (pcie->init_link_width > current_link_width) { 353 351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); 354 352 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + ··· 496 496 ktime_t timeout; 497 497 498 498 /* 110us for both snoop and no-snoop */ 499 499 - val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; 500 500 - val |= (val << LTR_MST_NO_SNOOP_SHIFT); 499 499 + val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) | 500 500 + FIELD_PREP(PCI_LTR_SCALE_MASK, 2) | 501 501 + LTR_MSG_REQ | 502 502 + FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) | 503 503 + FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) | 504 504 + LTR_NOSNOOP_MSG_REQ; 501 505 appl_writel(pcie, val, APPL_LTR_MSG_1); 502 506 503 507 /* Send LTR upstream */ ··· 764 760 765 761 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 766 762 PCI_EXP_LNKSTA); 767 767 - pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >> 768 768 - PCI_EXP_LNKSTA_NLW_SHIFT; 763 763 + pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w); 769 764 770 765 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + 771 766 PCI_EXP_LNKCTL);

+1 -1

drivers/pci/controller/pci-mvebu.c

reviewed

··· 264 264 */ 265 265 lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); 266 266 lnkcap &= ~PCI_EXP_LNKCAP_MLW; 267 267 - lnkcap |= (port->is_x4 ? 4 : 1) << 4; 267 267 + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, port->is_x4 ? 4 : 1); 268 268 mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); 269 269 270 270 /* Disable Root Bridge I/O space, memory space and bus mastering. */

+2 -1

drivers/pci/hotplug/pciehp_core.c

reviewed

··· 20 20 #define pr_fmt(fmt) "pciehp: " fmt 21 21 #define dev_fmt pr_fmt 22 22 23 23 + #include <linux/bitfield.h> 23 24 #include <linux/moduleparam.h> 24 25 #include <linux/kernel.h> 25 26 #include <linux/slab.h> ··· 104 103 struct pci_dev *pdev = ctrl->pcie->port; 105 104 106 105 if (status) 107 107 - status <<= PCI_EXP_SLTCTL_ATTN_IND_SHIFT; 106 106 + status = FIELD_PREP(PCI_EXP_SLTCTL_AIC, status); 108 107 else 109 108 status = PCI_EXP_SLTCTL_ATTN_IND_OFF; 110 109

+3 -2

drivers/pci/hotplug/pciehp_hpc.c

reviewed

··· 14 14 15 15 #define dev_fmt(fmt) "pciehp: " fmt 16 16 17 17 + #include <linux/bitfield.h> 17 18 #include <linux/dmi.h> 18 19 #include <linux/kernel.h> 19 20 #include <linux/types.h> ··· 485 484 struct pci_dev *pdev = ctrl_dev(ctrl); 486 485 487 486 pci_config_pm_runtime_get(pdev); 488 488 - pcie_write_cmd_nowait(ctrl, status << 6, 487 487 + pcie_write_cmd_nowait(ctrl, FIELD_PREP(PCI_EXP_SLTCTL_AIC, status), 489 488 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC); 490 489 pci_config_pm_runtime_put(pdev); 491 490 return 0; ··· 1029 1028 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC); 1030 1029 1031 1030 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n", 1032 1032 - (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 1031 1031 + FIELD_GET(PCI_EXP_SLTCAP_PSN, slot_cap), 1033 1032 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 1034 1033 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 1035 1034 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),

+2 -1

drivers/pci/hotplug/pnv_php.c

reviewed

··· 5 5 * Copyright Gavin Shan, IBM Corporation 2016. 6 6 */ 7 7 8 8 + #include <linux/bitfield.h> 8 9 #include <linux/libfdt.h> 9 10 #include <linux/module.h> 10 11 #include <linux/pci.h> ··· 732 731 733 732 /* Check hotplug MSIx entry is in range */ 734 733 pcie_capability_read_word(pdev, PCI_EXP_FLAGS, &pcie_flag); 735 735 - entry.entry = (pcie_flag & PCI_EXP_FLAGS_IRQ) >> 9; 734 734 + entry.entry = FIELD_GET(PCI_EXP_FLAGS_IRQ, pcie_flag); 736 735 if (entry.entry >= nr_entries) 737 736 return -ERANGE; 738 737

+6 -4

drivers/pci/msi/msi.c

reviewed

··· 6 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 7 * Copyright (C) 2016 Christoph Hellwig. 8 8 */ 9 9 + #include <linux/bitfield.h> 9 10 #include <linux/err.h> 10 11 #include <linux/export.h> 11 12 #include <linux/irq.h> ··· 189 188 190 189 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); 191 190 msgctl &= ~PCI_MSI_FLAGS_QSIZE; 192 192 - msgctl |= desc->pci.msi_attrib.multiple << 4; 191 191 + msgctl |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, desc->pci.msi_attrib.multiple); 193 192 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); 194 193 195 194 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, msg->address_lo); ··· 300 299 desc.pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); 301 300 desc.pci.msi_attrib.can_mask = !!(control & PCI_MSI_FLAGS_MASKBIT); 302 301 desc.pci.msi_attrib.default_irq = dev->irq; 303 303 - desc.pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; 302 302 + desc.pci.msi_attrib.multi_cap = FIELD_GET(PCI_MSI_FLAGS_QMASK, control); 304 303 desc.pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); 305 304 desc.affinity = masks; 306 305 ··· 479 478 return -EINVAL; 480 479 481 480 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); 482 482 - ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); 481 481 + ret = 1 << FIELD_GET(PCI_MSI_FLAGS_QMASK, msgctl); 483 482 484 483 return ret; 485 484 } ··· 512 511 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 513 512 pci_msi_update_mask(entry, 0, 0); 514 513 control &= ~PCI_MSI_FLAGS_QSIZE; 515 515 - control |= (entry->pci.msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; 514 514 + control |= PCI_MSI_FLAGS_ENABLE | 515 515 + FIELD_PREP(PCI_MSI_FLAGS_QSIZE, entry->pci.msi_attrib.multiple); 516 516 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 517 517 } 518 518

+2 -3

drivers/pci/pci-sysfs.c

reviewed

··· 12 12 * Modeled after usb's driverfs.c 13 13 */ 14 14 15 15 - 15 15 + #include <linux/bitfield.h> 16 16 #include <linux/kernel.h> 17 17 #include <linux/sched.h> 18 18 #include <linux/pci.h> ··· 230 230 if (err) 231 231 return -EINVAL; 232 232 233 233 - return sysfs_emit(buf, "%u\n", 234 234 - (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT); 233 233 + return sysfs_emit(buf, "%u\n", FIELD_GET(PCI_EXP_LNKSTA_NLW, linkstat)); 235 234 } 236 235 static DEVICE_ATTR_RO(current_link_width); 237 236

+28 -30

drivers/pci/pci.c

reviewed

··· 1778 1778 return; 1779 1779 1780 1780 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); 1781 1781 - nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> 1782 1782 - PCI_REBAR_CTRL_NBAR_SHIFT; 1781 1781 + nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); 1783 1782 1784 1783 for (i = 0; i < nbars; i++, pos += 8) { 1785 1784 struct resource *res; ··· 1789 1790 res = pdev->resource + bar_idx; 1790 1791 size = pci_rebar_bytes_to_size(resource_size(res)); 1791 1792 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; 1792 1792 - ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; 1793 1793 + ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); 1793 1794 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); 1794 1795 } 1795 1796 } ··· 3230 3231 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 3231 3232 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "", 3232 3233 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 3233 3233 - dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 3234 3234 + dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc); 3234 3235 dev->pme_poll = true; 3235 3236 /* 3236 3237 * Make device's PM flags reflect the wake-up capability, but ··· 3301 3302 ent_offset += 4; 3302 3303 3303 3304 /* Entry size field indicates DWORDs after 1st */ 3304 3304 - ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; 3305 3305 + ent_size = (FIELD_GET(PCI_EA_ES, dw0) + 1) << 2; 3305 3306 3306 3307 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ 3307 3308 goto out; 3308 3309 3309 3309 - bei = (dw0 & PCI_EA_BEI) >> 4; 3310 3310 - prop = (dw0 & PCI_EA_PP) >> 8; 3310 3310 + bei = FIELD_GET(PCI_EA_BEI, dw0); 3311 3311 + prop = FIELD_GET(PCI_EA_PP, dw0); 3311 3312 3312 3313 /* 3313 3314 * If the Property is in the reserved range, try the Secondary 3314 3315 * Property instead. 3315 3316 */ 3316 3317 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) 3317 3317 - prop = (dw0 & PCI_EA_SP) >> 16; 3318 3318 + prop = FIELD_GET(PCI_EA_SP, dw0); 3318 3319 if (prop > PCI_EA_P_BRIDGE_IO) 3319 3320 goto out; 3320 3321 ··· 3721 3722 return -ENOTSUPP; 3722 3723 3723 3724 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); 3724 3724 - nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> 3725 3725 - PCI_REBAR_CTRL_NBAR_SHIFT; 3725 3725 + nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); 3726 3726 3727 3727 for (i = 0; i < nbars; i++, pos += 8) { 3728 3728 int bar_idx; 3729 3729 3730 3730 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); 3731 3731 - bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; 3731 3731 + bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); 3732 3732 if (bar_idx == bar) 3733 3733 return pos; 3734 3734 } ··· 3753 3755 return 0; 3754 3756 3755 3757 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); 3756 3756 - cap &= PCI_REBAR_CAP_SIZES; 3758 3758 + cap = FIELD_GET(PCI_REBAR_CAP_SIZES, cap); 3757 3759 3758 3760 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ 3759 3761 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && 3760 3760 - bar == 0 && cap == 0x7000) 3761 3761 - cap = 0x3f000; 3762 3762 + bar == 0 && cap == 0x700) 3763 3763 + return 0x3f00; 3762 3764 3763 3763 - return cap >> 4; 3765 3765 + return cap; 3764 3766 } 3765 3767 EXPORT_SYMBOL(pci_rebar_get_possible_sizes); 3766 3768 ··· 3782 3784 return pos; 3783 3785 3784 3786 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); 3785 3785 - return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT; 3787 3787 + return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl); 3786 3788 } 3787 3789 3788 3790 /** ··· 3805 3807 3806 3808 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); 3807 3809 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; 3808 3808 - ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; 3810 3810 + ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); 3809 3811 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); 3810 3812 return 0; 3811 3813 } ··· 6043 6045 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 6044 6046 return -EINVAL; 6045 6047 6046 6046 - return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 6048 6048 + return 512 << FIELD_GET(PCI_X_STATUS_MAX_READ, stat); 6047 6049 } 6048 6050 EXPORT_SYMBOL(pcix_get_max_mmrbc); 6049 6051 ··· 6066 6068 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 6067 6069 return -EINVAL; 6068 6070 6069 6069 - return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 6071 6071 + return 512 << FIELD_GET(PCI_X_CMD_MAX_READ, cmd); 6070 6072 } 6071 6073 EXPORT_SYMBOL(pcix_get_mmrbc); 6072 6074 ··· 6097 6099 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 6098 6100 return -EINVAL; 6099 6101 6100 6100 - if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 6102 6102 + if (v > FIELD_GET(PCI_X_STATUS_MAX_READ, stat)) 6101 6103 return -E2BIG; 6102 6104 6103 6105 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 6104 6106 return -EINVAL; 6105 6107 6106 6106 - o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 6108 6108 + o = FIELD_GET(PCI_X_CMD_MAX_READ, cmd); 6107 6109 if (o != v) { 6108 6110 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 6109 6111 return -EIO; 6110 6112 6111 6113 cmd &= ~PCI_X_CMD_MAX_READ; 6112 6112 - cmd |= v << 2; 6114 6114 + cmd |= FIELD_PREP(PCI_X_CMD_MAX_READ, v); 6113 6115 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 6114 6116 return -EIO; 6115 6117 } ··· 6129 6131 6130 6132 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 6131 6133 6132 6132 - return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 6134 6134 + return 128 << FIELD_GET(PCI_EXP_DEVCTL_READRQ, ctl); 6133 6135 } 6134 6136 EXPORT_SYMBOL(pcie_get_readrq); 6135 6137 ··· 6162 6164 rq = mps; 6163 6165 } 6164 6166 6165 6165 - v = (ffs(rq) - 8) << 12; 6167 6167 + v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8); 6166 6168 6167 6169 if (bridge->no_inc_mrrs) { 6168 6170 int max_mrrs = pcie_get_readrq(dev); ··· 6192 6194 6193 6195 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 6194 6196 6195 6195 - return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 6197 6197 + return 128 << FIELD_GET(PCI_EXP_DEVCTL_PAYLOAD, ctl); 6196 6198 } 6197 6199 EXPORT_SYMBOL(pcie_get_mps); 6198 6200 ··· 6215 6217 v = ffs(mps) - 8; 6216 6218 if (v > dev->pcie_mpss) 6217 6219 return -EINVAL; 6218 6218 - v <<= 5; 6220 6220 + v = FIELD_PREP(PCI_EXP_DEVCTL_PAYLOAD, v); 6219 6221 6220 6222 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 6221 6223 PCI_EXP_DEVCTL_PAYLOAD, v); ··· 6257 6259 while (dev) { 6258 6260 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 6259 6261 6260 6260 - next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; 6261 6261 - next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> 6262 6262 - PCI_EXP_LNKSTA_NLW_SHIFT; 6262 6262 + next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, 6263 6263 + lnksta)]; 6264 6264 + next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); 6263 6265 6264 6266 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); 6265 6267 ··· 6331 6333 6332 6334 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 6333 6335 if (lnkcap) 6334 6334 - return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; 6336 6336 + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); 6335 6337 6336 6338 return PCIE_LNK_WIDTH_UNKNOWN; 6337 6339 }

+27 -15

drivers/pci/pcie/dpc.c

reviewed

··· 9 9 #define dev_fmt(fmt) "DPC: " fmt 10 10 11 11 #include <linux/aer.h> 12 12 + #include <linux/bitfield.h> 12 13 #include <linux/delay.h> 13 14 #include <linux/interrupt.h> 14 15 #include <linux/init.h> ··· 17 16 18 17 #include "portdrv.h" 19 18 #include "../pci.h" 19 19 + 20 20 + #define PCI_EXP_DPC_CTL_EN_MASK (PCI_EXP_DPC_CTL_EN_FATAL | \ 21 21 + PCI_EXP_DPC_CTL_EN_NONFATAL) 20 22 21 23 static const char * const rp_pio_error_string[] = { 22 24 "Configuration Request received UR Completion", /* Bit Position 0 */ ··· 206 202 207 203 /* Get First Error Pointer */ 208 204 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); 209 209 - first_error = (dpc_status & 0x1f00) >> 8; 205 205 + first_error = FIELD_GET(PCI_EXP_DPC_RP_PIO_FEP, dpc_status); 210 206 211 207 for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { 212 208 if ((status & ~mask) & (1 << i)) ··· 274 270 pci_info(pdev, "containment event, status:%#06x source:%#06x\n", 275 271 status, source); 276 272 277 277 - reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1; 278 278 - ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5; 273 273 + reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN; 274 274 + ext_reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT; 279 275 pci_warn(pdev, "%s detected\n", 280 280 - (reason == 0) ? "unmasked uncorrectable error" : 281 281 - (reason == 1) ? "ERR_NONFATAL" : 282 282 - (reason == 2) ? "ERR_FATAL" : 283 283 - (ext_reason == 0) ? "RP PIO error" : 284 284 - (ext_reason == 1) ? "software trigger" : 285 285 - "reserved error"); 276 276 + (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR) ? 277 277 + "unmasked uncorrectable error" : 278 278 + (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE) ? 279 279 + "ERR_NONFATAL" : 280 280 + (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE) ? 281 281 + "ERR_FATAL" : 282 282 + (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) ? 283 283 + "RP PIO error" : 284 284 + (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER) ? 285 285 + "software trigger" : 286 286 + "reserved error"); 286 287 287 288 /* show RP PIO error detail information */ 288 288 - if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0) 289 289 + if (pdev->dpc_rp_extensions && 290 290 + reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT && 291 291 + ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) 289 292 dpc_process_rp_pio_error(pdev); 290 290 - else if (reason == 0 && 293 293 + else if (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR && 291 294 dpc_get_aer_uncorrect_severity(pdev, &info) && 292 295 aer_get_device_error_info(pdev, &info)) { 293 296 aer_print_error(pdev, &info); ··· 349 338 /* Quirks may set dpc_rp_log_size if device or firmware is buggy */ 350 339 if (!pdev->dpc_rp_log_size) { 351 340 pdev->dpc_rp_log_size = 352 352 - (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; 341 341 + FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, cap); 353 342 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { 354 343 pci_err(pdev, "RP PIO log size %u is invalid\n", 355 344 pdev->dpc_rp_log_size); ··· 379 368 } 380 369 381 370 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap); 371 371 + 382 372 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl); 383 383 - 384 384 - ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; 373 373 + ctl &= ~PCI_EXP_DPC_CTL_EN_MASK; 374 374 + ctl |= PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN; 385 375 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl); 386 386 - pci_info(pdev, "enabled with IRQ %d\n", dev->irq); 387 376 377 377 + pci_info(pdev, "enabled with IRQ %d\n", dev->irq); 388 378 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", 389 379 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), 390 380 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),

+3 -1

drivers/pci/pcie/pme.c

reviewed

··· 9 9 10 10 #define dev_fmt(fmt) "PME: " fmt 11 11 12 12 + #include <linux/bitfield.h> 12 13 #include <linux/pci.h> 13 14 #include <linux/kernel.h> 14 15 #include <linux/errno.h> ··· 236 235 pcie_clear_root_pme_status(port); 237 236 238 237 spin_unlock_irq(&data->lock); 239 239 - pcie_pme_handle_request(port, rtsta & 0xffff); 238 238 + pcie_pme_handle_request(port, 239 239 + FIELD_GET(PCI_EXP_RTSTA_PME_RQ_ID, rtsta)); 240 240 spin_lock_irq(&data->lock); 241 241 242 242 continue;

+4 -3

drivers/pci/pcie/portdrv.c

reviewed

··· 6 6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) 7 7 */ 8 8 9 9 + #include <linux/bitfield.h> 9 10 #include <linux/dmi.h> 10 11 #include <linux/init.h> 11 12 #include <linux/module.h> ··· 70 69 if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | 71 70 PCIE_PORT_SERVICE_BWNOTIF)) { 72 71 pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16); 73 73 - *pme = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; 72 72 + *pme = FIELD_GET(PCI_EXP_FLAGS_IRQ, reg16); 74 73 nvec = *pme + 1; 75 74 } 76 75 ··· 82 81 if (pos) { 83 82 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, 84 83 &reg32); 85 85 - *aer = (reg32 & PCI_ERR_ROOT_AER_IRQ) >> 27; 84 84 + *aer = FIELD_GET(PCI_ERR_ROOT_AER_IRQ, reg32); 86 85 nvec = max(nvec, *aer + 1); 87 86 } 88 87 } ··· 93 92 if (pos) { 94 93 pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, 95 94 &reg16); 96 96 - *dpc = reg16 & PCI_EXP_DPC_IRQ; 95 95 + *dpc = FIELD_GET(PCI_EXP_DPC_IRQ, reg16); 97 96 nvec = max(nvec, *dpc + 1); 98 97 } 99 98 }

+3 -2

drivers/pci/pcie/ptm.c

reviewed

··· 4 4 * Copyright (c) 2016, Intel Corporation. 5 5 */ 6 6 7 7 + #include <linux/bitfield.h> 7 8 #include <linux/module.h> 8 9 #include <linux/init.h> 9 10 #include <linux/pci.h> ··· 54 53 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32)); 55 54 56 55 pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap); 57 57 - dev->ptm_granularity = (cap & PCI_PTM_GRANULARITY_MASK) >> 8; 56 56 + dev->ptm_granularity = FIELD_GET(PCI_PTM_GRANULARITY_MASK, cap); 58 57 59 58 /* 60 59 * Per the spec recommendation (PCIe r6.0, sec 7.9.15.3), select the ··· 147 146 148 147 ctrl |= PCI_PTM_CTRL_ENABLE; 149 148 ctrl &= ~PCI_PTM_GRANULARITY_MASK; 150 150 - ctrl |= dev->ptm_granularity << 8; 149 149 + ctrl |= FIELD_PREP(PCI_PTM_GRANULARITY_MASK, dev->ptm_granularity); 151 150 if (dev->ptm_root) 152 151 ctrl |= PCI_PTM_CTRL_ROOT; 153 152

+4 -4

drivers/pci/probe.c

reviewed

··· 807 807 } 808 808 809 809 bus->max_bus_speed = max; 810 810 - bus->cur_bus_speed = pcix_bus_speed[ 811 811 - (status & PCI_X_SSTATUS_FREQ) >> 6]; 810 810 + bus->cur_bus_speed = 811 811 + pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)]; 812 812 813 813 return; 814 814 } ··· 1217 1217 1218 1218 offset = ea + PCI_EA_FIRST_ENT; 1219 1219 pci_read_config_dword(dev, offset, &dw); 1220 1220 - ea_sec = dw & PCI_EA_SEC_BUS_MASK; 1221 1221 - ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; 1220 1220 + ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw); 1221 1221 + ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw); 1222 1222 if (ea_sec == 0 || ea_sub < ea_sec) 1223 1223 return false; 1224 1224

+1 -1

drivers/pci/quirks.c

reviewed

··· 6175 6175 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6176 6176 return; 6177 6177 6178 6178 - if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) { 6178 6178 + if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6179 6179 pci_info(dev, "Overriding RP PIO Log Size to 4\n"); 6180 6180 dev->dpc_rp_log_size = 4; 6181 6181 }

+5 -4

drivers/pci/vc.c

reviewed

··· 6 6 * Author: Alex Williamson <alex.williamson@redhat.com> 7 7 */ 8 8 9 9 + #include <linux/bitfield.h> 9 10 #include <linux/device.h> 10 11 #include <linux/kernel.h> 11 12 #include <linux/module.h> ··· 202 201 /* Extended VC Count (not counting VC0) */ 203 202 evcc = cap1 & PCI_VC_CAP1_EVCC; 204 203 /* Low Priority Extended VC Count (not counting VC0) */ 205 205 - lpevcc = (cap1 & PCI_VC_CAP1_LPEVCC) >> 4; 204 204 + lpevcc = FIELD_GET(PCI_VC_CAP1_LPEVCC, cap1); 206 205 /* Port Arbitration Table Entry Size (bits) */ 207 207 - parb_size = 1 << ((cap1 & PCI_VC_CAP1_ARB_SIZE) >> 10); 206 206 + parb_size = 1 << FIELD_GET(PCI_VC_CAP1_ARB_SIZE, cap1); 208 207 209 208 /* 210 209 * Port VC Control Register contains VC Arbitration Select, which ··· 232 231 int vcarb_offset; 233 232 234 233 pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP2, &cap2); 235 235 - vcarb_offset = ((cap2 & PCI_VC_CAP2_ARB_OFF) >> 24) * 16; 234 234 + vcarb_offset = FIELD_GET(PCI_VC_CAP2_ARB_OFF, cap2) * 16; 236 235 237 236 if (vcarb_offset) { 238 237 int size, vcarb_phases = 0; ··· 278 277 279 278 pci_read_config_dword(dev, pos + PCI_VC_RES_CAP + 280 279 (i * PCI_CAP_VC_PER_VC_SIZEOF), &cap); 281 281 - parb_offset = ((cap & PCI_VC_RES_CAP_ARB_OFF) >> 24) * 16; 280 280 + parb_offset = FIELD_GET(PCI_VC_RES_CAP_ARB_OFF, cap) * 16; 282 281 if (parb_offset) { 283 282 int size, parb_phases = 0; 284 283

+16 -5

include/uapi/linux/pci_regs.h

reviewed

··· 638 638 #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ 639 639 #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ 640 640 #define PCI_EXP_RTSTA 0x20 /* Root Status */ 641 641 + #define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */ 641 642 #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ 642 643 #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ 643 644 /* ··· 932 931 933 932 /* Process Address Space ID */ 934 933 #define PCI_PASID_CAP 0x04 /* PASID feature register */ 935 935 - #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ 936 936 - #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ 934 934 + #define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ 935 935 + #define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ 936 936 + #define PCI_PASID_CAP_WIDTH 0x1f00 937 937 #define PCI_PASID_CTRL 0x06 /* PASID control register */ 938 938 - #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ 939 939 - #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ 940 940 - #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ 938 938 + #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ 939 939 + #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ 940 940 + #define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ 941 941 #define PCI_EXT_CAP_PASID_SIZEOF 8 942 942 943 943 /* Single Root I/O Virtualization */ ··· 978 976 #define PCI_LTR_VALUE_MASK 0x000003ff 979 977 #define PCI_LTR_SCALE_MASK 0x00001c00 980 978 #define PCI_LTR_SCALE_SHIFT 10 979 979 + #define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */ 980 980 + #define PCI_LTR_NOSNOOP_SCALE 0x1c000000 /* Scale for Max Value */ 981 981 #define PCI_EXT_CAP_LTR_SIZEOF 8 982 982 983 983 /* Access Control Service */ ··· 1047 1043 #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ 1048 1044 #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ 1049 1045 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ 1046 1046 + #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR 0x0000 /* Uncorrectable error */ 1047 1047 + #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE 0x0002 /* Rcvd ERR_NONFATAL */ 1048 1048 + #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE 0x0004 /* Rcvd ERR_FATAL */ 1049 1049 + #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */ 1050 1050 #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ 1051 1051 #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ 1052 1052 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ 1053 1053 + #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO 0x0000 /* RP PIO error */ 1054 1054 + #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER 0x0020 /* DPC SW Trigger bit */ 1055 1055 + #define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */ 1053 1056 1054 1057 #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ 1055 1058