Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

m68k: clean up comment delimiters in dma.h

Change C99 style comments to traditional K&R style.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

+27 -27
+27 -27
arch/m68k/include/asm/dma.h
··· 177 177 dmabp = (unsigned char *) dma_base_addr[dmanr]; 178 178 dmawp = (unsigned short *) dma_base_addr[dmanr]; 179 179 180 - // Clear config errors 180 + /* Clear config errors */ 181 181 dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE; 182 182 183 - // Set command register 183 + /* Set command register */ 184 184 dmawp[MCFDMA_DCR] = 185 - MCFDMA_DCR_INT | // Enable completion irq 186 - MCFDMA_DCR_CS | // Force one xfer per request 187 - MCFDMA_DCR_AA | // Enable auto alignment 188 - // single-address-mode 185 + MCFDMA_DCR_INT | /* Enable completion irq */ 186 + MCFDMA_DCR_CS | /* Force one xfer per request */ 187 + MCFDMA_DCR_AA | /* Enable auto alignment */ 188 + /* single-address-mode */ 189 189 ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) | 190 - // sets s_rw (-> r/w) high if Memory to I/0 190 + /* sets s_rw (-> r/w) high if Memory to I/0 */ 191 191 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) | 192 - // Memory to I/O or I/O to Memory 192 + /* Memory to I/O or I/O to Memory */ 193 193 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) | 194 - // 32 bit, 16 bit or 8 bit transfers 194 + /* 32 bit, 16 bit or 8 bit transfers */ 195 195 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD : 196 196 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG : 197 197 MCFDMA_DCR_SSIZE_BYTE)) | ··· 219 219 dmawp = (unsigned short *) dma_base_addr[dmanr]; 220 220 dmalp = (unsigned int *) dma_base_addr[dmanr]; 221 221 222 - // Determine which address registers are used for memory/device accesses 222 + /* Determine which address registers are used for memory/device accesses */ 223 223 if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) { 224 - // Source incrementing, must be memory 224 + /* Source incrementing, must be memory */ 225 225 dmalp[MCFDMA_SAR] = a; 226 - // Set dest address, must be device 226 + /* Set dest address, must be device */ 227 227 dmalp[MCFDMA_DAR] = dma_device_address[dmanr]; 228 228 } else { 229 - // Destination incrementing, must be memory 229 + /* Destination incrementing, must be memory */ 230 230 dmalp[MCFDMA_DAR] = a; 231 - // Set source address, must be device 231 + /* Set source address, must be device */ 232 232 dmalp[MCFDMA_SAR] = dma_device_address[dmanr]; 233 233 } 234 234 ··· 367 367 dmalp = (unsigned int *) dma_base_addr[dmanr]; 368 368 dmawp = (unsigned short *) dma_base_addr[dmanr]; 369 369 370 - // Clear config errors 370 + /* Clear config errors */ 371 371 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; 372 372 373 - // Set command register 373 + /* Set command register */ 374 374 dmalp[MCFDMA_DMR] = 375 - MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting 376 - MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data. 377 - MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data. 378 - // source static-address-mode 375 + MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */ 376 + MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */ 377 + MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */ 378 + /* source static-address-mode */ 379 379 ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) | 380 - // dest static-address-mode 380 + /* dest static-address-mode */ 381 381 ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) | 382 - // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 382 + /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */ 383 383 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) | 384 384 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF); 385 385 ··· 403 403 404 404 dmalp = (unsigned int *) dma_base_addr[dmanr]; 405 405 406 - // Determine which address registers are used for memory/device accesses 406 + /* Determine which address registers are used for memory/device accesses */ 407 407 if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) { 408 - // Source incrementing, must be memory 408 + /* Source incrementing, must be memory */ 409 409 dmalp[MCFDMA_DSAR] = a; 410 - // Set dest address, must be device 410 + /* Set dest address, must be device */ 411 411 dmalp[MCFDMA_DDAR] = dma_device_address[dmanr]; 412 412 } else { 413 - // Destination incrementing, must be memory 413 + /* Destination incrementing, must be memory */ 414 414 dmalp[MCFDMA_DDAR] = a; 415 - // Set source address, must be device 415 + /* Set source address, must be device */ 416 416 dmalp[MCFDMA_DSAR] = dma_device_address[dmanr]; 417 417 } 418 418