···177177 dmabp = (unsigned char *) dma_base_addr[dmanr];178178 dmawp = (unsigned short *) dma_base_addr[dmanr];179179180180- // Clear config errors180180+ /* Clear config errors */181181 dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;182182183183- // Set command register183183+ /* Set command register */184184 dmawp[MCFDMA_DCR] =185185- MCFDMA_DCR_INT | // Enable completion irq186186- MCFDMA_DCR_CS | // Force one xfer per request187187- MCFDMA_DCR_AA | // Enable auto alignment188188- // single-address-mode185185+ MCFDMA_DCR_INT | /* Enable completion irq */186186+ MCFDMA_DCR_CS | /* Force one xfer per request */187187+ MCFDMA_DCR_AA | /* Enable auto alignment */188188+ /* single-address-mode */189189 ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |190190- // sets s_rw (-> r/w) high if Memory to I/0190190+ /* sets s_rw (-> r/w) high if Memory to I/0 */191191 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |192192- // Memory to I/O or I/O to Memory192192+ /* Memory to I/O or I/O to Memory */193193 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |194194- // 32 bit, 16 bit or 8 bit transfers194194+ /* 32 bit, 16 bit or 8 bit transfers */195195 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :196196 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :197197 MCFDMA_DCR_SSIZE_BYTE)) |···219219 dmawp = (unsigned short *) dma_base_addr[dmanr];220220 dmalp = (unsigned int *) dma_base_addr[dmanr];221221222222- // Determine which address registers are used for memory/device accesses222222+ /* Determine which address registers are used for memory/device accesses */223223 if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {224224- // Source incrementing, must be memory224224+ /* Source incrementing, must be memory */225225 dmalp[MCFDMA_SAR] = a;226226- // Set dest address, must be device226226+ /* Set dest address, must be device */227227 dmalp[MCFDMA_DAR] = dma_device_address[dmanr];228228 } else {229229- // Destination incrementing, must be memory229229+ /* Destination incrementing, must be memory */230230 dmalp[MCFDMA_DAR] = a;231231- // Set source address, must be device231231+ /* Set source address, must be device */232232 dmalp[MCFDMA_SAR] = dma_device_address[dmanr];233233 }234234···367367 dmalp = (unsigned int *) dma_base_addr[dmanr];368368 dmawp = (unsigned short *) dma_base_addr[dmanr];369369370370- // Clear config errors370370+ /* Clear config errors */371371 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;372372373373- // Set command register373373+ /* Set command register */374374 dmalp[MCFDMA_DMR] =375375- MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting376376- MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data.377377- MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data.378378- // source static-address-mode375375+ MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */376376+ MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */377377+ MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */378378+ /* source static-address-mode */379379 ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |380380- // dest static-address-mode380380+ /* dest static-address-mode */381381 ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |382382- // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272382382+ /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */383383 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |384384 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);385385···403403404404 dmalp = (unsigned int *) dma_base_addr[dmanr];405405406406- // Determine which address registers are used for memory/device accesses406406+ /* Determine which address registers are used for memory/device accesses */407407 if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {408408- // Source incrementing, must be memory408408+ /* Source incrementing, must be memory */409409 dmalp[MCFDMA_DSAR] = a;410410- // Set dest address, must be device410410+ /* Set dest address, must be device */411411 dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];412412 } else {413413- // Destination incrementing, must be memory413413+ /* Destination incrementing, must be memory */414414 dmalp[MCFDMA_DDAR] = a;415415- // Set source address, must be device415415+ /* Set source address, must be device */416416 dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];417417 }418418