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clocksource/drivers/arc_timer: Eliminate redefined macro error

In drivers/clocksource/, 3 drivers use "TIMER_CTRL_IE" with 3 different
values. Two of them (mps2-timer.c and timer-sp804.c/timer-sp.h) are
localized and left unmodifed.

One of them uses a shared header file (<soc/arc/timers.h>), which is
what is causing the "redefined" warnings, so change the macro name in
that driver only. Also change the TIMER_CTRL_NH macro name.
Both macro names are prefixed with "ARC_" to reduce the likelihood
of future name collisions.

In file included from ../drivers/clocksource/timer-sp804.c:24:
../drivers/clocksource/timer-sp.h:25: error: "TIMER_CTRL_IE" redefined [-Werror]
25 | #define TIMER_CTRL_IE (1 << 5) /* VR */
../include/soc/arc/timers.h:20: note: this is the location of the previous definition
20 | #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */

Fixes: b26c2e3823ba ("ARC: breakout timer include code into separate header")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Vineet Gupta <vgupta@kernel.org>
Cc: linux-snps-arc@lists.infradead.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shahab Vahedi <Shahab.Vahedi@synopsys.com>
Acked-by: Vineet Gupta <vgupta@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20210924020825.20317-1-rdunlap@infradead.org

authored by

Randy Dunlap and committed by
Daniel Lezcano
58100c34 d25a0252

+5 -5
+3 -3
drivers/clocksource/arc_timer.c
··· 225 225 226 226 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); 227 227 write_aux_reg(ARC_REG_TIMER1_CNT, 0); 228 - write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); 228 + write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH); 229 229 230 230 sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq); 231 231 ··· 245 245 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); 246 246 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ 247 247 248 - write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); 248 + write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | ARC_TIMER_CTRL_NH); 249 249 } 250 250 251 251 ··· 294 294 * explicitly clears IP bit 295 295 * 2. Re-arm interrupt if periodic by writing to IE bit [0] 296 296 */ 297 - write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); 297 + write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH); 298 298 299 299 evt->event_handler(evt); 300 300
+2 -2
include/soc/arc/timers.h
··· 17 17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 18 18 19 19 /* CTRL reg bits */ 20 - #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ 21 - #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 20 + #define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ 21 + #define ARC_TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 22 22 23 23 #define ARC_TIMERN_MAX 0xFFFFFFFF 24 24