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dt-bindings: Document the STM32 reset bindings
This adds documentation of device tree bindings for the
STM32 reset controller.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
authored by
Maxime Coquelin
and committed by
Philipp Zabel
57bd63a4
ca9f71f0
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Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
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Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
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STMicroelectronics STM32 Reset and Clock Controller
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===================================================
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The RCC IP is both a reset and a clock controller. This documentation only
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describes the clock part.
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The RCC IP is both a reset and a clock controller.
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Please also refer to clock-bindings.txt in this directory for common clock
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controller binding usage.
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Please refer to clock-bindings.txt for common clock controller binding usage.
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Please also refer to reset.txt for common reset controller binding usage.
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Required properties:
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- compatible: Should be "st,stm32f42xx-rcc"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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- #clock-cells: 2, device nodes should specify the clock in their "clocks"
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property, containing a phandle to the clock device node, an index selecting
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between gated clocks and other clocks and an index specifying the clock to
···
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Example:
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rcc: rcc@40023800 {
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#reset-cells = <1>;
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#clock-cells = <2>
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
···
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It is calculated as: index = register_offset / 4 * 32 + bit_offset.
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Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
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To simplify the usage and to share bit definition with the reset and clock
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drivers of the RCC IP, macros are available to generate the index in
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human-readble format.
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For STM32F4 series, the macro are available here:
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- include/dt-bindings/mfd/stm32f4-rcc.h
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Example:
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/* Gated clock, AHB1 bit 0 (GPIOA) */
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... {
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clocks = <&rcc 0 0>
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
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};
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/* Gated clock, AHB2 bit 4 (CRYP) */
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... {
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clocks = <&rcc 0 36>
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clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
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};
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Specifying other clocks
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/* Misc clock, FCLK */
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... {
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clocks = <&rcc 1 1>
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clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
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};
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Specifying softreset control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the reset device node and an index specifying
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which channel to use.
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The index is the bit number within the RCC registers bank, starting from RCC
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base address.
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It is calculated as: index = register_offset / 4 * 32 + bit_offset.
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Where bit_offset is the bit offset within the register.
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For example, for CRC reset:
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crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
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example:
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timer2 {
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resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
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};
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Documentation/devicetree/bindings/reset/st,stm32-rcc.txt
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Documentation/devicetree/bindings/reset/st,stm32-rcc.txt