tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/panel/panel-sitronix-st7701: Add Densitron DMT028VGHMCMI-1A TFT

Add support for Densitron DMT028VGHMCMI-1A TFT matrix into this driver.
This is a DSI-attached 480x640 2.83 inch panel.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220725151703.319939-2-marex@denx.de

authored by

Marek Vasut and committed by
Linus Walleij 57b2efce e6e62748

+182 -5
+182 -5
drivers/gpu/drm/panel/panel-sitronix-st7701.c
··· 42 42 /* 43 43 * Command2 with BK function selection. 44 44 * 45 - * BIT[4, 0]: [CN2, BKXSEL] 46 - * 10 = CMD2BK0, Command2 BK0 47 - * 11 = CMD2BK1, Command2 BK1 48 - * 00 = Command2 disable 45 + * BIT[4].....CN2 46 + * BIT[1:0]...BKXSEL 47 + * 1:00 = CMD2BK0, Command2 BK0 48 + * 1:01 = CMD2BK1, Command2 BK1 49 + * 1:11 = CMD2BK3, Command2 BK3 50 + * 0:00 = Command2 disable 49 51 */ 50 - #define DSI_CMD2BK1_SEL 0x11 51 52 #define DSI_CMD2BK0_SEL 0x10 53 + #define DSI_CMD2BK1_SEL 0x11 54 + #define DSI_CMD2BK3_SEL 0x13 52 55 #define DSI_CMD2BKX_SEL_NONE 0x00 53 56 54 57 /* Command2, BK0 bytes */ ··· 332 329 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); 333 330 } 334 331 332 + static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701) 333 + { 334 + ST7701_DSI(st7701, 0xEE, 0x42); 335 + ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); 336 + 337 + ST7701_DSI(st7701, 0xE1, 338 + 0x04, 0xA0, 0x06, 0xA0, 339 + 0x05, 0xA0, 0x07, 0xA0, 340 + 0x00, 0x44, 0x44); 341 + ST7701_DSI(st7701, 0xE2, 342 + 0x00, 0x00, 0x00, 0x00, 343 + 0x00, 0x00, 0x00, 0x00, 344 + 0x00, 0x00, 0x00, 0x00); 345 + ST7701_DSI(st7701, 0xE3, 346 + 0x00, 0x00, 0x22, 0x22); 347 + ST7701_DSI(st7701, 0xE4, 0x44, 0x44); 348 + ST7701_DSI(st7701, 0xE5, 349 + 0x0C, 0x90, 0xA0, 0xA0, 350 + 0x0E, 0x92, 0xA0, 0xA0, 351 + 0x08, 0x8C, 0xA0, 0xA0, 352 + 0x0A, 0x8E, 0xA0, 0xA0); 353 + ST7701_DSI(st7701, 0xE6, 354 + 0x00, 0x00, 0x22, 0x22); 355 + ST7701_DSI(st7701, 0xE7, 0x44, 0x44); 356 + ST7701_DSI(st7701, 0xE8, 357 + 0x0D, 0x91, 0xA0, 0xA0, 358 + 0x0F, 0x93, 0xA0, 0xA0, 359 + 0x09, 0x8D, 0xA0, 0xA0, 360 + 0x0B, 0x8F, 0xA0, 0xA0); 361 + ST7701_DSI(st7701, 0xEB, 362 + 0x00, 0x00, 0xE4, 0xE4, 363 + 0x44, 0x00, 0x00); 364 + ST7701_DSI(st7701, 0xED, 365 + 0xFF, 0xF5, 0x47, 0x6F, 366 + 0x0B, 0xA1, 0xAB, 0xFF, 367 + 0xFF, 0xBA, 0x1A, 0xB0, 368 + 0xF6, 0x74, 0x5F, 0xFF); 369 + ST7701_DSI(st7701, 0xEF, 370 + 0x08, 0x08, 0x08, 0x40, 371 + 0x3F, 0x64); 372 + 373 + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 374 + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 375 + 376 + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 377 + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); 378 + ST7701_DSI(st7701, 0xE6, 0x7C); 379 + ST7701_DSI(st7701, 0xE8, 0x00, 0x0E); 380 + 381 + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 382 + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 383 + ST7701_DSI(st7701, 0x11); 384 + msleep(120); 385 + 386 + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 387 + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); 388 + ST7701_DSI(st7701, 0xE8, 0x00, 0x0C); 389 + msleep(10); 390 + ST7701_DSI(st7701, 0xE8, 0x00, 0x00); 391 + 392 + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 393 + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 394 + ST7701_DSI(st7701, 0x11); 395 + msleep(120); 396 + ST7701_DSI(st7701, 0xE8, 0x00, 0x00); 397 + 398 + ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 399 + 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 400 + 401 + ST7701_DSI(st7701, 0x3A, 0x70); 402 + } 403 + 335 404 static int st7701_prepare(struct drm_panel *panel) 336 405 { 337 406 struct st7701 *st7701 = panel_to_st7701(panel); ··· 607 532 .gip_sequence = ts8550b_gip_sequence, 608 533 }; 609 534 535 + static const struct drm_display_mode dmt028vghmcmi_1a_mode = { 536 + .clock = 22325, 537 + 538 + .hdisplay = 480, 539 + .hsync_start = 480 + 40, 540 + .hsync_end = 480 + 40 + 4, 541 + .htotal = 480 + 40 + 4 + 20, 542 + 543 + .vdisplay = 640, 544 + .vsync_start = 640 + 2, 545 + .vsync_end = 640 + 2 + 40, 546 + .vtotal = 640 + 2 + 40 + 16, 547 + 548 + .width_mm = 56, 549 + .height_mm = 78, 550 + 551 + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 552 + 553 + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 554 + }; 555 + 556 + static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = { 557 + .mode = &dmt028vghmcmi_1a_mode, 558 + .lanes = 2, 559 + .format = MIPI_DSI_FMT_RGB888, 560 + .panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */ 561 + 562 + .pv_gamma = { 563 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 564 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 565 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 566 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), 567 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 568 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), 569 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), 570 + 571 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 572 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 573 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 574 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), 575 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 576 + 577 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), 578 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), 579 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 580 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 581 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), 582 + 583 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), 584 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 585 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), 586 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 587 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 588 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 589 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 590 + }, 591 + .nv_gamma = { 592 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 593 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 594 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 595 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), 596 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 597 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), 598 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), 599 + 600 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 601 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 602 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 603 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), 604 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 605 + 606 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 607 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), 608 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), 609 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 610 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), 611 + 612 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), 613 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 614 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), 615 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 616 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 617 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 618 + CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 619 + }, 620 + .nlinv = 1, 621 + .vop_uv = 4800000, 622 + .vcom_uv = 1650000, 623 + .vgh_mv = 15000, 624 + .vgl_mv = -10170, 625 + .avdd_mv = 6600, 626 + .avcl_mv = -4400, 627 + .gamma_op_bias = OP_BIAS_MIDDLE, 628 + .input_op_bias = OP_BIAS_MIN, 629 + .output_op_bias = OP_BIAS_MIN, 630 + .t2d_ns = 1600, 631 + .t3d_ns = 10400, 632 + .eot_en = true, 633 + .gip_sequence = dmt028vghmcmi_1a_gip_sequence, 634 + }; 635 + 610 636 static int st7701_dsi_probe(struct mipi_dsi_device *dsi) 611 637 { 612 638 const struct st7701_panel_desc *desc; ··· 774 598 } 775 599 776 600 static const struct of_device_id st7701_of_match[] = { 601 + { .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc }, 777 602 { .compatible = "techstar,ts8550b", .data = &ts8550b_desc }, 778 603 { } 779 604 };