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dt-bindings: phy: migrate combo QMP PHY bindings to qcom,sc8280xp-qmp-usb43dp-phy.yaml

Migrate legacy bindings (described in qcom,sc7180-qmp-usb3-dp-phy.yaml)
to qcom,sc8280xp-qmp-usb43dp-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711120916.4165894-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul
57a79ce9 f5a8ecef

+44 -286
-284
Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml
··· 1 - # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 - 3 - %YAML 1.2 4 - --- 5 - $id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml# 6 - $schema: http://devicetree.org/meta-schemas/core.yaml# 7 - 8 - title: Qualcomm QMP USB3 DP PHY controller (SC7180) 9 - 10 - description: 11 - The QMP PHY controller supports physical layer functionality for a number of 12 - controllers on Qualcomm chipsets, such as, PCIe, UFS and USB. 13 - 14 - Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see 15 - qcom,sc8280xp-qmp-usb43dp-phy.yaml. 16 - 17 - maintainers: 18 - - Wesley Cheng <quic_wcheng@quicinc.com> 19 - 20 - properties: 21 - compatible: 22 - oneOf: 23 - - enum: 24 - - qcom,sc7180-qmp-usb3-dp-phy 25 - - qcom,sc8180x-qmp-usb3-dp-phy 26 - - qcom,sdm845-qmp-usb3-dp-phy 27 - - qcom,sm8150-qmp-usb3-dp-phy 28 - - qcom,sm8250-qmp-usb3-dp-phy 29 - - items: 30 - - enum: 31 - - qcom,sc7280-qmp-usb3-dp-phy 32 - - const: qcom,sm8250-qmp-usb3-dp-phy 33 - 34 - reg: 35 - items: 36 - - description: Address and length of PHY's USB serdes block. 37 - - description: Address and length of the DP_COM control block. 38 - - description: Address and length of PHY's DP serdes block. 39 - 40 - reg-names: 41 - items: 42 - - const: usb 43 - - const: dp_com 44 - - const: dp 45 - 46 - "#address-cells": 47 - enum: [ 1, 2 ] 48 - 49 - "#size-cells": 50 - enum: [ 1, 2 ] 51 - 52 - ranges: true 53 - 54 - clocks: 55 - minItems: 3 56 - maxItems: 4 57 - 58 - clock-names: 59 - minItems: 3 60 - maxItems: 4 61 - 62 - power-domains: 63 - maxItems: 1 64 - 65 - orientation-switch: 66 - description: Flag the port as possible handler of orientation switching 67 - type: boolean 68 - 69 - resets: 70 - items: 71 - - description: reset of phy block. 72 - - description: phy common block reset. 73 - 74 - reset-names: 75 - items: 76 - - const: phy 77 - - const: common 78 - 79 - vdda-phy-supply: 80 - description: 81 - Phandle to a regulator supply to PHY core block. 82 - 83 - vdda-pll-supply: 84 - description: 85 - Phandle to 1.8V regulator supply to PHY refclk pll block. 86 - 87 - vddp-ref-clk-supply: 88 - description: 89 - Phandle to a regulator supply to any specific refclk pll block. 90 - 91 - # Required nodes: 92 - patternProperties: 93 - "^usb3-phy@[0-9a-f]+$": 94 - type: object 95 - additionalProperties: false 96 - description: 97 - The USB3 PHY. 98 - 99 - properties: 100 - reg: 101 - items: 102 - - description: Address and length of TX. 103 - - description: Address and length of RX. 104 - - description: Address and length of PCS. 105 - - description: Address and length of TX2. 106 - - description: Address and length of RX2. 107 - - description: Address and length of pcs_misc. 108 - 109 - clocks: 110 - items: 111 - - description: pipe clock 112 - 113 - clock-names: 114 - deprecated: true 115 - items: 116 - - const: pipe0 117 - 118 - clock-output-names: 119 - items: 120 - - const: usb3_phy_pipe_clk_src 121 - 122 - '#clock-cells': 123 - const: 0 124 - 125 - '#phy-cells': 126 - const: 0 127 - 128 - required: 129 - - reg 130 - - clocks 131 - - '#clock-cells' 132 - - '#phy-cells' 133 - 134 - "^dp-phy@[0-9a-f]+$": 135 - type: object 136 - additionalProperties: false 137 - description: 138 - The DP PHY. 139 - 140 - properties: 141 - reg: 142 - items: 143 - - description: Address and length of TX. 144 - - description: Address and length of RX. 145 - - description: Address and length of PCS. 146 - - description: Address and length of TX2. 147 - - description: Address and length of RX2. 148 - 149 - '#clock-cells': 150 - const: 1 151 - 152 - '#phy-cells': 153 - const: 0 154 - 155 - required: 156 - - reg 157 - - '#clock-cells' 158 - - '#phy-cells' 159 - 160 - required: 161 - - compatible 162 - - reg 163 - - "#address-cells" 164 - - "#size-cells" 165 - - ranges 166 - - clocks 167 - - clock-names 168 - - resets 169 - - reset-names 170 - - vdda-phy-supply 171 - - vdda-pll-supply 172 - 173 - allOf: 174 - - if: 175 - properties: 176 - compatible: 177 - enum: 178 - - qcom,sc7180-qmp-usb3-dp-phy 179 - - qcom,sdm845-qmp-usb3-dp-phy 180 - then: 181 - properties: 182 - clocks: 183 - items: 184 - - description: Phy aux clock 185 - - description: Phy config clock 186 - - description: 19.2 MHz ref clk 187 - - description: Phy common block aux clock 188 - clock-names: 189 - items: 190 - - const: aux 191 - - const: cfg_ahb 192 - - const: ref 193 - - const: com_aux 194 - 195 - - if: 196 - properties: 197 - compatible: 198 - enum: 199 - - qcom,sc8180x-qmp-usb3-dp-phy 200 - - qcom,sm8150-qmp-usb3-dp-phy 201 - then: 202 - properties: 203 - clocks: 204 - items: 205 - - description: Phy aux clock 206 - - description: 19.2 MHz ref clk 207 - - description: Phy common block aux clock 208 - clock-names: 209 - items: 210 - - const: aux 211 - - const: ref 212 - - const: com_aux 213 - 214 - - if: 215 - properties: 216 - compatible: 217 - enum: 218 - - qcom,sm8250-qmp-usb3-dp-phy 219 - then: 220 - properties: 221 - clocks: 222 - items: 223 - - description: Phy aux clock 224 - - description: Board XO source 225 - - description: Phy common block aux clock 226 - clock-names: 227 - items: 228 - - const: aux 229 - - const: ref_clk_src 230 - - const: com_aux 231 - 232 - additionalProperties: false 233 - 234 - examples: 235 - - | 236 - #include <dt-bindings/clock/qcom,gcc-sdm845.h> 237 - usb_1_qmpphy: phy-wrapper@88e9000 { 238 - compatible = "qcom,sdm845-qmp-usb3-dp-phy"; 239 - reg = <0x088e9000 0x18c>, 240 - <0x088e8000 0x10>, 241 - <0x088ea000 0x40>; 242 - reg-names = "usb", "dp_com", "dp"; 243 - #address-cells = <1>; 244 - #size-cells = <1>; 245 - ranges = <0x0 0x088e9000 0x2000>; 246 - 247 - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 248 - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 249 - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 250 - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 251 - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 252 - 253 - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 254 - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 255 - reset-names = "phy", "common"; 256 - 257 - vdda-phy-supply = <&vdda_usb2_ss_1p2>; 258 - vdda-pll-supply = <&vdda_usb2_ss_core>; 259 - 260 - orientation-switch; 261 - 262 - usb3-phy@200 { 263 - reg = <0x200 0x128>, 264 - <0x400 0x200>, 265 - <0xc00 0x218>, 266 - <0x600 0x128>, 267 - <0x800 0x200>, 268 - <0xa00 0x100>; 269 - #clock-cells = <0>; 270 - #phy-cells = <0>; 271 - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 272 - clock-output-names = "usb3_phy_pipe_clk_src"; 273 - }; 274 - 275 - dp-phy@88ea200 { 276 - reg = <0xa200 0x200>, 277 - <0xa400 0x200>, 278 - <0xaa00 0x200>, 279 - <0xa600 0x200>, 280 - <0xa800 0x200>; 281 - #clock-cells = <1>; 282 - #phy-cells = <0>; 283 - }; 284 - };
+44 -2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
··· 16 16 properties: 17 17 compatible: 18 18 enum: 19 + - qcom,sc7180-qmp-usb3-dp-phy 20 + - qcom,sc7280-qmp-usb3-dp-phy 21 + - qcom,sc8180x-qmp-usb3-dp-phy 19 22 - qcom,sc8280xp-qmp-usb43dp-phy 23 + - qcom,sdm845-qmp-usb3-dp-phy 20 24 - qcom,sm6350-qmp-usb3-dp-phy 25 + - qcom,sm8150-qmp-usb3-dp-phy 26 + - qcom,sm8250-qmp-usb3-dp-phy 21 27 - qcom,sm8350-qmp-usb3-dp-phy 22 28 - qcom,sm8450-qmp-usb3-dp-phy 23 29 - qcom,sm8550-qmp-usb3-dp-phy ··· 32 26 maxItems: 1 33 27 34 28 clocks: 35 - maxItems: 4 29 + minItems: 4 30 + maxItems: 5 36 31 37 32 clock-names: 33 + minItems: 4 38 34 items: 39 35 - const: aux 40 36 - const: ref 41 37 - const: com_aux 42 38 - const: usb3_pipe 39 + - const: cfg_ahb 43 40 44 41 power-domains: 45 42 maxItems: 1 ··· 94 85 - reg 95 86 - clocks 96 87 - clock-names 97 - - power-domains 98 88 - resets 99 89 - reset-names 100 90 - vdda-phy-supply 101 91 - vdda-pll-supply 102 92 - "#clock-cells" 103 93 - "#phy-cells" 94 + 95 + allOf: 96 + - if: 97 + properties: 98 + compatible: 99 + enum: 100 + - qcom,sc7180-qmp-usb3-dp-phy 101 + - qcom,sdm845-qmp-usb3-dp-phy 102 + then: 103 + properties: 104 + clocks: 105 + maxItems: 5 106 + clock-names: 107 + maxItems: 5 108 + else: 109 + properties: 110 + clocks: 111 + maxItems: 4 112 + clock-names: 113 + maxItems: 4 114 + 115 + - if: 116 + properties: 117 + compatible: 118 + enum: 119 + - qcom,sc8280xp-qmp-usb43dp-phy 120 + - qcom,sm6350-qmp-usb3-dp-phy 121 + - qcom,sm8550-qmp-usb3-dp-phy 122 + then: 123 + required: 124 + - power-domains 125 + else: 126 + properties: 127 + power-domains: false 104 128 105 129 additionalProperties: false 106 130