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dt-bindings: pinctrl: describe qcs8300-tlmm
Add DT bindings for the TLMM controller on QCS8300 platforms.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/20241018-qcs8300_tlmm-v3-1-8b8d3957cf1a@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Jingyi Wang
and committed by
Linus Walleij
57785359
f8d355bf
+118
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Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
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Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,qcs8300-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. QCS8300 TLMM block
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maintainers:
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- Jingyi Wang <quic_jingyw@quicinc.com>
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description: |
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Top Level Mode Multiplexer pin controller in Qualcomm QCS8300 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,qcs8300-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 67
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gpio-line-names:
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maxItems: 133
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-qcs8300-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-qcs8300-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-qcs8300-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
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- enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aoss_cti, atest_char, atest_usb2, audio_ref, cam_mclk,
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cci_async, cci_i2c_scl, cci_i2c_sda, cci_timer, cri_trng,
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dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3,
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edp0_hot, edp0_lcd, edp1_lcd, egpio, emac0_mcg0, emac0_mcg1,
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emac0_mcg2, emac0_mcg3, emac0_mdc, emac0_mdio, emac0_ptp_aux,
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emac0_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, gcc_gp5,
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gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, jitter_bist,
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mdp0_vsync0, mdp0_vsync1, mdp0_vsync3, mdp0_vsync6, mdp0_vsync7,
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mdp_vsync, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
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mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
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mi2s_mclk1, pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist,
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pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3,
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qdss_cti, qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3,
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qup0_se4, qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1,
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qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7,
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qup2_se0, sailss_emac0, sailss_ospi, sail_top, sgmii_phy,
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tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
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tsense_pwm2, tsense_pwm3, tsense_pwm4, usb2phy_ac,
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vsense_trigger ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,qcs8300-tlmm";
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reg = <0x0f100000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 133>;
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interrupt-controller;
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#interrupt-cells = <2>;
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qup-uart7-state {
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pins = "gpio43", "gpio44";
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function = "qup0_se7";
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};
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};
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...