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KVM: PPC: Book3S HV: Save/restore new PMU registers

Power ISA v3.1 has added new performance monitoring unit (PMU) special
purpose registers (SPRs). They are:

Monitor Mode Control Register 3 (MMCR3)
Sampled Instruction Event Register A (SIER2)
Sampled Instruction Event Register B (SIER3)

Add support to save/restore these new SPRs while entering/exiting
guest. Also include changes to support KVM_REG_PPC_MMCR3/SIER2/SIER3.
Add new SPRs to KVM API documentation.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1594996707-3727-6-git-send-email-atrajeev@linux.vnet.ibm.com

authored by

Athira Rajeev and committed by
Michael Ellerman 5752fe0b c718547e

+71 -5
+3
Documentation/virt/kvm/api.rst
··· 2156 2156 PPC KVM_REG_PPC_MMCRA 64 2157 2157 PPC KVM_REG_PPC_MMCR2 64 2158 2158 PPC KVM_REG_PPC_MMCRS 64 2159 + PPC KVM_REG_PPC_MMCR3 64 2159 2160 PPC KVM_REG_PPC_SIAR 64 2160 2161 PPC KVM_REG_PPC_SDAR 64 2161 2162 PPC KVM_REG_PPC_SIER 64 2163 + PPC KVM_REG_PPC_SIER2 64 2164 + PPC KVM_REG_PPC_SIER3 64 2162 2165 PPC KVM_REG_PPC_PMC1 32 2163 2166 PPC KVM_REG_PPC_PMC2 32 2164 2167 PPC KVM_REG_PPC_PMC3 32
+1 -1
arch/powerpc/include/asm/kvm_book3s_asm.h
··· 119 119 void __iomem *xive_tima_virt; 120 120 u32 saved_xirr; 121 121 u64 dabr; 122 - u64 host_mmcr[7]; /* MMCR 0,1,A, SIAR, SDAR, MMCR2, SIER */ 122 + u64 host_mmcr[10]; /* MMCR 0,1,A, SIAR, SDAR, MMCR2, SIER, MMCR3, SIER2/3 */ 123 123 u32 host_pmc[8]; 124 124 u64 host_purr; 125 125 u64 host_spurr;
+2 -2
arch/powerpc/include/asm/kvm_host.h
··· 637 637 u32 ccr1; 638 638 u32 dbsr; 639 639 640 - u64 mmcr[3]; /* MMCR0, MMCR1, MMCR2 */ 640 + u64 mmcr[4]; /* MMCR0, MMCR1, MMCR2, MMCR3 */ 641 641 u64 mmcra; 642 642 u64 mmcrs; 643 643 u32 pmc[8]; 644 644 u32 spmc[2]; 645 645 u64 siar; 646 646 u64 sdar; 647 - u64 sier; 647 + u64 sier[3]; 648 648 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 649 649 u64 tfhar; 650 650 u64 texasr;
+5
arch/powerpc/include/uapi/asm/kvm.h
··· 640 640 #define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf) 641 641 #define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0) 642 642 643 + /* POWER10 registers */ 644 + #define KVM_REG_PPC_MMCR3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1) 645 + #define KVM_REG_PPC_SIER2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2) 646 + #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) 647 + 643 648 /* Transactional Memory checkpointed state: 644 649 * This is all GPRs, all VSX regs and a subset of SPRs 645 650 */
+3
arch/powerpc/kernel/asm-offsets.c
··· 698 698 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]); 699 699 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]); 700 700 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]); 701 + HSTATE_FIELD(HSTATE_MMCR3, host_mmcr[7]); 702 + HSTATE_FIELD(HSTATE_SIER2, host_mmcr[8]); 703 + HSTATE_FIELD(HSTATE_SIER3, host_mmcr[9]); 701 704 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]); 702 705 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]); 703 706 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
+20 -2
arch/powerpc/kvm/book3s_hv.c
··· 1692 1692 case KVM_REG_PPC_MMCRS: 1693 1693 *val = get_reg_val(id, vcpu->arch.mmcrs); 1694 1694 break; 1695 + case KVM_REG_PPC_MMCR3: 1696 + *val = get_reg_val(id, vcpu->arch.mmcr[3]); 1697 + break; 1695 1698 case KVM_REG_PPC_PMC1 ... KVM_REG_PPC_PMC8: 1696 1699 i = id - KVM_REG_PPC_PMC1; 1697 1700 *val = get_reg_val(id, vcpu->arch.pmc[i]); ··· 1710 1707 *val = get_reg_val(id, vcpu->arch.sdar); 1711 1708 break; 1712 1709 case KVM_REG_PPC_SIER: 1713 - *val = get_reg_val(id, vcpu->arch.sier); 1710 + *val = get_reg_val(id, vcpu->arch.sier[0]); 1711 + break; 1712 + case KVM_REG_PPC_SIER2: 1713 + *val = get_reg_val(id, vcpu->arch.sier[1]); 1714 + break; 1715 + case KVM_REG_PPC_SIER3: 1716 + *val = get_reg_val(id, vcpu->arch.sier[2]); 1714 1717 break; 1715 1718 case KVM_REG_PPC_IAMR: 1716 1719 *val = get_reg_val(id, vcpu->arch.iamr); ··· 1931 1922 case KVM_REG_PPC_MMCRS: 1932 1923 vcpu->arch.mmcrs = set_reg_val(id, *val); 1933 1924 break; 1925 + case KVM_REG_PPC_MMCR3: 1926 + *val = get_reg_val(id, vcpu->arch.mmcr[3]); 1927 + break; 1934 1928 case KVM_REG_PPC_PMC1 ... KVM_REG_PPC_PMC8: 1935 1929 i = id - KVM_REG_PPC_PMC1; 1936 1930 vcpu->arch.pmc[i] = set_reg_val(id, *val); ··· 1949 1937 vcpu->arch.sdar = set_reg_val(id, *val); 1950 1938 break; 1951 1939 case KVM_REG_PPC_SIER: 1952 - vcpu->arch.sier = set_reg_val(id, *val); 1940 + vcpu->arch.sier[0] = set_reg_val(id, *val); 1941 + break; 1942 + case KVM_REG_PPC_SIER2: 1943 + vcpu->arch.sier[1] = set_reg_val(id, *val); 1944 + break; 1945 + case KVM_REG_PPC_SIER3: 1946 + vcpu->arch.sier[2] = set_reg_val(id, *val); 1953 1947 break; 1954 1948 case KVM_REG_PPC_IAMR: 1955 1949 vcpu->arch.iamr = set_reg_val(id, *val);
+8
arch/powerpc/kvm/book3s_hv_interrupts.S
··· 140 140 std r8, HSTATE_MMCR2(r13) 141 141 std r9, HSTATE_SIER(r13) 142 142 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 143 + BEGIN_FTR_SECTION 144 + mfspr r5, SPRN_MMCR3 145 + mfspr r6, SPRN_SIER2 146 + mfspr r7, SPRN_SIER3 147 + std r5, HSTATE_MMCR3(r13) 148 + std r6, HSTATE_SIER2(r13) 149 + std r7, HSTATE_SIER3(r13) 150 + END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31) 143 151 mfspr r3, SPRN_PMC1 144 152 mfspr r5, SPRN_PMC2 145 153 mfspr r6, SPRN_PMC3
+24
arch/powerpc/kvm/book3s_hv_rmhandlers.S
··· 3436 3436 mtspr SPRN_SIAR, r7 3437 3437 mtspr SPRN_SDAR, r8 3438 3438 BEGIN_FTR_SECTION 3439 + ld r5, VCPU_MMCR + 24(r4) 3440 + ld r6, VCPU_SIER + 8(r4) 3441 + ld r7, VCPU_SIER + 16(r4) 3442 + mtspr SPRN_MMCR3, r5 3443 + mtspr SPRN_SIER2, r6 3444 + mtspr SPRN_SIER3, r7 3445 + END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31) 3446 + BEGIN_FTR_SECTION 3439 3447 ld r5, VCPU_MMCR + 16(r4) 3440 3448 ld r6, VCPU_SIER(r4) 3441 3449 mtspr SPRN_MMCR2, r5 ··· 3504 3496 mtspr SPRN_MMCR2, r8 3505 3497 mtspr SPRN_SIER, r9 3506 3498 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 3499 + BEGIN_FTR_SECTION 3500 + ld r5, HSTATE_MMCR3(r13) 3501 + ld r6, HSTATE_SIER2(r13) 3502 + ld r7, HSTATE_SIER3(r13) 3503 + mtspr SPRN_MMCR3, r5 3504 + mtspr SPRN_SIER2, r6 3505 + mtspr SPRN_SIER3, r7 3506 + END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31) 3507 3507 mtspr SPRN_MMCR0, r3 3508 3508 isync 3509 3509 mtlr r0 ··· 3571 3555 BEGIN_FTR_SECTION 3572 3556 std r10, VCPU_MMCR + 16(r9) 3573 3557 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 3558 + BEGIN_FTR_SECTION 3559 + mfspr r5, SPRN_MMCR3 3560 + mfspr r6, SPRN_SIER2 3561 + mfspr r7, SPRN_SIER3 3562 + std r5, VCPU_MMCR + 24(r9) 3563 + std r6, VCPU_SIER + 8(r9) 3564 + std r7, VCPU_SIER + 16(r9) 3565 + END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31) 3574 3566 std r7, VCPU_SIAR(r9) 3575 3567 std r8, VCPU_SDAR(r9) 3576 3568 mfspr r3, SPRN_PMC1
+5
tools/arch/powerpc/include/uapi/asm/kvm.h
··· 640 640 #define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf) 641 641 #define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0) 642 642 643 + /* POWER10 registers */ 644 + #define KVM_REG_PPC_MMCR3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1) 645 + #define KVM_REG_PPC_SIER2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2) 646 + #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) 647 + 643 648 /* Transactional Memory checkpointed state: 644 649 * This is all GPRs, all VSX regs and a subset of SPRs 645 650 */