clk: st: flexgen: embed soc clock outputs within compatible data

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.

In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.

Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20210331201632.24530-3-avolmat@me.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Alain Volmat and committed by

Stephen Boyd 4 years ago 574dffc2 b5a87e69

+353 -14

1 changed file

expand all

drivers

clk

clk-flexgen.c

+353 -14

drivers/clk/st/clk-flexgen.c

··· 16 16 #include <linux/of.h> 17 17 #include <linux/of_address.h> 18 18 19 + struct clkgen_clk_out { 20 + const char *name; 21 + unsigned long flags; 22 + }; 23 + 19 24 struct clkgen_data { 20 25 unsigned long flags; 21 26 bool mode; 27 + const struct clkgen_clk_out *outputs; 28 + const unsigned int outputs_nb; 22 29 }; 23 30 24 31 struct flexgen { ··· 302 295 .mode = 1, 303 296 }; 304 297 298 + static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = { 299 + /* This clk needs to be on so that memory interface is accessible */ 300 + { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL }, 301 + }; 302 + 303 + static const struct clkgen_data clkgen_stih407_a0 = { 304 + .outputs = clkgen_stih407_a0_clk_out, 305 + .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out), 306 + }; 307 + 308 + static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = { 309 + /* Those clks need to be on so that memory interface is accessible */ 310 + { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL }, 311 + { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL }, 312 + }; 313 + 314 + static const struct clkgen_data clkgen_stih410_a0 = { 315 + .outputs = clkgen_stih410_a0_clk_out, 316 + .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out), 317 + }; 318 + 319 + static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = { 320 + { .name = "clk-icn-gpu", }, 321 + { .name = "clk-fdma", }, 322 + { .name = "clk-nand", }, 323 + { .name = "clk-hva", }, 324 + { .name = "clk-proc-stfe", }, 325 + { .name = "clk-proc-tp", }, 326 + { .name = "clk-rx-icn-dmu", }, 327 + { .name = "clk-rx-icn-hva", }, 328 + /* This clk needs to be on to keep bus interconnect alive */ 329 + { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL }, 330 + /* This clk needs to be on to keep bus interconnect alive */ 331 + { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL }, 332 + { .name = "clk-mmc-0", }, 333 + { .name = "clk-mmc-1", }, 334 + { .name = "clk-jpegdec", }, 335 + /* This clk needs to be on to keep A9 running */ 336 + { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL }, 337 + { .name = "clk-ic-bdisp-0", }, 338 + { .name = "clk-ic-bdisp-1", }, 339 + { .name = "clk-pp-dmu", }, 340 + { .name = "clk-vid-dmu", }, 341 + { .name = "clk-dss-lpc", }, 342 + { .name = "clk-st231-aud-0", }, 343 + { .name = "clk-st231-gp-1", }, 344 + { .name = "clk-st231-dmu", }, 345 + /* This clk needs to be on to keep bus interconnect alive */ 346 + { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL }, 347 + { .name = "clk-tx-icn-disp-1", }, 348 + /* This clk needs to be on to keep bus interconnect alive */ 349 + { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL }, 350 + { .name = "clk-stfe-frc2", }, 351 + { .name = "clk-eth-phy", }, 352 + { .name = "clk-eth-ref-phyclk", }, 353 + { .name = "clk-flash-promip", }, 354 + { .name = "clk-main-disp", }, 355 + { .name = "clk-aux-disp", }, 356 + { .name = "clk-compo-dvp", }, 357 + }; 358 + 359 + static const struct clkgen_data clkgen_stih407_c0 = { 360 + .outputs = clkgen_stih407_c0_clk_out, 361 + .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out), 362 + }; 363 + 364 + static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = { 365 + { .name = "clk-icn-gpu", }, 366 + { .name = "clk-fdma", }, 367 + { .name = "clk-nand", }, 368 + { .name = "clk-hva", }, 369 + { .name = "clk-proc-stfe", }, 370 + { .name = "clk-proc-tp", }, 371 + { .name = "clk-rx-icn-dmu", }, 372 + { .name = "clk-rx-icn-hva", }, 373 + /* This clk needs to be on to keep bus interconnect alive */ 374 + { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL }, 375 + /* This clk needs to be on to keep bus interconnect alive */ 376 + { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL }, 377 + { .name = "clk-mmc-0", }, 378 + { .name = "clk-mmc-1", }, 379 + { .name = "clk-jpegdec", }, 380 + /* This clk needs to be on to keep A9 running */ 381 + { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL }, 382 + { .name = "clk-ic-bdisp-0", }, 383 + { .name = "clk-ic-bdisp-1", }, 384 + { .name = "clk-pp-dmu", }, 385 + { .name = "clk-vid-dmu", }, 386 + { .name = "clk-dss-lpc", }, 387 + { .name = "clk-st231-aud-0", }, 388 + { .name = "clk-st231-gp-1", }, 389 + { .name = "clk-st231-dmu", }, 390 + /* This clk needs to be on to keep bus interconnect alive */ 391 + { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL }, 392 + { .name = "clk-tx-icn-disp-1", }, 393 + /* This clk needs to be on to keep bus interconnect alive */ 394 + { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL }, 395 + { .name = "clk-stfe-frc2", }, 396 + { .name = "clk-eth-phy", }, 397 + { .name = "clk-eth-ref-phyclk", }, 398 + { .name = "clk-flash-promip", }, 399 + { .name = "clk-main-disp", }, 400 + { .name = "clk-aux-disp", }, 401 + { .name = "clk-compo-dvp", }, 402 + { .name = "clk-tx-icn-hades", }, 403 + { .name = "clk-rx-icn-hades", }, 404 + /* This clk needs to be on to keep bus interconnect alive */ 405 + { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL }, 406 + { .name = "clk-pp-hades", }, 407 + { .name = "clk-clust-hades", }, 408 + { .name = "clk-hwpe-hades", }, 409 + { .name = "clk-fc-hades", }, 410 + }; 411 + 412 + static const struct clkgen_data clkgen_stih410_c0 = { 413 + .outputs = clkgen_stih410_c0_clk_out, 414 + .outputs_nb = ARRAY_SIZE(clkgen_stih410_c0_clk_out), 415 + }; 416 + 417 + static const struct clkgen_clk_out clkgen_stih418_c0_clk_out[] = { 418 + { .name = "clk-icn-gpu", }, 419 + { .name = "clk-fdma", }, 420 + { .name = "clk-nand", }, 421 + { .name = "clk-hva", }, 422 + { .name = "clk-proc-stfe", }, 423 + { .name = "clk-tp", }, 424 + /* This clk needs to be on to keep bus interconnect alive */ 425 + { .name = "clk-rx-icn-dmu", .flags = CLK_IS_CRITICAL }, 426 + /* This clk needs to be on to keep bus interconnect alive */ 427 + { .name = "clk-rx-icn-hva", .flags = CLK_IS_CRITICAL }, 428 + { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL }, 429 + /* This clk needs to be on to keep bus interconnect alive */ 430 + { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL }, 431 + { .name = "clk-mmc-0", }, 432 + { .name = "clk-mmc-1", }, 433 + { .name = "clk-jpegdec", }, 434 + /* This clk needs to be on to keep bus interconnect alive */ 435 + { .name = "clk-icn-reg", .flags = CLK_IS_CRITICAL }, 436 + { .name = "clk-proc-bdisp-0", }, 437 + { .name = "clk-proc-bdisp-1", }, 438 + { .name = "clk-pp-dmu", }, 439 + { .name = "clk-vid-dmu", }, 440 + { .name = "clk-dss-lpc", }, 441 + { .name = "clk-st231-aud-0", }, 442 + { .name = "clk-st231-gp-1", }, 443 + { .name = "clk-st231-dmu", }, 444 + /* This clk needs to be on to keep bus interconnect alive */ 445 + { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL }, 446 + /* This clk needs to be on to keep bus interconnect alive */ 447 + { .name = "clk-tx-icn-1", .flags = CLK_IS_CRITICAL }, 448 + /* This clk needs to be on to keep bus interconnect alive */ 449 + { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL }, 450 + { .name = "clk-stfe-frc2", }, 451 + { .name = "clk-eth-phyref", }, 452 + { .name = "clk-eth-ref-phyclk", }, 453 + { .name = "clk-flash-promip", }, 454 + { .name = "clk-main-disp", }, 455 + { .name = "clk-aux-disp", }, 456 + { .name = "clk-compo-dvp", }, 457 + /* This clk needs to be on to keep bus interconnect alive */ 458 + { .name = "clk-tx-icn-hades", .flags = CLK_IS_CRITICAL }, 459 + /* This clk needs to be on to keep bus interconnect alive */ 460 + { .name = "clk-rx-icn-hades", .flags = CLK_IS_CRITICAL }, 461 + /* This clk needs to be on to keep bus interconnect alive */ 462 + { .name = "clk-icn-reg-16", .flags = CLK_IS_CRITICAL }, 463 + { .name = "clk-pp-hevc", }, 464 + { .name = "clk-clust-hevc", }, 465 + { .name = "clk-hwpe-hevc", }, 466 + { .name = "clk-fc-hevc", }, 467 + { .name = "clk-proc-mixer", }, 468 + { .name = "clk-proc-sc", }, 469 + { .name = "clk-avsp-hevc", }, 470 + }; 471 + 472 + static const struct clkgen_data clkgen_stih418_c0 = { 473 + .outputs = clkgen_stih418_c0_clk_out, 474 + .outputs_nb = ARRAY_SIZE(clkgen_stih418_c0_clk_out), 475 + }; 476 + 477 + static const struct clkgen_clk_out clkgen_stih407_d0_clk_out[] = { 478 + { .name = "clk-pcm-0", }, 479 + { .name = "clk-pcm-1", }, 480 + { .name = "clk-pcm-2", }, 481 + { .name = "clk-spdiff", }, 482 + }; 483 + 484 + static const struct clkgen_data clkgen_stih407_d0 = { 485 + .flags = CLK_SET_RATE_PARENT, 486 + .outputs = clkgen_stih407_d0_clk_out, 487 + .outputs_nb = ARRAY_SIZE(clkgen_stih407_d0_clk_out), 488 + }; 489 + 490 + static const struct clkgen_clk_out clkgen_stih410_d0_clk_out[] = { 491 + { .name = "clk-pcm-0", }, 492 + { .name = "clk-pcm-1", }, 493 + { .name = "clk-pcm-2", }, 494 + { .name = "clk-spdiff", }, 495 + { .name = "clk-pcmr10-master", }, 496 + { .name = "clk-usb2-phy", }, 497 + }; 498 + 499 + static const struct clkgen_data clkgen_stih410_d0 = { 500 + .flags = CLK_SET_RATE_PARENT, 501 + .outputs = clkgen_stih410_d0_clk_out, 502 + .outputs_nb = ARRAY_SIZE(clkgen_stih410_d0_clk_out), 503 + }; 504 + 505 + static const struct clkgen_clk_out clkgen_stih407_d2_clk_out[] = { 506 + { .name = "clk-pix-main-disp", }, 507 + { .name = "clk-pix-pip", }, 508 + { .name = "clk-pix-gdp1", }, 509 + { .name = "clk-pix-gdp2", }, 510 + { .name = "clk-pix-gdp3", }, 511 + { .name = "clk-pix-gdp4", }, 512 + { .name = "clk-pix-aux-disp", }, 513 + { .name = "clk-denc", }, 514 + { .name = "clk-pix-hddac", }, 515 + { .name = "clk-hddac", }, 516 + { .name = "clk-sddac", }, 517 + { .name = "clk-pix-dvo", }, 518 + { .name = "clk-dvo", }, 519 + { .name = "clk-pix-hdmi", }, 520 + { .name = "clk-tmds-hdmi", }, 521 + { .name = "clk-ref-hdmiphy", }, 522 + }; 523 + 524 + static const struct clkgen_data clkgen_stih407_d2 = { 525 + .outputs = clkgen_stih407_d2_clk_out, 526 + .outputs_nb = ARRAY_SIZE(clkgen_stih407_d2_clk_out), 527 + .flags = CLK_SET_RATE_PARENT, 528 + .mode = 1, 529 + }; 530 + 531 + static const struct clkgen_clk_out clkgen_stih418_d2_clk_out[] = { 532 + { .name = "clk-pix-main-disp", }, 533 + { .name = "", }, 534 + { .name = "", }, 535 + { .name = "", }, 536 + { .name = "", }, 537 + { .name = "clk-tmds-hdmi-div2", }, 538 + { .name = "clk-pix-aux-disp", }, 539 + { .name = "clk-denc", }, 540 + { .name = "clk-pix-hddac", }, 541 + { .name = "clk-hddac", }, 542 + { .name = "clk-sddac", }, 543 + { .name = "clk-pix-dvo", }, 544 + { .name = "clk-dvo", }, 545 + { .name = "clk-pix-hdmi", }, 546 + { .name = "clk-tmds-hdmi", }, 547 + { .name = "clk-ref-hdmiphy", }, 548 + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, 549 + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, 550 + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, 551 + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, 552 + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, 553 + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, 554 + { .name = "", }, { .name = "", }, { .name = "", }, { .name = "", }, 555 + { .name = "", }, { .name = "", }, { .name = "", }, 556 + { .name = "clk-vp9", }, 557 + }; 558 + 559 + static const struct clkgen_data clkgen_stih418_d2 = { 560 + .outputs = clkgen_stih418_d2_clk_out, 561 + .outputs_nb = ARRAY_SIZE(clkgen_stih418_d2_clk_out), 562 + .flags = CLK_SET_RATE_PARENT, 563 + .mode = 1, 564 + }; 565 + 566 + static const struct clkgen_clk_out clkgen_stih407_d3_clk_out[] = { 567 + { .name = "clk-stfe-frc1", }, 568 + { .name = "clk-tsout-0", }, 569 + { .name = "clk-tsout-1", }, 570 + { .name = "clk-mchi", }, 571 + { .name = "clk-vsens-compo", }, 572 + { .name = "clk-frc1-remote", }, 573 + { .name = "clk-lpc-0", }, 574 + { .name = "clk-lpc-1", }, 575 + }; 576 + 577 + static const struct clkgen_data clkgen_stih407_d3 = { 578 + .outputs = clkgen_stih407_d3_clk_out, 579 + .outputs_nb = ARRAY_SIZE(clkgen_stih407_d3_clk_out), 580 + }; 581 + 305 582 static const struct of_device_id flexgen_of_match[] = { 306 583 { 307 584 .compatible = "st,flexgen-audio", ··· 594 303 { 595 304 .compatible = "st,flexgen-video", 596 305 .data = &clkgen_video, 306 + }, 307 + { 308 + .compatible = "st,flexgen-stih407-a0", 309 + .data = &clkgen_stih407_a0, 310 + }, 311 + { 312 + .compatible = "st,flexgen-stih410-a0", 313 + .data = &clkgen_stih410_a0, 314 + }, 315 + { 316 + .compatible = "st,flexgen-stih407-c0", 317 + .data = &clkgen_stih407_c0, 318 + }, 319 + { 320 + .compatible = "st,flexgen-stih410-c0", 321 + .data = &clkgen_stih410_c0, 322 + }, 323 + { 324 + .compatible = "st,flexgen-stih418-c0", 325 + .data = &clkgen_stih418_c0, 326 + }, 327 + { 328 + .compatible = "st,flexgen-stih407-d0", 329 + .data = &clkgen_stih407_d0, 330 + }, 331 + { 332 + .compatible = "st,flexgen-stih410-d0", 333 + .data = &clkgen_stih410_d0, 334 + }, 335 + { 336 + .compatible = "st,flexgen-stih407-d2", 337 + .data = &clkgen_stih407_d2, 338 + }, 339 + { 340 + .compatible = "st,flexgen-stih418-d2", 341 + .data = &clkgen_stih418_d2, 342 + }, 343 + { 344 + .compatible = "st,flexgen-stih407-d3", 345 + .data = &clkgen_stih407_d3, 597 346 }, 598 347 {} 599 348 }; ··· 651 320 unsigned long flex_flags = 0; 652 321 int ret; 653 322 bool clk_mode = 0; 323 + const char *clk_name; 654 324 655 325 pnode = of_get_parent(np); 656 326 if (!pnode) ··· 679 347 if (!clk_data) 680 348 goto err; 681 349 682 - ret = of_property_count_strings(np, "clock-output-names"); 683 - if (ret <= 0) { 684 - pr_err("%s: Failed to get number of output clocks (%d)", 685 - __func__, clk_data->clk_num); 686 - goto err; 687 - } 688 - clk_data->clk_num = ret; 350 + /* First try to get output information from the compatible data */ 351 + if (!data || !data->outputs_nb || !data->outputs) { 352 + ret = of_property_count_strings(np, "clock-output-names"); 353 + if (ret <= 0) { 354 + pr_err("%s: Failed to get number of output clocks (%d)", 355 + __func__, clk_data->clk_num); 356 + goto err; 357 + } 358 + clk_data->clk_num = ret; 359 + } else 360 + clk_data->clk_num = data->outputs_nb; 689 361 690 362 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), 691 363 GFP_KERNEL); ··· 704 368 705 369 for (i = 0; i < clk_data->clk_num; i++) { 706 370 struct clk *clk; 707 - const char *clk_name; 708 371 709 - if (of_property_read_string_index(np, "clock-output-names", 710 - i, &clk_name)) { 711 - break; 372 + if (!data || !data->outputs_nb || !data->outputs) { 373 + if (of_property_read_string_index(np, 374 + "clock-output-names", 375 + i, &clk_name)) 376 + break; 377 + flex_flags &= ~CLK_IS_CRITICAL; 378 + of_clk_detect_critical(np, i, &flex_flags); 379 + } else { 380 + clk_name = data->outputs[i].name; 381 + flex_flags = data->flags | data->outputs[i].flags; 712 382 } 713 - 714 - flex_flags &= ~CLK_IS_CRITICAL; 715 - of_clk_detect_critical(np, i, &flex_flags); 716 383 717 384 /* 718 385 * If we read an empty clock name then the output is unused