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dt-bindings: pinctrl: fsl,imx6ul-pinctrl: Convert i.MX35/5x/6 to YAML

The IOMUXC controller description is almost identical on i.MX35/5x/6 SoCs,
except for the configuration bits which differ across SoCs. Rename the
fsl,imx6ul-pinctrl.yaml to fsl,imx35-pinctrl.yaml, fill in compatible
strings for the other SoCs and fill in the various bits into desciption.
This way, i.MX35/5x/6 series SoCs can all be converted to DT schema.
Remove the old text DT bindings description.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/20241017211241.170861-1-marex@denx.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Marek Vasut and committed by
Linus Walleij 56c9d1a0 b509b5e5

+184 -436
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Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
··· 1 - * Freescale IMX35 IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx35-iomuxc" 8 - - fsl,pins: two integers array, represents a group of pins mux and config 9 - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 10 - pin working on a specific function, CONFIG is the pad setting value like 11 - pull-up for this pin. Please refer to imx35 datasheet for the valid pad 12 - config settings. 13 - 14 - CONFIG bits definition: 15 - PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) 16 - PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) 17 - PAD_CTL_HYS (1 << 8) 18 - PAD_CTL_PKE (1 << 7) 19 - PAD_CTL_PUE (1 << 6) 20 - PAD_CTL_PUS_100K_DOWN (0 << 4) 21 - PAD_CTL_PUS_47K_UP (1 << 4) 22 - PAD_CTL_PUS_100K_UP (2 << 4) 23 - PAD_CTL_PUS_22K_UP (3 << 4) 24 - PAD_CTL_ODE_CMOS (0 << 3) 25 - PAD_CTL_ODE_OPENDRAIN (1 << 3) 26 - PAD_CTL_DSE_NOMINAL (0 << 1) 27 - PAD_CTL_DSE_HIGH (1 << 1) 28 - PAD_CTL_DSE_MAX (2 << 1) 29 - PAD_CTL_SRE_FAST (1 << 0) 30 - PAD_CTL_SRE_SLOW (0 << 0) 31 - 32 - Refer to imx35-pinfunc.h in device tree source folder for all available 33 - imx35 PIN_FUNC_ID.
+184
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: 13 + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory 14 + for common binding part and usage. 15 + 16 + allOf: 17 + - $ref: pinctrl.yaml# 18 + 19 + properties: 20 + compatible: 21 + oneOf: 22 + - enum: 23 + - fsl,imx35-iomuxc 24 + - fsl,imx51-iomuxc 25 + - fsl,imx53-iomuxc 26 + - fsl,imx6dl-iomuxc 27 + - fsl,imx6q-iomuxc 28 + - fsl,imx6sl-iomuxc 29 + - fsl,imx6sll-iomuxc 30 + - fsl,imx6sx-iomuxc 31 + - fsl,imx6ul-iomuxc 32 + - fsl,imx6ull-iomuxc-snvs 33 + - items: 34 + - const: fsl,imx50-iomuxc 35 + - const: fsl,imx53-iomuxc 36 + 37 + reg: 38 + maxItems: 1 39 + 40 + # Client device subnode's properties 41 + patternProperties: 42 + 'grp$': 43 + type: object 44 + description: 45 + Pinctrl node's client devices use subnodes for desired pin configuration. 46 + Client device subnodes use below standard properties. 47 + 48 + properties: 49 + fsl,pins: 50 + description: 51 + each entry consists of 6 integers and represents the mux and config 52 + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg 53 + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can 54 + be found in <arch/arm/boot/dts/nxp/imx/imx*-pinfunc.h>. The last integer 55 + CONFIG is the pad setting value like pull-up on this pin. Please 56 + refer to matching i.MX Reference Manual for detailed CONFIG settings. 57 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 58 + items: 59 + items: 60 + - description: | 61 + "mux_reg" indicates the offset of mux register. 62 + - description: | 63 + "conf_reg" indicates the offset of pad configuration register. 64 + - description: | 65 + "input_reg" indicates the offset of select input register. 66 + - description: | 67 + "mux_val" indicates the mux value to be applied. 68 + - description: | 69 + "input_val" indicates the select input value to be applied. 70 + - description: | 71 + "pad_setting" indicates the pad configuration value to be applied. 72 + Common i.MX35 73 + PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) 74 + PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) 75 + PAD_CTL_HYS (1 << 8) 76 + PAD_CTL_PKE (1 << 7) 77 + PAD_CTL_PUE (1 << 6) 78 + PAD_CTL_PUS_100K_DOWN (0 << 4) 79 + PAD_CTL_PUS_47K_UP (1 << 4) 80 + PAD_CTL_PUS_100K_UP (2 << 4) 81 + PAD_CTL_PUS_22K_UP (3 << 4) 82 + PAD_CTL_ODE_CMOS (0 << 3) 83 + PAD_CTL_ODE_OPENDRAIN (1 << 3) 84 + PAD_CTL_DSE_NOMINAL (0 << 1) 85 + PAD_CTL_DSE_HIGH (1 << 1) 86 + PAD_CTL_DSE_MAX (2 << 1) 87 + PAD_CTL_SRE_FAST (1 << 0) 88 + PAD_CTL_SRE_SLOW (0 << 0) 89 + Common i.MX50/i.MX51/i.MX53 bits 90 + PAD_CTL_HVE (1 << 13) 91 + PAD_CTL_HYS (1 << 8) 92 + PAD_CTL_PKE (1 << 7) 93 + PAD_CTL_PUE (1 << 6) 94 + PAD_CTL_PUS_100K_DOWN (0 << 4) 95 + PAD_CTL_PUS_47K_UP (1 << 4) 96 + PAD_CTL_PUS_100K_UP (2 << 4) 97 + PAD_CTL_PUS_22K_UP (3 << 4) 98 + PAD_CTL_ODE (1 << 3) 99 + PAD_CTL_DSE_LOW (0 << 1) 100 + PAD_CTL_DSE_MED (1 << 1) 101 + PAD_CTL_DSE_HIGH (2 << 1) 102 + PAD_CTL_DSE_MAX (3 << 1) 103 + PAD_CTL_SRE_FAST (1 << 0) 104 + PAD_CTL_SRE_SLOW (0 << 0) 105 + Common i.MX6 bits 106 + PAD_CTL_HYS (1 << 16) 107 + PAD_CTL_PUS_100K_DOWN (0 << 14) 108 + PAD_CTL_PUS_47K_UP (1 << 14) 109 + PAD_CTL_PUS_100K_UP (2 << 14) 110 + PAD_CTL_PUS_22K_UP (3 << 14) 111 + PAD_CTL_PUE (1 << 13) 112 + PAD_CTL_PKE (1 << 12) 113 + PAD_CTL_ODE (1 << 11) 114 + PAD_CTL_SPEED_LOW (0 << 6) 115 + PAD_CTL_SPEED_MED (1 << 6) 116 + PAD_CTL_SPEED_HIGH (3 << 6) 117 + PAD_CTL_DSE_DISABLE (0 << 3) 118 + PAD_CTL_SRE_FAST (1 << 0) 119 + PAD_CTL_SRE_SLOW (0 << 0) 120 + i.MX6SL/MX6SLL specific bits 121 + PAD_CTL_LVE (1 << 22) (MX6SL/SLL only) 122 + i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits 123 + PAD_CTL_DSE_260ohm (1 << 3) 124 + PAD_CTL_DSE_130ohm (2 << 3) 125 + PAD_CTL_DSE_87ohm (3 << 3) 126 + PAD_CTL_DSE_65ohm (4 << 3) 127 + PAD_CTL_DSE_52ohm (5 << 3) 128 + PAD_CTL_DSE_43ohm (6 << 3) 129 + PAD_CTL_DSE_37ohm (7 << 3) 130 + i.MX6DL/i.MX6Q/i.MX6SL specific bits 131 + PAD_CTL_DSE_240ohm (1 << 3) 132 + PAD_CTL_DSE_120ohm (2 << 3) 133 + PAD_CTL_DSE_80ohm (3 << 3) 134 + PAD_CTL_DSE_60ohm (4 << 3) 135 + PAD_CTL_DSE_48ohm (5 << 3) 136 + PAD_CTL_DSE_40ohm (6 << 3) 137 + PAD_CTL_DSE_34ohm (7 << 3) 138 + 139 + required: 140 + - fsl,pins 141 + 142 + additionalProperties: false 143 + 144 + required: 145 + - compatible 146 + - reg 147 + 148 + additionalProperties: false 149 + 150 + examples: 151 + - | 152 + iomuxc: pinctrl@20e0000 { 153 + compatible = "fsl,imx6ul-iomuxc"; 154 + reg = <0x020e0000 0x4000>; 155 + 156 + mux_uart: uartgrp { 157 + fsl,pins = < 158 + 0x0084 0x0310 0x0000 0 0 0x1b0b1 159 + 0x0088 0x0314 0x0624 0 3 0x1b0b1 160 + >; 161 + }; 162 + }; 163 + - | 164 + iomuxc_snvs: pinctrl@2290000 { 165 + compatible = "fsl,imx6ull-iomuxc-snvs"; 166 + reg = <0x02290000 0x4000>; 167 + 168 + pinctrl_snvs_usbc_det: snvsusbcdetgrp { 169 + fsl,pins = < 170 + 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 171 + >; 172 + }; 173 + }; 174 + - | 175 + iomuxc_mx6q: pinctrl@20e0000 { 176 + compatible = "fsl,imx6q-iomuxc"; 177 + reg = <0x20e0000 0x4000>; 178 + 179 + pinctrl_uart4: uart4grp { 180 + fsl,pins = 181 + <0x288 0x658 0x000 0x3 0x0 0x140>, 182 + <0x28c 0x65c 0x938 0x3 0x3 0x140>; 183 + }; 184 + };
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Documentation/devicetree/bindings/pinctrl/fsl,imx50-pinctrl.txt
··· 1 - * Freescale IMX50 IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx50-iomuxc" 8 - - fsl,pins: two integers array, represents a group of pins mux and config 9 - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 10 - pin working on a specific function, CONFIG is the pad setting value like 11 - pull-up for this pin. Please refer to imx50 datasheet for the valid pad 12 - config settings. 13 - 14 - CONFIG bits definition: 15 - PAD_CTL_HVE (1 << 13) 16 - PAD_CTL_HYS (1 << 8) 17 - PAD_CTL_PKE (1 << 7) 18 - PAD_CTL_PUE (1 << 6) 19 - PAD_CTL_PUS_100K_DOWN (0 << 4) 20 - PAD_CTL_PUS_47K_UP (1 << 4) 21 - PAD_CTL_PUS_100K_UP (2 << 4) 22 - PAD_CTL_PUS_22K_UP (3 << 4) 23 - PAD_CTL_ODE (1 << 3) 24 - PAD_CTL_DSE_LOW (0 << 1) 25 - PAD_CTL_DSE_MED (1 << 1) 26 - PAD_CTL_DSE_HIGH (2 << 1) 27 - PAD_CTL_DSE_MAX (3 << 1) 28 - PAD_CTL_SRE_FAST (1 << 0) 29 - PAD_CTL_SRE_SLOW (0 << 0) 30 - 31 - Refer to imx50-pinfunc.h in device tree source folder for all available 32 - imx50 PIN_FUNC_ID.
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Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
··· 1 - * Freescale IMX51 IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx51-iomuxc" 8 - - fsl,pins: two integers array, represents a group of pins mux and config 9 - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 10 - pin working on a specific function, CONFIG is the pad setting value like 11 - pull-up for this pin. Please refer to imx51 datasheet for the valid pad 12 - config settings. 13 - 14 - CONFIG bits definition: 15 - PAD_CTL_HVE (1 << 13) 16 - PAD_CTL_HYS (1 << 8) 17 - PAD_CTL_PKE (1 << 7) 18 - PAD_CTL_PUE (1 << 6) 19 - PAD_CTL_PUS_100K_DOWN (0 << 4) 20 - PAD_CTL_PUS_47K_UP (1 << 4) 21 - PAD_CTL_PUS_100K_UP (2 << 4) 22 - PAD_CTL_PUS_22K_UP (3 << 4) 23 - PAD_CTL_ODE (1 << 3) 24 - PAD_CTL_DSE_LOW (0 << 1) 25 - PAD_CTL_DSE_MED (1 << 1) 26 - PAD_CTL_DSE_HIGH (2 << 1) 27 - PAD_CTL_DSE_MAX (3 << 1) 28 - PAD_CTL_SRE_FAST (1 << 0) 29 - PAD_CTL_SRE_SLOW (0 << 0) 30 - 31 - Refer to imx51-pinfunc.h in device tree source folder for all available 32 - imx51 PIN_FUNC_ID.
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Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
··· 1 - * Freescale IMX53 IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx53-iomuxc" 8 - - fsl,pins: two integers array, represents a group of pins mux and config 9 - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 10 - pin working on a specific function, CONFIG is the pad setting value like 11 - pull-up for this pin. Please refer to imx53 datasheet for the valid pad 12 - config settings. 13 - 14 - CONFIG bits definition: 15 - PAD_CTL_HVE (1 << 13) 16 - PAD_CTL_HYS (1 << 8) 17 - PAD_CTL_PKE (1 << 7) 18 - PAD_CTL_PUE (1 << 6) 19 - PAD_CTL_PUS_100K_DOWN (0 << 4) 20 - PAD_CTL_PUS_47K_UP (1 << 4) 21 - PAD_CTL_PUS_100K_UP (2 << 4) 22 - PAD_CTL_PUS_22K_UP (3 << 4) 23 - PAD_CTL_ODE (1 << 3) 24 - PAD_CTL_DSE_LOW (0 << 1) 25 - PAD_CTL_DSE_MED (1 << 1) 26 - PAD_CTL_DSE_HIGH (2 << 1) 27 - PAD_CTL_DSE_MAX (3 << 1) 28 - PAD_CTL_SRE_FAST (1 << 0) 29 - PAD_CTL_SRE_SLOW (0 << 0) 30 - 31 - Refer to imx53-pinfunc.h in device tree source folder for all available 32 - imx53 PIN_FUNC_ID.
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Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt
··· 1 - * Freescale IMX6 DualLite/Solo IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx6dl-iomuxc" 8 - - fsl,pins: two integers array, represents a group of pins mux and config 9 - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 10 - pin working on a specific function, CONFIG is the pad setting value like 11 - pull-up for this pin. Please refer to imx6dl datasheet for the valid pad 12 - config settings. 13 - 14 - CONFIG bits definition: 15 - PAD_CTL_HYS (1 << 16) 16 - PAD_CTL_PUS_100K_DOWN (0 << 14) 17 - PAD_CTL_PUS_47K_UP (1 << 14) 18 - PAD_CTL_PUS_100K_UP (2 << 14) 19 - PAD_CTL_PUS_22K_UP (3 << 14) 20 - PAD_CTL_PUE (1 << 13) 21 - PAD_CTL_PKE (1 << 12) 22 - PAD_CTL_ODE (1 << 11) 23 - PAD_CTL_SPEED_LOW (1 << 6) 24 - PAD_CTL_SPEED_MED (2 << 6) 25 - PAD_CTL_SPEED_HIGH (3 << 6) 26 - PAD_CTL_DSE_DISABLE (0 << 3) 27 - PAD_CTL_DSE_240ohm (1 << 3) 28 - PAD_CTL_DSE_120ohm (2 << 3) 29 - PAD_CTL_DSE_80ohm (3 << 3) 30 - PAD_CTL_DSE_60ohm (4 << 3) 31 - PAD_CTL_DSE_48ohm (5 << 3) 32 - PAD_CTL_DSE_40ohm (6 << 3) 33 - PAD_CTL_DSE_34ohm (7 << 3) 34 - PAD_CTL_SRE_FAST (1 << 0) 35 - PAD_CTL_SRE_SLOW (0 << 0) 36 - 37 - Refer to imx6dl-pinfunc.h in device tree source folder for all available 38 - imx6dl PIN_FUNC_ID.
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Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
··· 1 - * Freescale IMX6Q IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx6q-iomuxc" 8 - - fsl,pins: two integers array, represents a group of pins mux and config 9 - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 10 - pin working on a specific function, CONFIG is the pad setting value like 11 - pull-up for this pin. Please refer to imx6q datasheet for the valid pad 12 - config settings. 13 - 14 - CONFIG bits definition: 15 - PAD_CTL_HYS (1 << 16) 16 - PAD_CTL_PUS_100K_DOWN (0 << 14) 17 - PAD_CTL_PUS_47K_UP (1 << 14) 18 - PAD_CTL_PUS_100K_UP (2 << 14) 19 - PAD_CTL_PUS_22K_UP (3 << 14) 20 - PAD_CTL_PUE (1 << 13) 21 - PAD_CTL_PKE (1 << 12) 22 - PAD_CTL_ODE (1 << 11) 23 - PAD_CTL_SPEED_LOW (1 << 6) 24 - PAD_CTL_SPEED_MED (2 << 6) 25 - PAD_CTL_SPEED_HIGH (3 << 6) 26 - PAD_CTL_DSE_DISABLE (0 << 3) 27 - PAD_CTL_DSE_240ohm (1 << 3) 28 - PAD_CTL_DSE_120ohm (2 << 3) 29 - PAD_CTL_DSE_80ohm (3 << 3) 30 - PAD_CTL_DSE_60ohm (4 << 3) 31 - PAD_CTL_DSE_48ohm (5 << 3) 32 - PAD_CTL_DSE_40ohm (6 << 3) 33 - PAD_CTL_DSE_34ohm (7 << 3) 34 - PAD_CTL_SRE_FAST (1 << 0) 35 - PAD_CTL_SRE_SLOW (0 << 0) 36 - 37 - Refer to imx6q-pinfunc.h in device tree source folder for all available 38 - imx6q PIN_FUNC_ID.
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Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt
··· 1 - * Freescale IMX6 SoloLite IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx6sl-iomuxc" 8 - - fsl,pins: two integers array, represents a group of pins mux and config 9 - setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a 10 - pin working on a specific function, CONFIG is the pad setting value like 11 - pull-up for this pin. Please refer to imx6sl datasheet for the valid pad 12 - config settings. 13 - 14 - CONFIG bits definition: 15 - PAD_CTL_LVE (1 << 22) 16 - PAD_CTL_HYS (1 << 16) 17 - PAD_CTL_PUS_100K_DOWN (0 << 14) 18 - PAD_CTL_PUS_47K_UP (1 << 14) 19 - PAD_CTL_PUS_100K_UP (2 << 14) 20 - PAD_CTL_PUS_22K_UP (3 << 14) 21 - PAD_CTL_PUE (1 << 13) 22 - PAD_CTL_PKE (1 << 12) 23 - PAD_CTL_ODE (1 << 11) 24 - PAD_CTL_SPEED_LOW (1 << 6) 25 - PAD_CTL_SPEED_MED (2 << 6) 26 - PAD_CTL_SPEED_HIGH (3 << 6) 27 - PAD_CTL_DSE_DISABLE (0 << 3) 28 - PAD_CTL_DSE_240ohm (1 << 3) 29 - PAD_CTL_DSE_120ohm (2 << 3) 30 - PAD_CTL_DSE_80ohm (3 << 3) 31 - PAD_CTL_DSE_60ohm (4 << 3) 32 - PAD_CTL_DSE_48ohm (5 << 3) 33 - PAD_CTL_DSE_40ohm (6 << 3) 34 - PAD_CTL_DSE_34ohm (7 << 3) 35 - PAD_CTL_SRE_FAST (1 << 0) 36 - PAD_CTL_SRE_SLOW (0 << 0) 37 - 38 - Refer to imx6sl-pinfunc.h in device tree source folder for all available 39 - imx6sl PIN_FUNC_ID.
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Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
··· 1 - * Freescale i.MX6 SLL IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx6sll-iomuxc" 8 - - fsl,pins: each entry consists of 6 integers and represents the mux and config 9 - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 10 - input_val> are specified using a PIN_FUNC_ID macro, which can be found in 11 - imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is 12 - the pad setting value like pull-up on this pin. Please refer to i.MX6SLL 13 - Reference Manual for detailed CONFIG settings. 14 - 15 - CONFIG bits definition: 16 - PAD_CTL_LVE (1 << 22) 17 - PAD_CTL_HYS (1 << 16) 18 - PAD_CTL_PUS_100K_DOWN (0 << 14) 19 - PAD_CTL_PUS_47K_UP (1 << 14) 20 - PAD_CTL_PUS_100K_UP (2 << 14) 21 - PAD_CTL_PUS_22K_UP (3 << 14) 22 - PAD_CTL_PUE (1 << 13) 23 - PAD_CTL_PKE (1 << 12) 24 - PAD_CTL_ODE (1 << 11) 25 - PAD_CTL_SPEED_LOW (0 << 6) 26 - PAD_CTL_SPEED_MED (1 << 6) 27 - PAD_CTL_SPEED_HIGH (3 << 6) 28 - PAD_CTL_DSE_DISABLE (0 << 3) 29 - PAD_CTL_DSE_260ohm (1 << 3) 30 - PAD_CTL_DSE_130ohm (2 << 3) 31 - PAD_CTL_DSE_87ohm (3 << 3) 32 - PAD_CTL_DSE_65ohm (4 << 3) 33 - PAD_CTL_DSE_52ohm (5 << 3) 34 - PAD_CTL_DSE_43ohm (6 << 3) 35 - PAD_CTL_DSE_37ohm (7 << 3) 36 - PAD_CTL_SRE_FAST (1 << 0) 37 - PAD_CTL_SRE_SLOW (0 << 0) 38 - 39 - Refer to imx6sll-pinfunc.h in device tree source folder for all available 40 - imx6sll PIN_FUNC_ID.
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Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
··· 1 - * Freescale i.MX6 SoloX IOMUX Controller 2 - 3 - Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 4 - and usage. 5 - 6 - Required properties: 7 - - compatible: "fsl,imx6sx-iomuxc" 8 - - fsl,pins: each entry consists of 6 integers and represents the mux and config 9 - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 10 - input_val> are specified using a PIN_FUNC_ID macro, which can be found in 11 - imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is 12 - the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX 13 - Reference Manual for detailed CONFIG settings. 14 - 15 - CONFIG bits definition: 16 - PAD_CTL_HYS (1 << 16) 17 - PAD_CTL_PUS_100K_DOWN (0 << 14) 18 - PAD_CTL_PUS_47K_UP (1 << 14) 19 - PAD_CTL_PUS_100K_UP (2 << 14) 20 - PAD_CTL_PUS_22K_UP (3 << 14) 21 - PAD_CTL_PUE (1 << 13) 22 - PAD_CTL_PKE (1 << 12) 23 - PAD_CTL_ODE (1 << 11) 24 - PAD_CTL_SPEED_LOW (0 << 6) 25 - PAD_CTL_SPEED_MED (1 << 6) 26 - PAD_CTL_SPEED_HIGH (3 << 6) 27 - PAD_CTL_DSE_DISABLE (0 << 3) 28 - PAD_CTL_DSE_260ohm (1 << 3) 29 - PAD_CTL_DSE_130ohm (2 << 3) 30 - PAD_CTL_DSE_87ohm (3 << 3) 31 - PAD_CTL_DSE_65ohm (4 << 3) 32 - PAD_CTL_DSE_52ohm (5 << 3) 33 - PAD_CTL_DSE_43ohm (6 << 3) 34 - PAD_CTL_DSE_37ohm (7 << 3) 35 - PAD_CTL_SRE_FAST (1 << 0) 36 - PAD_CTL_SRE_SLOW (0 << 0)
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Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.yaml
··· 1 - # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 - %YAML 1.2 3 - --- 4 - $id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml# 5 - $schema: http://devicetree.org/meta-schemas/core.yaml# 6 - 7 - title: Freescale IMX6UL IOMUX Controller 8 - 9 - maintainers: 10 - - Dong Aisheng <aisheng.dong@nxp.com> 11 - 12 - description: 13 - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory 14 - for common binding part and usage. 15 - 16 - allOf: 17 - - $ref: pinctrl.yaml# 18 - 19 - properties: 20 - compatible: 21 - enum: 22 - - fsl,imx6ul-iomuxc 23 - - fsl,imx6ull-iomuxc-snvs 24 - 25 - reg: 26 - maxItems: 1 27 - 28 - # Client device subnode's properties 29 - patternProperties: 30 - 'grp$': 31 - type: object 32 - description: 33 - Pinctrl node's client devices use subnodes for desired pin configuration. 34 - Client device subnodes use below standard properties. 35 - 36 - properties: 37 - fsl,pins: 38 - description: 39 - each entry consists of 6 integers and represents the mux and config 40 - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg 41 - mux_val input_val> are specified using a PIN_FUNC_ID macro, which can 42 - be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer 43 - CONFIG is the pad setting value like pull-up on this pin. Please 44 - refer to i.MX6UL Reference Manual for detailed CONFIG settings. 45 - $ref: /schemas/types.yaml#/definitions/uint32-matrix 46 - items: 47 - items: 48 - - description: | 49 - "mux_reg" indicates the offset of mux register. 50 - - description: | 51 - "conf_reg" indicates the offset of pad configuration register. 52 - - description: | 53 - "input_reg" indicates the offset of select input register. 54 - - description: | 55 - "mux_val" indicates the mux value to be applied. 56 - - description: | 57 - "input_val" indicates the select input value to be applied. 58 - - description: | 59 - "pad_setting" indicates the pad configuration value to be applied: 60 - PAD_CTL_HYS (1 << 16) 61 - PAD_CTL_PUS_100K_DOWN (0 << 14) 62 - PAD_CTL_PUS_47K_UP (1 << 14) 63 - PAD_CTL_PUS_100K_UP (2 << 14) 64 - PAD_CTL_PUS_22K_UP (3 << 14) 65 - PAD_CTL_PUE (1 << 13) 66 - PAD_CTL_PKE (1 << 12) 67 - PAD_CTL_ODE (1 << 11) 68 - PAD_CTL_SPEED_LOW (0 << 6) 69 - PAD_CTL_SPEED_MED (1 << 6) 70 - PAD_CTL_SPEED_HIGH (3 << 6) 71 - PAD_CTL_DSE_DISABLE (0 << 3) 72 - PAD_CTL_DSE_260ohm (1 << 3) 73 - PAD_CTL_DSE_130ohm (2 << 3) 74 - PAD_CTL_DSE_87ohm (3 << 3) 75 - PAD_CTL_DSE_65ohm (4 << 3) 76 - PAD_CTL_DSE_52ohm (5 << 3) 77 - PAD_CTL_DSE_43ohm (6 << 3) 78 - PAD_CTL_DSE_37ohm (7 << 3) 79 - PAD_CTL_SRE_FAST (1 << 0) 80 - PAD_CTL_SRE_SLOW (0 << 0) 81 - 82 - required: 83 - - fsl,pins 84 - 85 - additionalProperties: false 86 - 87 - required: 88 - - compatible 89 - - reg 90 - 91 - additionalProperties: false 92 - 93 - examples: 94 - - | 95 - iomuxc: pinctrl@20e0000 { 96 - compatible = "fsl,imx6ul-iomuxc"; 97 - reg = <0x020e0000 0x4000>; 98 - 99 - mux_uart: uartgrp { 100 - fsl,pins = < 101 - 0x0084 0x0310 0x0000 0 0 0x1b0b1 102 - 0x0088 0x0314 0x0624 0 3 0x1b0b1 103 - >; 104 - }; 105 - }; 106 - - | 107 - iomuxc_snvs: pinctrl@2290000 { 108 - compatible = "fsl,imx6ull-iomuxc-snvs"; 109 - reg = <0x02290000 0x4000>; 110 - 111 - pinctrl_snvs_usbc_det: snvsusbcdetgrp { 112 - fsl,pins = < 113 - 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 114 - >; 115 - }; 116 - };