Merge tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt

+2 -1

Documentation/devicetree/bindings/arm/google.yaml

··· 34 34 const: '/' 35 35 compatible: 36 36 oneOf: 37 - - description: Google Pixel 6 / Oriole 37 + - description: Google Pixel 6 or 6 Pro (Oriole or Raven) 38 38 items: 39 39 - enum: 40 40 - google,gs101-oriole 41 + - google,gs101-raven 41 42 - const: google,gs101 42 43 43 44 # Bootloader requires empty ect node to be present

+19

Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml

··· 31 31 compatible: 32 32 enum: 33 33 - samsung,exynos990-cmu-hsi0 34 + - samsung,exynos990-cmu-peris 34 35 - samsung,exynos990-cmu-top 35 36 36 37 clocks: ··· 79 78 - const: usb31drd 80 79 - const: usbdp_debug 81 80 - const: dpgtc 81 + 82 + - if: 83 + properties: 84 + compatible: 85 + contains: 86 + const: samsung,exynos990-cmu-peris 87 + 88 + then: 89 + properties: 90 + clocks: 91 + items: 92 + - description: External reference clock (26 MHz) 93 + - description: CMU_PERIS BUS clock (from CMU_TOP) 94 + 95 + clock-names: 96 + items: 97 + - const: oscclk 98 + - const: bus 82 99 83 100 - if: 84 101 properties:

+66 -33

Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml

··· 11 11 - Krzysztof Kozlowski <krzk@kernel.org> 12 12 13 13 description: | 14 - USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). 15 - USI shares almost all internal circuits within each protocol, so only one 16 - protocol can be chosen at a time. USI is modeled as a node with zero or more 17 - child nodes, each representing a serial sub-node device. The mode setting 18 - selects which particular function will be used. 14 + The USI IP-core provides configurable support for serial protocols, enabling 15 + different serial communication modes depending on the version. 16 + 17 + In USIv1, configurations are available to enable either one or two protocols 18 + simultaneously in select combinations - High-Speed I2C0, High-Speed 19 + I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed 20 + I2C1 and UART. 21 + 22 + In USIv2, only one protocol can be active at a time, either UART, SPI, or 23 + High-Speed I2C. 24 + 25 + The USI core shares internal circuits across protocols, meaning only the 26 + selected configuration is active at any given time. USI is modeled as a node 27 + with zero or more child nodes, each representing a serial sub-node device. The 28 + mode setting selects which particular function will be used. 19 29 20 30 properties: 21 31 $nodename: ··· 41 31 - const: samsung,exynos850-usi 42 32 - enum: 43 33 - samsung,exynos850-usi 34 + - samsung,exynos8895-usi 44 35 45 36 reg: 46 37 maxItems: 1 ··· 75 64 76 65 samsung,mode: 77 66 $ref: /schemas/types.yaml#/definitions/uint32 78 - enum: [0, 1, 2, 3] 67 + enum: [0, 1, 2, 3, 4, 5, 6] 79 68 description: 80 69 Selects USI function (which serial protocol to use). Refer to 81 70 <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values. ··· 112 101 - samsung,sysreg 113 102 - samsung,mode 114 103 115 - if: 116 - properties: 117 - compatible: 118 - contains: 119 - enum: 120 - - samsung,exynos850-usi 104 + allOf: 105 + - if: 106 + properties: 107 + compatible: 108 + contains: 109 + enum: 110 + - samsung,exynos850-usi 121 111 122 - then: 123 - properties: 124 - reg: 125 - maxItems: 1 112 + then: 113 + properties: 114 + reg: 115 + maxItems: 1 126 116 127 - clocks: 128 - items: 129 - - description: Bus (APB) clock 130 - - description: Operating clock for UART/SPI/I2C protocol 117 + clocks: 118 + items: 119 + - description: Bus (APB) clock 120 + - description: Operating clock for UART/SPI/I2C protocol 131 121 132 - clock-names: 133 - maxItems: 2 122 + clock-names: 123 + maxItems: 2 134 124 135 - required: 136 - - reg 137 - - clocks 138 - - clock-names 125 + samsung,mode: 126 + enum: [0, 1, 2, 3] 139 127 140 - else: 141 - properties: 142 - reg: false 143 - clocks: false 144 - clock-names: false 145 - samsung,clkreq-on: false 128 + required: 129 + - reg 130 + - clocks 131 + - clock-names 132 + 133 + - if: 134 + properties: 135 + compatible: 136 + contains: 137 + enum: 138 + - samsung,exynos8895-usi 139 + 140 + then: 141 + properties: 142 + reg: false 143 + 144 + clocks: 145 + items: 146 + - description: Bus (APB) clock 147 + - description: Operating clock for UART/SPI protocol 148 + 149 + clock-names: 150 + maxItems: 2 151 + 152 + samsung,clkreq-on: false 153 + 154 + required: 155 + - clocks 156 + - clock-names 146 157 147 158 additionalProperties: false 148 159 ··· 177 144 compatible = "samsung,exynos850-usi"; 178 145 reg = <0x138200c0 0x20>; 179 146 samsung,sysreg = <&sysreg_peri 0x1010>; 180 - samsung,mode = <USI_V2_UART>; 147 + samsung,mode = <USI_MODE_UART>; 181 148 samsung,clkreq-on; /* needed for UART mode */ 182 149 #address-cells = <1>; 183 150 #size-cells = <1>;

+72

arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts

··· 10 10 #include <dt-bindings/gpio/gpio.h> 11 11 #include <dt-bindings/input/input.h> 12 12 #include <dt-bindings/interrupt-controller/irq.h> 13 + #include <dt-bindings/soc/samsung,exynos-usi.h> 13 14 14 15 / { 15 16 model = "Samsung Galaxy S8 (SM-G950F)"; 16 17 compatible = "samsung,dreamlte", "samsung,exynos8895"; 17 18 chassis-type = "handset"; 19 + 20 + aliases { 21 + mmc0 = &mmc; 22 + }; 18 23 19 24 chosen { 20 25 #address-cells = <2>; ··· 94 89 wakeup-source; 95 90 }; 96 91 }; 92 + 93 + /* TODO: Remove once PMIC is implemented */ 94 + reg_placeholder: regulator-0 { 95 + compatible = "regulator-fixed"; 96 + regulator-name = "reg-placeholder"; 97 + }; 98 + }; 99 + 100 + &hsi2c_23 { 101 + #address-cells = <1>; 102 + #size-cells = <0>; 103 + status = "okay"; 104 + 105 + touchscreen@48 { 106 + compatible = "samsung,s6sy761"; 107 + reg = <0x48>; 108 + 109 + /* TODO: Update once PMIC is implemented */ 110 + avdd-supply = <&reg_placeholder>; 111 + vdd-supply = <&reg_placeholder>; 112 + 113 + interrupt-parent = <&gpa1>; 114 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 115 + 116 + pinctrl-0 = <&ts_int>; 117 + pinctrl-names = "default"; 118 + }; 97 119 }; 98 120 99 121 &oscclk { 100 122 clock-frequency = <26000000>; 123 + }; 124 + 125 + &mmc { 126 + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &sd2_cd>; 127 + pinctrl-names = "default"; 128 + 129 + bus-width = <4>; 130 + card-detect-delay = <200>; 131 + cd-gpios = <&gpa1 5 GPIO_ACTIVE_LOW>; 132 + clock-frequency = <800000000>; 133 + disable-wp; 134 + sd-uhs-sdr50; 135 + sd-uhs-sdr104; 136 + 137 + /* TODO: Add regulators once PMIC is implemented */ 138 + 139 + samsung,dw-mshc-ciu-div = <3>; 140 + samsung,dw-mshc-ddr-timing = <1 2>; 141 + samsung,dw-mshc-sdr-timing = <0 3>; 142 + 143 + status = "okay"; 101 144 }; 102 145 103 146 &pinctrl_alive { ··· 176 123 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 177 124 samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; 178 125 }; 126 + 127 + sd2_cd: sd2-cd-pins { 128 + samsung,pins = "gpa1-5"; 129 + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; 130 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 131 + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; 132 + }; 133 + 134 + ts_int: ts-int-pins { 135 + samsung,pins = "gpa1-0"; 136 + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; 137 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 138 + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; 139 + }; 140 + }; 141 + 142 + &usi9 { 143 + samsung,mode = <USI_MODE_I2C0_1>; 144 + status = "okay"; 179 145 };

+932 -24

arch/arm64/boot/dts/exynos/exynos8895.dtsi

··· 26 26 pinctrl7 = &pinctrl_peric1; 27 27 }; 28 28 29 - arm-a53-pmu { 30 - compatible = "arm,cortex-a53-pmu"; 31 - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 32 - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 33 - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 34 - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 35 - interrupt-affinity = <&cpu0>, 36 - <&cpu1>, 37 - <&cpu2>, 38 - <&cpu3>; 39 - }; 40 - 41 - mongoose-m2-pmu { 42 - compatible = "samsung,mongoose-pmu"; 43 - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 44 - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 45 - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 46 - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 47 - interrupt-affinity = <&cpu4>, 48 - <&cpu5>, 49 - <&cpu6>, 50 - <&cpu7>; 51 - }; 52 - 53 29 cpus { 54 30 #address-cells = <1>; 55 31 #size-cells = <0>; ··· 125 149 clock-output-names = "oscclk"; 126 150 }; 127 151 152 + pmu-a53 { 153 + compatible = "arm,cortex-a53-pmu"; 154 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 155 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 156 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 157 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 158 + interrupt-affinity = <&cpu0>, 159 + <&cpu1>, 160 + <&cpu2>, 161 + <&cpu3>; 162 + }; 163 + 164 + pmu-mongoose-m2 { 165 + compatible = "samsung,mongoose-pmu"; 166 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 167 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 168 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 169 + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 170 + interrupt-affinity = <&cpu4>, 171 + <&cpu5>, 172 + <&cpu6>, 173 + <&cpu7>; 174 + }; 175 + 128 176 psci { 129 177 compatible = "arm,psci"; 130 178 method = "smc"; ··· 228 228 "usi1", "usi2", "usi3"; 229 229 }; 230 230 231 + syscon_peric0: syscon@10420000 { 232 + compatible = "samsung,exynos8895-peric0-sysreg", "syscon"; 233 + reg = <0x10420000 0x2000>; 234 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 235 + }; 236 + 231 237 serial_0: serial@10430000 { 232 238 compatible = "samsung,exynos8895-uart"; 233 239 reg = <0x10430000 0x100>; ··· 245 239 pinctrl-0 = <&uart0_bus>; 246 240 samsung,uart-fifosize = <256>; 247 241 status = "disabled"; 242 + }; 243 + 244 + usi0: usi@10440000 { 245 + compatible = "samsung,exynos8895-usi"; 246 + ranges = <0x0 0x10440000 0x11000>; 247 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, 248 + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; 249 + clock-names = "pclk", "ipclk"; 250 + #address-cells = <1>; 251 + #size-cells = <1>; 252 + samsung,sysreg = <&syscon_peric0 0x1000>; 253 + status = "disabled"; 254 + 255 + hsi2c_5: i2c@0 { 256 + compatible = "samsung,exynos8895-hsi2c"; 257 + reg = <0x0 0x1000>; 258 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>; 259 + clock-names = "hsi2c"; 260 + interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 261 + pinctrl-0 = <&hsi2c5_bus>; 262 + pinctrl-names = "default"; 263 + status = "disabled"; 264 + }; 265 + 266 + serial_2: serial@0 { 267 + compatible = "samsung,exynos8895-uart"; 268 + reg = <0x0 0x100>; 269 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, 270 + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; 271 + clock-names = "uart", "clk_uart_baud0"; 272 + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 273 + pinctrl-0 = <&uart2_bus>; 274 + pinctrl-names = "default"; 275 + samsung,uart-fifosize = <64>; 276 + status = "disabled"; 277 + }; 278 + 279 + spi_2: spi@0 { 280 + compatible = "samsung,exynos8895-spi", 281 + "samsung,exynos850-spi"; 282 + reg = <0x0 0x100>; 283 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, 284 + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; 285 + clock-names = "spi", "spi_busclk0"; 286 + interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 287 + pinctrl-0 = <&spi2_bus>; 288 + pinctrl-names = "default"; 289 + #address-cells = <1>; 290 + #size-cells = <0>; 291 + status = "disabled"; 292 + }; 293 + 294 + hsi2c_6: i2c@10000 { 295 + compatible = "samsung,exynos8895-hsi2c"; 296 + reg = <0x10000 0x1000>; 297 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>; 298 + clock-names = "hsi2c"; 299 + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 300 + pinctrl-0 = <&hsi2c6_bus>; 301 + pinctrl-names = "default"; 302 + status = "disabled"; 303 + }; 304 + }; 305 + 306 + usi1: usi@10460000 { 307 + compatible = "samsung,exynos8895-usi"; 308 + ranges = <0x0 0x10460000 0x11000>; 309 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, 310 + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; 311 + clock-names = "pclk", "ipclk"; 312 + #address-cells = <1>; 313 + #size-cells = <1>; 314 + samsung,sysreg = <&syscon_peric0 0x1004>; 315 + status = "disabled"; 316 + 317 + hsi2c_7: i2c@0 { 318 + compatible = "samsung,exynos8895-hsi2c"; 319 + reg = <0x0 0x1000>; 320 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>; 321 + clock-names = "hsi2c"; 322 + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 323 + pinctrl-0 = <&hsi2c5_bus>; 324 + pinctrl-names = "default"; 325 + status = "disabled"; 326 + }; 327 + 328 + serial_3: serial@0 { 329 + compatible = "samsung,exynos8895-uart"; 330 + reg = <0x0 0x100>; 331 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, 332 + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; 333 + clock-names = "uart", "clk_uart_baud0"; 334 + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 335 + pinctrl-0 = <&uart3_bus>; 336 + pinctrl-names = "default"; 337 + samsung,uart-fifosize = <64>; 338 + status = "disabled"; 339 + }; 340 + 341 + spi_3: spi@0 { 342 + compatible = "samsung,exynos8895-spi", 343 + "samsung,exynos850-spi"; 344 + reg = <0x0 0x100>; 345 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, 346 + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; 347 + clock-names = "spi", "spi_busclk0"; 348 + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 349 + pinctrl-0 = <&spi3_bus>; 350 + pinctrl-names = "default"; 351 + #address-cells = <1>; 352 + #size-cells = <0>; 353 + status = "disabled"; 354 + }; 355 + 356 + hsi2c_8: i2c@10000 { 357 + compatible = "samsung,exynos8895-hsi2c"; 358 + reg = <0x10000 0x1000>; 359 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>; 360 + clock-names = "hsi2c"; 361 + interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 362 + pinctrl-0 = <&hsi2c8_bus>; 363 + pinctrl-names = "default"; 364 + status = "disabled"; 365 + }; 366 + }; 367 + 368 + usi2: usi@10480000 { 369 + compatible = "samsung,exynos8895-usi"; 370 + ranges = <0x0 0x10480000 0x11000>; 371 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, 372 + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; 373 + clock-names = "pclk", "ipclk"; 374 + #address-cells = <1>; 375 + #size-cells = <1>; 376 + samsung,sysreg = <&syscon_peric0 0x1008>; 377 + status = "disabled"; 378 + 379 + hsi2c_9: i2c@0 { 380 + compatible = "samsung,exynos8895-hsi2c"; 381 + reg = <0x0 0x1000>; 382 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>; 383 + clock-names = "hsi2c"; 384 + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 385 + pinctrl-0 = <&hsi2c9_bus>; 386 + pinctrl-names = "default"; 387 + status = "disabled"; 388 + }; 389 + 390 + serial_4: serial@0 { 391 + compatible = "samsung,exynos8895-uart"; 392 + reg = <0x0 0x100>; 393 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, 394 + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; 395 + clock-names = "uart", "clk_uart_baud0"; 396 + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 397 + pinctrl-0 = <&uart4_bus>; 398 + pinctrl-names = "default"; 399 + samsung,uart-fifosize = <64>; 400 + status = "disabled"; 401 + }; 402 + 403 + spi_4: spi@0 { 404 + compatible = "samsung,exynos8895-spi", 405 + "samsung,exynos850-spi"; 406 + reg = <0x0 0x100>; 407 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, 408 + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; 409 + clock-names = "spi", "spi_busclk0"; 410 + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 411 + pinctrl-0 = <&spi4_bus>; 412 + pinctrl-names = "default"; 413 + #address-cells = <1>; 414 + #size-cells = <0>; 415 + status = "disabled"; 416 + }; 417 + 418 + hsi2c_10: i2c@10000 { 419 + compatible = "samsung,exynos8895-hsi2c"; 420 + reg = <0x10000 0x1000>; 421 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>; 422 + clock-names = "hsi2c"; 423 + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 424 + pinctrl-0 = <&hsi2c10_bus>; 425 + pinctrl-names = "default"; 426 + status = "disabled"; 427 + }; 428 + }; 429 + 430 + usi3: usi@104a0000 { 431 + compatible = "samsung,exynos8895-usi"; 432 + ranges = <0x0 0x104a0000 0x11000>; 433 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, 434 + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; 435 + clock-names = "pclk", "ipclk"; 436 + #address-cells = <1>; 437 + #size-cells = <1>; 438 + samsung,sysreg = <&syscon_peric0 0x100c>; 439 + status = "disabled"; 440 + 441 + hsi2c_11: i2c@0 { 442 + compatible = "samsung,exynos8895-hsi2c"; 443 + reg = <0x0 0x1000>; 444 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>; 445 + clock-names = "hsi2c"; 446 + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 447 + pinctrl-0 = <&hsi2c11_bus>; 448 + pinctrl-names = "default"; 449 + status = "disabled"; 450 + }; 451 + 452 + serial_5: serial@0 { 453 + compatible = "samsung,exynos8895-uart"; 454 + reg = <0x0 0x100>; 455 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, 456 + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; 457 + clock-names = "uart", "clk_uart_baud0"; 458 + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 459 + pinctrl-0 = <&uart5_bus>; 460 + pinctrl-names = "default"; 461 + samsung,uart-fifosize = <64>; 462 + status = "disabled"; 463 + }; 464 + 465 + spi_5: spi@0 { 466 + compatible = "samsung,exynos8895-spi", 467 + "samsung,exynos850-spi"; 468 + reg = <0x0 0x100>; 469 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, 470 + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; 471 + clock-names = "spi", "spi_busclk0"; 472 + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 473 + pinctrl-0 = <&spi5_bus>; 474 + pinctrl-names = "default"; 475 + #address-cells = <1>; 476 + #size-cells = <0>; 477 + status = "disabled"; 478 + }; 479 + 480 + hsi2c_12: i2c@10000 { 481 + compatible = "samsung,exynos8895-hsi2c"; 482 + reg = <0x10000 0x1000>; 483 + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>; 484 + clock-names = "hsi2c"; 485 + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 486 + pinctrl-0 = <&hsi2c12_bus>; 487 + pinctrl-names = "default"; 488 + status = "disabled"; 489 + }; 248 490 }; 249 491 250 492 pinctrl_peric0: pinctrl@104d0000 { ··· 527 273 "usi10", "usi11", "usi12", "usi13"; 528 274 }; 529 275 276 + syscon_peric1: syscon@10820000 { 277 + compatible = "samsung,exynos8895-peric1-sysreg", "syscon"; 278 + reg = <0x10820000 0x2000>; 279 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 280 + }; 281 + 530 282 serial_1: serial@10830000 { 531 283 compatible = "samsung,exynos8895-uart"; 532 284 reg = <0x10830000 0x100>; ··· 544 284 pinctrl-0 = <&uart1_bus>; 545 285 samsung,uart-fifosize = <256>; 546 286 status = "disabled"; 287 + }; 288 + 289 + usi4: usi@10840000 { 290 + compatible = "samsung,exynos8895-usi"; 291 + ranges = <0x0 0x10840000 0x11000>; 292 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, 293 + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; 294 + clock-names = "pclk", "ipclk"; 295 + #address-cells = <1>; 296 + #size-cells = <1>; 297 + samsung,sysreg = <&syscon_peric1 0x1008>; 298 + status = "disabled"; 299 + 300 + hsi2c_13: i2c@0 { 301 + compatible = "samsung,exynos8895-hsi2c"; 302 + reg = <0x0 0x1000>; 303 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>; 304 + clock-names = "hsi2c"; 305 + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; 306 + pinctrl-0 = <&hsi2c13_bus>; 307 + pinctrl-names = "default"; 308 + status = "disabled"; 309 + }; 310 + 311 + serial_6: serial@0 { 312 + compatible = "samsung,exynos8895-uart"; 313 + reg = <0x0 0x100>; 314 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, 315 + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; 316 + clock-names = "uart", "clk_uart_baud0"; 317 + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 318 + pinctrl-0 = <&uart6_bus>; 319 + pinctrl-names = "default"; 320 + samsung,uart-fifosize = <64>; 321 + status = "disabled"; 322 + }; 323 + 324 + spi_6: spi@0 { 325 + compatible = "samsung,exynos8895-spi", 326 + "samsung,exynos850-spi"; 327 + reg = <0x0 0x100>; 328 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, 329 + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; 330 + clock-names = "spi", "spi_busclk0"; 331 + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 332 + pinctrl-0 = <&spi6_bus>; 333 + pinctrl-names = "default"; 334 + #address-cells = <1>; 335 + #size-cells = <0>; 336 + status = "disabled"; 337 + }; 338 + 339 + hsi2c_14: i2c@10000 { 340 + compatible = "samsung,exynos8895-hsi2c"; 341 + reg = <0x10000 0x1000>; 342 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>; 343 + clock-names = "hsi2c"; 344 + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 345 + pinctrl-0 = <&hsi2c14_bus>; 346 + pinctrl-names = "default"; 347 + status = "disabled"; 348 + }; 349 + }; 350 + 351 + usi5: usi@10860000 { 352 + compatible = "samsung,exynos8895-usi"; 353 + ranges = <0x0 0x10860000 0x11000>; 354 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, 355 + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; 356 + clock-names = "pclk", "ipclk"; 357 + #address-cells = <1>; 358 + #size-cells = <1>; 359 + samsung,sysreg = <&syscon_peric1 0x100c>; 360 + status = "disabled"; 361 + 362 + hsi2c_15: i2c@0 { 363 + compatible = "samsung,exynos8895-hsi2c"; 364 + reg = <0x0 0x1000>; 365 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>; 366 + clock-names = "hsi2c"; 367 + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 368 + pinctrl-0 = <&hsi2c15_bus>; 369 + pinctrl-names = "default"; 370 + status = "disabled"; 371 + }; 372 + 373 + serial_7: serial@0 { 374 + compatible = "samsung,exynos8895-uart"; 375 + reg = <0x0 0x100>; 376 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, 377 + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; 378 + clock-names = "uart", "clk_uart_baud0"; 379 + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 380 + pinctrl-0 = <&uart7_bus>; 381 + pinctrl-names = "default"; 382 + samsung,uart-fifosize = <64>; 383 + status = "disabled"; 384 + }; 385 + 386 + spi_7: spi@0 { 387 + compatible = "samsung,exynos8895-spi", 388 + "samsung,exynos850-spi"; 389 + reg = <0x0 0x100>; 390 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, 391 + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; 392 + clock-names = "spi", "spi_busclk0"; 393 + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 394 + pinctrl-0 = <&spi7_bus>; 395 + pinctrl-names = "default"; 396 + #address-cells = <1>; 397 + #size-cells = <0>; 398 + status = "disabled"; 399 + }; 400 + 401 + hsi2c_16: i2c@10000 { 402 + compatible = "samsung,exynos8895-hsi2c"; 403 + reg = <0x10000 0x1000>; 404 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>; 405 + clock-names = "hsi2c"; 406 + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 407 + pinctrl-0 = <&hsi2c16_bus>; 408 + pinctrl-names = "default"; 409 + status = "disabled"; 410 + }; 411 + }; 412 + 413 + usi6: usi@10880000 { 414 + compatible = "samsung,exynos8895-usi"; 415 + ranges = <0x0 0x10880000 0x11000>; 416 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, 417 + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; 418 + clock-names = "pclk", "ipclk"; 419 + #address-cells = <1>; 420 + #size-cells = <1>; 421 + samsung,sysreg = <&syscon_peric1 0x1010>; 422 + status = "disabled"; 423 + 424 + hsi2c_17: i2c@0 { 425 + compatible = "samsung,exynos8895-hsi2c"; 426 + reg = <0x0 0x1000>; 427 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>; 428 + clock-names = "hsi2c"; 429 + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 430 + pinctrl-0 = <&hsi2c17_bus>; 431 + pinctrl-names = "default"; 432 + status = "disabled"; 433 + }; 434 + 435 + serial_8: serial@0 { 436 + compatible = "samsung,exynos8895-uart"; 437 + reg = <0x0 0x100>; 438 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, 439 + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; 440 + clock-names = "uart", "clk_uart_baud0"; 441 + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 442 + pinctrl-0 = <&uart8_bus>; 443 + pinctrl-names = "default"; 444 + samsung,uart-fifosize = <64>; 445 + status = "disabled"; 446 + }; 447 + 448 + spi_8: spi@0 { 449 + compatible = "samsung,exynos8895-spi", 450 + "samsung,exynos850-spi"; 451 + reg = <0x0 0x100>; 452 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, 453 + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; 454 + clock-names = "spi", "spi_busclk0"; 455 + interrupts = <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>; 456 + pinctrl-0 = <&spi8_bus>; 457 + pinctrl-names = "default"; 458 + #address-cells = <1>; 459 + #size-cells = <0>; 460 + status = "disabled"; 461 + }; 462 + 463 + hsi2c_18: i2c@10000 { 464 + compatible = "samsung,exynos8895-hsi2c"; 465 + reg = <0x10000 0x1000>; 466 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>; 467 + clock-names = "hsi2c"; 468 + interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 469 + pinctrl-0 = <&hsi2c18_bus>; 470 + pinctrl-names = "default"; 471 + status = "disabled"; 472 + }; 473 + }; 474 + 475 + usi7: usi@108a0000 { 476 + compatible = "samsung,exynos8895-usi"; 477 + ranges = <0x0 0x108a0000 0x11000>; 478 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, 479 + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; 480 + clock-names = "pclk", "ipclk"; 481 + #address-cells = <1>; 482 + #size-cells = <1>; 483 + samsung,sysreg = <&syscon_peric1 0x1014>; 484 + status = "disabled"; 485 + 486 + hsi2c_19: i2c@0 { 487 + compatible = "samsung,exynos8895-hsi2c"; 488 + reg = <0x0 0x1000>; 489 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>; 490 + clock-names = "hsi2c"; 491 + interrupts = <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>; 492 + pinctrl-0 = <&hsi2c19_bus>; 493 + pinctrl-names = "default"; 494 + status = "disabled"; 495 + }; 496 + 497 + serial_9: serial@0 { 498 + compatible = "samsung,exynos8895-uart"; 499 + reg = <0x0 0x100>; 500 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, 501 + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; 502 + clock-names = "uart", "clk_uart_baud0"; 503 + interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 504 + pinctrl-0 = <&uart9_bus>; 505 + pinctrl-names = "default"; 506 + samsung,uart-fifosize = <64>; 507 + status = "disabled"; 508 + }; 509 + 510 + spi_9: spi@0 { 511 + compatible = "samsung,exynos8895-spi", 512 + "samsung,exynos850-spi"; 513 + reg = <0x0 0x100>; 514 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, 515 + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; 516 + clock-names = "spi", "spi_busclk0"; 517 + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 518 + pinctrl-0 = <&spi9_bus>; 519 + pinctrl-names = "default"; 520 + #address-cells = <1>; 521 + #size-cells = <0>; 522 + status = "disabled"; 523 + }; 524 + 525 + hsi2c_20: i2c@10000 { 526 + compatible = "samsung,exynos8895-hsi2c"; 527 + reg = <0x10000 0x1000>; 528 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>; 529 + clock-names = "hsi2c"; 530 + interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 531 + pinctrl-0 = <&hsi2c20_bus>; 532 + pinctrl-names = "default"; 533 + status = "disabled"; 534 + }; 535 + }; 536 + 537 + usi8: usi@108c0000 { 538 + compatible = "samsung,exynos8895-usi"; 539 + ranges = <0x0 0x108c0000 0x11000>; 540 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, 541 + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; 542 + clock-names = "pclk", "ipclk"; 543 + #address-cells = <1>; 544 + #size-cells = <1>; 545 + samsung,sysreg = <&syscon_peric1 0x1018>; 546 + status = "disabled"; 547 + 548 + hsi2c_21: i2c@0 { 549 + compatible = "samsung,exynos8895-hsi2c"; 550 + reg = <0x0 0x1000>; 551 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>; 552 + clock-names = "hsi2c"; 553 + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; 554 + pinctrl-0 = <&hsi2c21_bus>; 555 + pinctrl-names = "default"; 556 + status = "disabled"; 557 + }; 558 + 559 + serial_10: serial@0 { 560 + compatible = "samsung,exynos8895-uart"; 561 + reg = <0x0 0x100>; 562 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, 563 + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; 564 + clock-names = "uart", "clk_uart_baud0"; 565 + interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 566 + pinctrl-0 = <&uart10_bus>; 567 + pinctrl-names = "default"; 568 + samsung,uart-fifosize = <64>; 569 + status = "disabled"; 570 + }; 571 + 572 + spi_10: spi@0 { 573 + compatible = "samsung,exynos8895-spi", 574 + "samsung,exynos850-spi"; 575 + reg = <0x0 0x100>; 576 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, 577 + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; 578 + clock-names = "spi", "spi_busclk0"; 579 + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 580 + pinctrl-0 = <&spi10_bus>; 581 + pinctrl-names = "default"; 582 + #address-cells = <1>; 583 + #size-cells = <0>; 584 + status = "disabled"; 585 + }; 586 + 587 + hsi2c_22: i2c@10000 { 588 + compatible = "samsung,exynos8895-hsi2c"; 589 + reg = <0x10000 0x1000>; 590 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>; 591 + clock-names = "hsi2c"; 592 + interrupts = <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>; 593 + pinctrl-0 = <&hsi2c22_bus>; 594 + pinctrl-names = "default"; 595 + status = "disabled"; 596 + }; 597 + }; 598 + 599 + usi9: usi@108e0000 { 600 + compatible = "samsung,exynos8895-usi"; 601 + ranges = <0x0 0x108e0000 0x11000>; 602 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, 603 + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; 604 + clock-names = "pclk", "ipclk"; 605 + #address-cells = <1>; 606 + #size-cells = <1>; 607 + samsung,sysreg = <&syscon_peric1 0x101c>; 608 + status = "disabled"; 609 + 610 + hsi2c_23: i2c@0 { 611 + compatible = "samsung,exynos8895-hsi2c"; 612 + reg = <0x0 0x1000>; 613 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>; 614 + clock-names = "hsi2c"; 615 + interrupts = <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>; 616 + pinctrl-0 = <&hsi2c23_bus>; 617 + pinctrl-names = "default"; 618 + status = "disabled"; 619 + }; 620 + 621 + serial_11: serial@0 { 622 + compatible = "samsung,exynos8895-uart"; 623 + reg = <0 0x100>; 624 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, 625 + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; 626 + clock-names = "uart", "clk_uart_baud0"; 627 + interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 628 + pinctrl-0 = <&uart11_bus>; 629 + pinctrl-names = "default"; 630 + samsung,uart-fifosize = <64>; 631 + status = "disabled"; 632 + }; 633 + 634 + spi_11: spi@0 { 635 + compatible = "samsung,exynos8895-spi", 636 + "samsung,exynos850-spi"; 637 + reg = <0 0x100>; 638 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, 639 + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; 640 + clock-names = "spi", "spi_busclk0"; 641 + interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 642 + pinctrl-0 = <&spi11_bus>; 643 + pinctrl-names = "default"; 644 + #address-cells = <1>; 645 + #size-cells = <0>; 646 + status = "disabled"; 647 + }; 648 + 649 + hsi2c_24: i2c@10000 { 650 + compatible = "samsung,exynos8895-hsi2c"; 651 + reg = <0x10000 0x1000>; 652 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>; 653 + clock-names = "hsi2c"; 654 + interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; 655 + pinctrl-0 = <&hsi2c24_bus>; 656 + pinctrl-names = "default"; 657 + status = "disabled"; 658 + }; 659 + }; 660 + 661 + usi10: usi@10900000 { 662 + compatible = "samsung,exynos8895-usi"; 663 + ranges = <0x0 0x10900000 0x11000>; 664 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, 665 + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; 666 + clock-names = "pclk", "ipclk"; 667 + #address-cells = <1>; 668 + #size-cells = <1>; 669 + samsung,sysreg = <&syscon_peric1 0x1020>; 670 + status = "disabled"; 671 + 672 + hsi2c_25: i2c@0 { 673 + compatible = "samsung,exynos8895-hsi2c"; 674 + reg = <0x0 0x1000>; 675 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>; 676 + clock-names = "hsi2c"; 677 + interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 678 + pinctrl-0 = <&hsi2c25_bus>; 679 + pinctrl-names = "default"; 680 + status = "disabled"; 681 + }; 682 + 683 + serial_12: serial@0 { 684 + compatible = "samsung,exynos8895-uart"; 685 + reg = <0 0x100>; 686 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, 687 + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; 688 + clock-names = "uart", "clk_uart_baud0"; 689 + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; 690 + pinctrl-0 = <&uart12_bus>; 691 + pinctrl-names = "default"; 692 + samsung,uart-fifosize = <64>; 693 + status = "disabled"; 694 + }; 695 + 696 + spi_12: spi@0 { 697 + compatible = "samsung,exynos8895-spi", 698 + "samsung,exynos850-spi"; 699 + reg = <0 0x100>; 700 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, 701 + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; 702 + clock-names = "spi", "spi_busclk0"; 703 + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 704 + pinctrl-0 = <&spi12_bus>; 705 + pinctrl-names = "default"; 706 + #address-cells = <1>; 707 + #size-cells = <0>; 708 + status = "disabled"; 709 + }; 710 + 711 + hsi2c_26: i2c@10000 { 712 + compatible = "samsung,exynos8895-hsi2c"; 713 + reg = <0x10000 0x1000>; 714 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>; 715 + clock-names = "hsi2c"; 716 + interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>; 717 + pinctrl-0 = <&hsi2c26_bus>; 718 + pinctrl-names = "default"; 719 + status = "disabled"; 720 + }; 721 + }; 722 + 723 + usi11: usi@10920000 { 724 + compatible = "samsung,exynos8895-usi"; 725 + ranges = <0x0 0x10920000 0x11000>; 726 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, 727 + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; 728 + clock-names = "pclk", "ipclk"; 729 + #address-cells = <1>; 730 + #size-cells = <1>; 731 + samsung,sysreg = <&syscon_peric1 0x1024>; 732 + status = "disabled"; 733 + 734 + hsi2c_27: i2c@0 { 735 + compatible = "samsung,exynos8895-hsi2c"; 736 + reg = <0x0 0x1000>; 737 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>; 738 + clock-names = "hsi2c"; 739 + interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>; 740 + pinctrl-0 = <&hsi2c27_bus>; 741 + pinctrl-names = "default"; 742 + status = "disabled"; 743 + }; 744 + 745 + serial_13: serial@0 { 746 + compatible = "samsung,exynos8895-uart"; 747 + reg = <0 0x100>; 748 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, 749 + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; 750 + clock-names = "uart", "clk_uart_baud0"; 751 + interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 752 + pinctrl-0 = <&uart13_bus>; 753 + pinctrl-names = "default"; 754 + samsung,uart-fifosize = <64>; 755 + status = "disabled"; 756 + }; 757 + 758 + spi_13: spi@0 { 759 + compatible = "samsung,exynos8895-spi", 760 + "samsung,exynos850-spi"; 761 + reg = <0 0x100>; 762 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, 763 + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; 764 + clock-names = "spi", "spi_busclk0"; 765 + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 766 + pinctrl-0 = <&spi13_bus>; 767 + pinctrl-names = "default"; 768 + #address-cells = <1>; 769 + #size-cells = <0>; 770 + status = "disabled"; 771 + }; 772 + 773 + hsi2c_28: i2c@10000 { 774 + compatible = "samsung,exynos8895-hsi2c"; 775 + reg = <0x10000 0x1000>; 776 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>; 777 + clock-names = "hsi2c"; 778 + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; 779 + pinctrl-0 = <&hsi2c28_bus>; 780 + pinctrl-names = "default"; 781 + status = "disabled"; 782 + }; 783 + }; 784 + 785 + usi12: usi@10940000 { 786 + compatible = "samsung,exynos8895-usi"; 787 + ranges = <0x0 0x10940000 0x11000>; 788 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, 789 + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; 790 + clock-names = "pclk", "ipclk"; 791 + #address-cells = <1>; 792 + #size-cells = <1>; 793 + samsung,sysreg = <&syscon_peric1 0x1028>; 794 + status = "disabled"; 795 + 796 + hsi2c_29: i2c@0 { 797 + compatible = "samsung,exynos8895-hsi2c"; 798 + reg = <0x0 0x1000>; 799 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>; 800 + clock-names = "hsi2c"; 801 + interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 802 + pinctrl-0 = <&hsi2c29_bus>; 803 + pinctrl-names = "default"; 804 + status = "disabled"; 805 + }; 806 + 807 + serial_14: serial@0 { 808 + compatible = "samsung,exynos8895-uart"; 809 + reg = <0 0x100>; 810 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, 811 + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; 812 + clock-names = "uart", "clk_uart_baud0"; 813 + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 814 + pinctrl-0 = <&uart14_bus>; 815 + pinctrl-names = "default"; 816 + samsung,uart-fifosize = <64>; 817 + status = "disabled"; 818 + }; 819 + 820 + spi_14: spi@0 { 821 + compatible = "samsung,exynos8895-spi", 822 + "samsung,exynos850-spi"; 823 + reg = <0 0x100>; 824 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, 825 + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; 826 + clock-names = "spi", "spi_busclk0"; 827 + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 828 + pinctrl-0 = <&spi14_bus>; 829 + pinctrl-names = "default"; 830 + #address-cells = <1>; 831 + #size-cells = <0>; 832 + status = "disabled"; 833 + }; 834 + 835 + hsi2c_30: i2c@10000 { 836 + compatible = "samsung,exynos8895-hsi2c"; 837 + reg = <0x10000 0x1000>; 838 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>; 839 + clock-names = "hsi2c"; 840 + interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 841 + pinctrl-0 = <&hsi2c30_bus>; 842 + pinctrl-names = "default"; 843 + status = "disabled"; 844 + }; 845 + }; 846 + 847 + usi13: usi@10960000 { 848 + compatible = "samsung,exynos8895-usi"; 849 + ranges = <0x0 0x10960000 0x11000>; 850 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, 851 + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; 852 + clock-names = "pclk", "ipclk"; 853 + #address-cells = <1>; 854 + #size-cells = <1>; 855 + samsung,sysreg = <&syscon_peric1 0x102c>; 856 + status = "disabled"; 857 + 858 + hsi2c_31: i2c@0 { 859 + compatible = "samsung,exynos8895-hsi2c"; 860 + reg = <0x0 0x1000>; 861 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>; 862 + clock-names = "hsi2c"; 863 + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>; 864 + pinctrl-0 = <&hsi2c31_bus>; 865 + pinctrl-names = "default"; 866 + status = "disabled"; 867 + }; 868 + 869 + serial_15: serial@0 { 870 + compatible = "samsung,exynos8895-uart"; 871 + reg = <0 0x100>; 872 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, 873 + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; 874 + clock-names = "uart", "clk_uart_baud0"; 875 + interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>; 876 + pinctrl-0 = <&uart15_bus>; 877 + pinctrl-names = "default"; 878 + samsung,uart-fifosize = <64>; 879 + status = "disabled"; 880 + }; 881 + 882 + spi_15: spi@0 { 883 + compatible = "samsung,exynos8895-spi", 884 + "samsung,exynos850-spi"; 885 + reg = <0 0x100>; 886 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, 887 + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; 888 + clock-names = "spi", "spi_busclk0"; 889 + interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 890 + pinctrl-0 = <&spi15_bus>; 891 + pinctrl-names = "default"; 892 + #address-cells = <1>; 893 + #size-cells = <0>; 894 + status = "disabled"; 895 + }; 896 + 897 + hsi2c_32: i2c@10000 { 898 + compatible = "samsung,exynos8895-hsi2c"; 899 + reg = <0x10000 0x1000>; 900 + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>; 901 + clock-names = "hsi2c"; 902 + interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>; 903 + pinctrl-0 = <&hsi2c32_bus>; 904 + pinctrl-names = "default"; 905 + status = "disabled"; 906 + }; 547 907 }; 548 908 549 909 pinctrl_peric1: pinctrl@10980000 { ··· 1260 380 "ufs", "usbdrd30"; 1261 381 }; 1262 382 383 + syscon_fsys0: syscon@11020000 { 384 + compatible = "samsung,exynos8895-fsys0-sysreg", "syscon"; 385 + reg = <0x11020000 0x2000>; 386 + clocks = <&cmu_fsys0 CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK>; 387 + }; 388 + 1263 389 pinctrl_fsys0: pinctrl@11050000 { 1264 390 compatible = "samsung,exynos8895-pinctrl"; 1265 391 reg = <0x11050000 0x1000>; ··· 1284 398 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; 1285 399 }; 1286 400 401 + syscon_fsys1: syscon@11420000 { 402 + compatible = "samsung,exynos8895-fsys1-sysreg", "syscon"; 403 + reg = <0x11420000 0x2000>; 404 + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK>; 405 + }; 406 + 1287 407 pinctrl_fsys1: pinctrl@11430000 { 1288 408 compatible = "samsung,exynos8895-pinctrl"; 1289 409 reg = <0x11430000 0x1000>; 1290 410 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 411 + }; 412 + 413 + mmc: mmc@11500000 { 414 + compatible = "samsung,exynos8895-dw-mshc-smu", 415 + "samsung,exynos7-dw-mshc-smu"; 416 + reg = <0x11500000 0x2000>; 417 + assigned-clocks = <&cmu_top CLK_MOUT_CMU_FSYS1_MMC_CARD>; 418 + assigned-clock-parents = <&cmu_top CLK_FOUT_SHARED4_PLL>; 419 + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_I_ACLK>, 420 + <&cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN>; 421 + clock-names = "biu", "ciu"; 422 + fifo-depth = <64>; 423 + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 424 + #address-cells = <1>; 425 + #size-cells = <0>; 426 + status = "disabled"; 1291 427 }; 1292 428 1293 429 pinctrl_abox: pinctrl@13e60000 {

+61 -31

arch/arm64/boot/dts/exynos/exynos990.dtsi

··· 25 25 pinctrl6 = &pinctrl_vts; 26 26 }; 27 27 28 - arm-a55-pmu { 29 - compatible = "arm,cortex-a55-pmu"; 30 - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 31 - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 32 - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 33 - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 34 - 35 - interrupt-affinity = <&cpu0>, 36 - <&cpu1>, 37 - <&cpu2>, 38 - <&cpu3>; 39 - }; 40 - 41 - arm-a76-pmu { 42 - compatible = "arm,cortex-a76-pmu"; 43 - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 44 - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 45 - 46 - interrupt-affinity = <&cpu4>, 47 - <&cpu5>; 48 - }; 49 - 50 - mongoose-m5-pmu { 51 - compatible = "samsung,mongoose-pmu"; 52 - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 53 - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 54 - 55 - interrupt-affinity = <&cpu6>, 56 - <&cpu7>; 57 - }; 58 - 59 28 cpus { 60 29 #address-cells = <1>; 61 30 #size-cells = <0>; ··· 132 163 clock-output-names = "oscclk"; 133 164 }; 134 165 166 + pmu-a55 { 167 + compatible = "arm,cortex-a55-pmu"; 168 + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 169 + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 170 + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 171 + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 172 + 173 + interrupt-affinity = <&cpu0>, 174 + <&cpu1>, 175 + <&cpu2>, 176 + <&cpu3>; 177 + }; 178 + 179 + pmu-a76 { 180 + compatible = "arm,cortex-a76-pmu"; 181 + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 182 + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 183 + 184 + interrupt-affinity = <&cpu4>, 185 + <&cpu5>; 186 + }; 187 + 188 + pmu-mongoose-m5 { 189 + compatible = "samsung,mongoose-pmu"; 190 + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 191 + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 192 + 193 + interrupt-affinity = <&cpu6>, 194 + <&cpu7>; 195 + }; 196 + 135 197 psci { 136 198 compatible = "arm,psci-0.2"; 137 199 method = "hvc"; ··· 179 179 compatible = "samsung,exynos990-chipid", 180 180 "samsung,exynos850-chipid"; 181 181 reg = <0x10000000 0x100>; 182 + }; 183 + 184 + cmu_peris: clock-controller@10020000 { 185 + compatible = "samsung,exynos990-cmu-peris"; 186 + reg = <0x10020000 0x8000>; 187 + #clock-cells = <1>; 188 + 189 + clocks = <&oscclk>, 190 + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; 191 + clock-names = "oscclk", "bus"; 192 + }; 193 + 194 + timer@10040000 { 195 + compatible = "samsung,exynos990-mct", 196 + "samsung,exynos4210-mct"; 197 + reg = <0x10040000 0x800>; 198 + clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; 199 + clock-names = "fin_pll", "mct"; 200 + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 201 + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 202 + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 203 + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 204 + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 205 + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 206 + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 207 + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 208 + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 209 + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 210 + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 211 + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 182 212 }; 183 213 184 214 gic: interrupt-controller@10101000 {

+138

arch/arm64/boot/dts/exynos/exynosautov920.dtsi

··· 89 89 compatible = "arm,cortex-a78ae"; 90 90 reg = <0x0 0x0>; 91 91 enable-method = "psci"; 92 + i-cache-size = <0x10000>; 93 + i-cache-line-size = <64>; 94 + i-cache-sets = <256>; 95 + d-cache-size = <0x10000>; 96 + d-cache-line-size = <64>; 97 + d-cache-sets = <256>; 98 + next-level-cache = <&l2_cache_cl0>; 92 99 }; 93 100 94 101 cpu1: cpu@100 { ··· 103 96 compatible = "arm,cortex-a78ae"; 104 97 reg = <0x0 0x100>; 105 98 enable-method = "psci"; 99 + i-cache-size = <0x10000>; 100 + i-cache-line-size = <64>; 101 + i-cache-sets = <256>; 102 + d-cache-size = <0x10000>; 103 + d-cache-line-size = <64>; 104 + d-cache-sets = <256>; 105 + next-level-cache = <&l2_cache_cl0>; 106 106 }; 107 107 108 108 cpu2: cpu@200 { ··· 117 103 compatible = "arm,cortex-a78ae"; 118 104 reg = <0x0 0x200>; 119 105 enable-method = "psci"; 106 + i-cache-size = <0x10000>; 107 + i-cache-line-size = <64>; 108 + i-cache-sets = <256>; 109 + d-cache-size = <0x10000>; 110 + d-cache-line-size = <64>; 111 + d-cache-sets = <256>; 112 + next-level-cache = <&l2_cache_cl0>; 120 113 }; 121 114 122 115 cpu3: cpu@300 { ··· 131 110 compatible = "arm,cortex-a78ae"; 132 111 reg = <0x0 0x300>; 133 112 enable-method = "psci"; 113 + i-cache-size = <0x10000>; 114 + i-cache-line-size = <64>; 115 + i-cache-sets = <256>; 116 + d-cache-size = <0x10000>; 117 + d-cache-line-size = <64>; 118 + d-cache-sets = <256>; 119 + next-level-cache = <&l2_cache_cl0>; 134 120 }; 135 121 136 122 cpu4: cpu@10000 { ··· 145 117 compatible = "arm,cortex-a78ae"; 146 118 reg = <0x0 0x10000>; 147 119 enable-method = "psci"; 120 + i-cache-size = <0x10000>; 121 + i-cache-line-size = <64>; 122 + i-cache-sets = <256>; 123 + d-cache-size = <0x10000>; 124 + d-cache-line-size = <64>; 125 + d-cache-sets = <256>; 126 + next-level-cache = <&l2_cache_cl1>; 148 127 }; 149 128 150 129 cpu5: cpu@10100 { ··· 159 124 compatible = "arm,cortex-a78ae"; 160 125 reg = <0x0 0x10100>; 161 126 enable-method = "psci"; 127 + i-cache-size = <0x10000>; 128 + i-cache-line-size = <64>; 129 + i-cache-sets = <256>; 130 + d-cache-size = <0x10000>; 131 + d-cache-line-size = <64>; 132 + d-cache-sets = <256>; 133 + next-level-cache = <&l2_cache_cl1>; 162 134 }; 163 135 164 136 cpu6: cpu@10200 { ··· 173 131 compatible = "arm,cortex-a78ae"; 174 132 reg = <0x0 0x10200>; 175 133 enable-method = "psci"; 134 + i-cache-size = <0x10000>; 135 + i-cache-line-size = <64>; 136 + i-cache-sets = <256>; 137 + d-cache-size = <0x10000>; 138 + d-cache-line-size = <64>; 139 + d-cache-sets = <256>; 140 + next-level-cache = <&l2_cache_cl1>; 176 141 }; 177 142 178 143 cpu7: cpu@10300 { ··· 187 138 compatible = "arm,cortex-a78ae"; 188 139 reg = <0x0 0x10300>; 189 140 enable-method = "psci"; 141 + i-cache-size = <0x10000>; 142 + i-cache-line-size = <64>; 143 + i-cache-sets = <256>; 144 + d-cache-size = <0x10000>; 145 + d-cache-line-size = <64>; 146 + d-cache-sets = <256>; 147 + next-level-cache = <&l2_cache_cl1>; 190 148 }; 191 149 192 150 cpu8: cpu@20000 { ··· 201 145 compatible = "arm,cortex-a78ae"; 202 146 reg = <0x0 0x20000>; 203 147 enable-method = "psci"; 148 + i-cache-size = <0x10000>; 149 + i-cache-line-size = <64>; 150 + i-cache-sets = <256>; 151 + d-cache-size = <0x10000>; 152 + d-cache-line-size = <64>; 153 + d-cache-sets = <256>; 154 + next-level-cache = <&l2_cache_cl2>; 204 155 }; 205 156 206 157 cpu9: cpu@20100 { ··· 215 152 compatible = "arm,cortex-a78ae"; 216 153 reg = <0x0 0x20100>; 217 154 enable-method = "psci"; 155 + i-cache-size = <0x10000>; 156 + i-cache-line-size = <64>; 157 + i-cache-sets = <256>; 158 + d-cache-size = <0x10000>; 159 + d-cache-line-size = <64>; 160 + d-cache-sets = <256>; 161 + next-level-cache = <&l2_cache_cl2>; 162 + }; 163 + 164 + l2_cache_cl0: l2-cache0 { 165 + compatible = "cache"; 166 + cache-level = <2>; 167 + cache-unified; 168 + cache-size = <0x40000>; 169 + cache-line-size = <64>; 170 + cache-sets = <512>; 171 + next-level-cache = <&l3_cache_cl0>; 172 + }; 173 + 174 + l2_cache_cl1: l2-cache1 { 175 + compatible = "cache"; 176 + cache-level = <2>; 177 + cache-unified; 178 + cache-size = <0x40000>; 179 + cache-line-size = <64>; 180 + cache-sets = <512>; 181 + next-level-cache = <&l3_cache_cl1>; 182 + }; 183 + 184 + l2_cache_cl2: l2-cache2 { 185 + compatible = "cache"; 186 + cache-level = <2>; 187 + cache-unified; 188 + cache-size = <0x40000>; 189 + cache-line-size = <64>; 190 + cache-sets = <512>; 191 + next-level-cache = <&l3_cache_cl2>; 192 + }; 193 + 194 + l3_cache_cl0: l3-cache0 { 195 + compatible = "cache"; 196 + cache-level = <3>; 197 + cache-unified; 198 + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */ 199 + cache-line-size = <64>; 200 + cache-sets = <2048>; 201 + }; 202 + 203 + l3_cache_cl1: l3-cache1 { 204 + compatible = "cache"; 205 + cache-level = <3>; 206 + cache-unified; 207 + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */ 208 + cache-line-size = <64>; 209 + cache-sets = <2048>; 210 + }; 211 + 212 + l3_cache_cl2: l3-cache2 { 213 + compatible = "cache"; 214 + cache-level = <3>; 215 + cache-unified; 216 + cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */ 217 + cache-line-size = <64>; 218 + cache-sets = <1365>; 218 219 }; 219 220 }; 220 221 ··· 565 438 compatible = "samsung,exynosautov920-pinctrl"; 566 439 reg = <0x16d20000 0x10000>; 567 440 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 441 + }; 442 + 443 + ufs_0_phy: phy@16e04000 { 444 + compatible = "samsung,exynosautov920-ufs-phy"; 445 + reg = <0x16e04000 0x4000>; 446 + reg-names = "phy-pma"; 447 + clocks = <&xtcxo>; 448 + clock-names = "ref_clk"; 449 + samsung,pmu-syscon = <&pmu_system_controller>; 450 + #phy-cells = <0>; 451 + status = "disabled"; 568 452 }; 569 453 570 454 pinctrl_aud: pinctrl@1a460000 {

+1

arch/arm64/boot/dts/exynos/google/Makefile

··· 2 2 3 3 dtb-$(CONFIG_ARCH_EXYNOS) += \ 4 4 gs101-oriole.dtb \ 5 + gs101-raven.dtb

+8 -259

arch/arm64/boot/dts/exynos/google/gs101-oriole.dts

··· 8 8 9 9 /dts-v1/; 10 10 11 - #include <dt-bindings/gpio/gpio.h> 12 - #include <dt-bindings/input/input.h> 13 - #include <dt-bindings/usb/pd.h> 14 - #include "gs101-pinctrl.h" 15 - #include "gs101.dtsi" 11 + #include "gs101-pixel-common.dtsi" 16 12 17 13 / { 18 14 model = "Oriole"; 19 15 compatible = "google,gs101-oriole", "google,gs101"; 20 - 21 - aliases { 22 - serial0 = &serial_0; 23 - }; 24 - 25 - chosen { 26 - /* Bootloader expects bootargs specified otherwise it crashes */ 27 - bootargs = ""; 28 - stdout-path = &serial_0; 29 - }; 30 - 31 - gpio-keys { 32 - compatible = "gpio-keys"; 33 - pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; 34 - pinctrl-names = "default"; 35 - 36 - button-vol-down { 37 - label = "KEY_VOLUMEDOWN"; 38 - linux,code = <KEY_VOLUMEDOWN>; 39 - gpios = <&gpa7 3 GPIO_ACTIVE_LOW>; 40 - wakeup-source; 41 - }; 42 - 43 - button-vol-up { 44 - label = "KEY_VOLUMEUP"; 45 - linux,code = <KEY_VOLUMEUP>; 46 - gpios = <&gpa8 1 GPIO_ACTIVE_LOW>; 47 - wakeup-source; 48 - }; 49 - 50 - button-power { 51 - label = "KEY_POWER"; 52 - linux,code = <KEY_POWER>; 53 - gpios = <&gpa10 1 GPIO_ACTIVE_LOW>; 54 - wakeup-source; 55 - }; 56 - }; 57 - 58 - /* TODO: Remove this once PMIC is implemented */ 59 - reg_placeholder: regulator-0 { 60 - compatible = "regulator-fixed"; 61 - regulator-name = "placeholder_reg"; 62 - }; 63 - 64 - /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ 65 - ufs_0_fixed_vcc_reg: regulator-1 { 66 - compatible = "regulator-fixed"; 67 - regulator-name = "ufs-vcc"; 68 - gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; 69 - regulator-boot-on; 70 - enable-active-high; 71 - }; 72 16 }; 73 17 74 - &ext_24_5m { 75 - clock-frequency = <24576000>; 76 - }; 77 - 78 - &ext_200m { 79 - clock-frequency = <200000000>; 80 - }; 81 - 82 - &hsi2c_8 { 83 - status = "okay"; 84 - 85 - eeprom: eeprom@50 { 86 - compatible = "atmel,24c08"; 87 - reg = <0x50>; 88 - }; 89 - }; 90 - 91 - &hsi2c_12 { 92 - status = "okay"; 93 - /* TODO: add the devices once drivers exist */ 94 - 95 - usb-typec@25 { 96 - compatible = "maxim,max77759-tcpci", "maxim,max33359"; 97 - reg = <0x25>; 98 - interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>; 99 - pinctrl-0 = <&typec_int>; 100 - pinctrl-names = "default"; 101 - 102 - connector { 103 - compatible = "usb-c-connector"; 104 - label = "USB-C"; 105 - data-role = "dual"; 106 - power-role = "dual"; 107 - self-powered; 108 - try-power-role = "sink"; 109 - op-sink-microwatt = <2600000>; 110 - slow-charger-loop; 111 - /* 112 - * max77759 operating in reverse boost mode (0xA) can 113 - * source up to 1.5A while extboost can only do ~1A. 114 - * Since extboost is the primary path, advertise 900mA. 115 - */ 116 - source-pdos = <PDO_FIXED(5000, 900, 117 - (PDO_FIXED_SUSPEND 118 - | PDO_FIXED_USB_COMM 119 - | PDO_FIXED_DATA_SWAP 120 - | PDO_FIXED_DUAL_ROLE))>; 121 - sink-pdos = <PDO_FIXED(5000, 3000, 122 - (PDO_FIXED_DATA_SWAP 123 - | PDO_FIXED_USB_COMM 124 - | PDO_FIXED_HIGHER_CAP 125 - | PDO_FIXED_DUAL_ROLE)) 126 - PDO_FIXED(9000, 2200, 0) 127 - PDO_PPS_APDO(5000, 11000, 3000)>; 128 - sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, 129 - IDH_PTYPE_DFP_HOST, 2, 0x18d1) 130 - VDO_CERT(0x0) 131 - VDO_PRODUCT(0x4ee1, 0x0) 132 - VDO_UFP(UFP_VDO_VER1_2, 133 - (DEV_USB2_CAPABLE 134 - | DEV_USB3_CAPABLE), 135 - UFP_RECEPTACLE, 0, 136 - AMA_VCONN_NOT_REQ, 0, 137 - UFP_ALTMODE_NOT_SUPP, 138 - UFP_USB32_GEN1) 139 - /* padding */ 0 140 - VDO_DFP(DFP_VDO_VER1_1, 141 - (HOST_USB2_CAPABLE 142 - | HOST_USB3_CAPABLE), 143 - DFP_RECEPTACLE, 0)>; 144 - sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, 145 - 0, 0, 0x18d1) 146 - VDO_CERT(0x0) 147 - VDO_PRODUCT(0x4ee1, 0x0)>; 148 - /* 149 - * Until bootloader is updated to set those two when 150 - * console is enabled, we disable PD here. 151 - */ 152 - pd-disable; 153 - typec-power-opmode = "default"; 154 - 155 - ports { 156 - #address-cells = <1>; 157 - #size-cells = <0>; 158 - 159 - port@0 { 160 - reg = <0>; 161 - 162 - usbc0_orien_sw: endpoint { 163 - remote-endpoint = <&usbdrd31_phy_orien_switch>; 164 - }; 165 - }; 166 - 167 - port@1 { 168 - reg = <1>; 169 - 170 - usbc0_role_sw: endpoint { 171 - remote-endpoint = <&usbdrd31_dwc3_role_switch>; 172 - }; 173 - }; 174 - }; 175 - }; 176 - }; 177 - }; 178 - 179 - &pinctrl_far_alive { 180 - key_voldown: key-voldown-pins { 181 - samsung,pins = "gpa7-3"; 182 - samsung,pin-function = <GS101_PIN_FUNC_EINT>; 183 - samsung,pin-pud = <GS101_PIN_PULL_NONE>; 184 - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 185 - }; 186 - 187 - key_volup: key-volup-pins { 188 - samsung,pins = "gpa8-1"; 189 - samsung,pin-function = <GS101_PIN_FUNC_EINT>; 190 - samsung,pin-pud = <GS101_PIN_PULL_NONE>; 191 - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 192 - }; 193 - 194 - typec_int: typec-int-pins { 195 - samsung,pins = "gpa8-2"; 196 - samsung,pin-function = <GS101_PIN_FUNC_EINT>; 197 - samsung,pin-pud = <GS101_PIN_PULL_UP>; 198 - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 199 - }; 200 - }; 201 - 202 - &pinctrl_gpio_alive { 203 - key_power: key-power-pins { 204 - samsung,pins = "gpa10-1"; 205 - samsung,pin-function = <GS101_PIN_FUNC_EINT>; 206 - samsung,pin-pud = <GS101_PIN_PULL_NONE>; 207 - samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 208 - }; 209 - }; 210 - 211 - &serial_0 { 18 + &cont_splash_mem { 19 + reg = <0x0 0xfac00000 (1080 * 2400 * 4)>; 212 20 status = "okay"; 213 21 }; 214 22 215 - &ufs_0 { 216 - status = "okay"; 217 - vcc-supply = <&ufs_0_fixed_vcc_reg>; 218 - }; 219 - 220 - &ufs_0_phy { 221 - status = "okay"; 222 - }; 223 - 224 - &usbdrd31 { 225 - vdd10-supply = <&reg_placeholder>; 226 - vdd33-supply = <&reg_placeholder>; 227 - status = "okay"; 228 - }; 229 - 230 - &usbdrd31_dwc3 { 231 - dr_mode = "otg"; 232 - usb-role-switch; 233 - role-switch-default-mode = "peripheral"; 234 - maximum-speed = "super-speed-plus"; 235 - status = "okay"; 236 - 237 - port { 238 - usbdrd31_dwc3_role_switch: endpoint { 239 - remote-endpoint = <&usbc0_role_sw>; 240 - }; 241 - }; 242 - }; 243 - 244 - &usbdrd31_phy { 245 - orientation-switch; 246 - /* TODO: Update these once PMIC is implemented */ 247 - pll-supply = <&reg_placeholder>; 248 - dvdd-usb20-supply = <&reg_placeholder>; 249 - vddh-usb20-supply = <&reg_placeholder>; 250 - vdd33-usb20-supply = <&reg_placeholder>; 251 - vdda-usbdp-supply = <&reg_placeholder>; 252 - vddh-usbdp-supply = <&reg_placeholder>; 253 - status = "okay"; 254 - 255 - port { 256 - usbdrd31_phy_orien_switch: endpoint { 257 - remote-endpoint = <&usbc0_orien_sw>; 258 - }; 259 - }; 260 - }; 261 - 262 - &usi_uart { 263 - samsung,clkreq-on; /* needed for UART mode */ 264 - status = "okay"; 265 - }; 266 - 267 - &usi8 { 268 - samsung,mode = <USI_V2_I2C>; 269 - status = "okay"; 270 - }; 271 - 272 - &usi12 { 273 - samsung,mode = <USI_V2_I2C>; 274 - status = "okay"; 275 - }; 276 - 277 - &watchdog_cl0 { 278 - timeout-sec = <30>; 23 + &framebuffer0 { 24 + width = <1080>; 25 + height = <2400>; 26 + stride = <(1080 * 4)>; 27 + format = "a8r8g8b8"; 279 28 status = "okay"; 280 29 };

+294

arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Device Tree nodes common for all GS101-based Pixel 4 + * 5 + * Copyright 2021-2023 Google LLC 6 + * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include <dt-bindings/gpio/gpio.h> 12 + #include <dt-bindings/input/input.h> 13 + #include <dt-bindings/usb/pd.h> 14 + #include "gs101-pinctrl.h" 15 + #include "gs101.dtsi" 16 + 17 + / { 18 + aliases { 19 + serial0 = &serial_0; 20 + }; 21 + 22 + chosen { 23 + /* Bootloader expects bootargs specified otherwise it crashes */ 24 + bootargs = ""; 25 + stdout-path = &serial_0; 26 + 27 + /* Use display framebuffer as setup by bootloader */ 28 + framebuffer0: framebuffer-0 { 29 + compatible = "simple-framebuffer"; 30 + memory-region = <&cont_splash_mem>; 31 + /* format properties to be added by actual board */ 32 + status = "disabled"; 33 + }; 34 + }; 35 + 36 + gpio-keys { 37 + compatible = "gpio-keys"; 38 + pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; 39 + pinctrl-names = "default"; 40 + 41 + button-vol-down { 42 + label = "KEY_VOLUMEDOWN"; 43 + linux,code = <KEY_VOLUMEDOWN>; 44 + gpios = <&gpa7 3 GPIO_ACTIVE_LOW>; 45 + wakeup-source; 46 + }; 47 + 48 + button-vol-up { 49 + label = "KEY_VOLUMEUP"; 50 + linux,code = <KEY_VOLUMEUP>; 51 + gpios = <&gpa8 1 GPIO_ACTIVE_LOW>; 52 + wakeup-source; 53 + }; 54 + 55 + button-power { 56 + label = "KEY_POWER"; 57 + linux,code = <KEY_POWER>; 58 + gpios = <&gpa10 1 GPIO_ACTIVE_LOW>; 59 + wakeup-source; 60 + }; 61 + }; 62 + 63 + /* TODO: Remove this once PMIC is implemented */ 64 + reg_placeholder: regulator-0 { 65 + compatible = "regulator-fixed"; 66 + regulator-name = "placeholder_reg"; 67 + }; 68 + 69 + /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ 70 + ufs_0_fixed_vcc_reg: regulator-1 { 71 + compatible = "regulator-fixed"; 72 + regulator-name = "ufs-vcc"; 73 + gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; 74 + regulator-boot-on; 75 + enable-active-high; 76 + }; 77 + 78 + reserved-memory { 79 + cont_splash_mem: splash@fac00000 { 80 + /* size to be updated by actual board */ 81 + reg = <0x0 0xfac00000 0x0>; 82 + no-map; 83 + status = "disabled"; 84 + }; 85 + }; 86 + }; 87 + 88 + &ext_24_5m { 89 + clock-frequency = <24576000>; 90 + }; 91 + 92 + &ext_200m { 93 + clock-frequency = <200000000>; 94 + }; 95 + 96 + &hsi2c_8 { 97 + status = "okay"; 98 + 99 + eeprom: eeprom@50 { 100 + compatible = "atmel,24c08"; 101 + reg = <0x50>; 102 + }; 103 + }; 104 + 105 + &hsi2c_12 { 106 + status = "okay"; 107 + /* TODO: add the devices once drivers exist */ 108 + 109 + usb-typec@25 { 110 + compatible = "maxim,max77759-tcpci", "maxim,max33359"; 111 + reg = <0x25>; 112 + interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>; 113 + pinctrl-0 = <&typec_int>; 114 + pinctrl-names = "default"; 115 + 116 + connector { 117 + compatible = "usb-c-connector"; 118 + label = "USB-C"; 119 + data-role = "dual"; 120 + power-role = "dual"; 121 + self-powered; 122 + try-power-role = "sink"; 123 + op-sink-microwatt = <2600000>; 124 + slow-charger-loop; 125 + /* 126 + * max77759 operating in reverse boost mode (0xA) can 127 + * source up to 1.5A while extboost can only do ~1A. 128 + * Since extboost is the primary path, advertise 900mA. 129 + */ 130 + source-pdos = <PDO_FIXED(5000, 900, 131 + (PDO_FIXED_SUSPEND 132 + | PDO_FIXED_USB_COMM 133 + | PDO_FIXED_DATA_SWAP 134 + | PDO_FIXED_DUAL_ROLE))>; 135 + sink-pdos = <PDO_FIXED(5000, 3000, 136 + (PDO_FIXED_DATA_SWAP 137 + | PDO_FIXED_USB_COMM 138 + | PDO_FIXED_HIGHER_CAP 139 + | PDO_FIXED_DUAL_ROLE)) 140 + PDO_FIXED(9000, 2200, 0) 141 + PDO_PPS_APDO(5000, 11000, 3000)>; 142 + sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, 143 + IDH_PTYPE_DFP_HOST, 2, 0x18d1) 144 + VDO_CERT(0x0) 145 + VDO_PRODUCT(0x4ee1, 0x0) 146 + VDO_UFP(UFP_VDO_VER1_2, 147 + (DEV_USB2_CAPABLE 148 + | DEV_USB3_CAPABLE), 149 + UFP_RECEPTACLE, 0, 150 + AMA_VCONN_NOT_REQ, 0, 151 + UFP_ALTMODE_NOT_SUPP, 152 + UFP_USB32_GEN1) 153 + /* padding */ 0 154 + VDO_DFP(DFP_VDO_VER1_1, 155 + (HOST_USB2_CAPABLE 156 + | HOST_USB3_CAPABLE), 157 + DFP_RECEPTACLE, 0)>; 158 + sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0, 159 + 0, 0, 0x18d1) 160 + VDO_CERT(0x0) 161 + VDO_PRODUCT(0x4ee1, 0x0)>; 162 + /* 163 + * Until bootloader is updated to set those two when 164 + * console is enabled, we disable PD here. 165 + */ 166 + pd-disable; 167 + typec-power-opmode = "default"; 168 + 169 + ports { 170 + #address-cells = <1>; 171 + #size-cells = <0>; 172 + 173 + port@0 { 174 + reg = <0>; 175 + 176 + usbc0_orien_sw: endpoint { 177 + remote-endpoint = <&usbdrd31_phy_orien_switch>; 178 + }; 179 + }; 180 + 181 + port@1 { 182 + reg = <1>; 183 + 184 + usbc0_role_sw: endpoint { 185 + remote-endpoint = <&usbdrd31_dwc3_role_switch>; 186 + }; 187 + }; 188 + }; 189 + }; 190 + }; 191 + }; 192 + 193 + &pinctrl_far_alive { 194 + key_voldown: key-voldown-pins { 195 + samsung,pins = "gpa7-3"; 196 + samsung,pin-function = <GS101_PIN_FUNC_EINT>; 197 + samsung,pin-pud = <GS101_PIN_PULL_NONE>; 198 + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 199 + }; 200 + 201 + key_volup: key-volup-pins { 202 + samsung,pins = "gpa8-1"; 203 + samsung,pin-function = <GS101_PIN_FUNC_EINT>; 204 + samsung,pin-pud = <GS101_PIN_PULL_NONE>; 205 + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 206 + }; 207 + 208 + typec_int: typec-int-pins { 209 + samsung,pins = "gpa8-2"; 210 + samsung,pin-function = <GS101_PIN_FUNC_EINT>; 211 + samsung,pin-pud = <GS101_PIN_PULL_UP>; 212 + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 213 + }; 214 + }; 215 + 216 + &pinctrl_gpio_alive { 217 + key_power: key-power-pins { 218 + samsung,pins = "gpa10-1"; 219 + samsung,pin-function = <GS101_PIN_FUNC_EINT>; 220 + samsung,pin-pud = <GS101_PIN_PULL_NONE>; 221 + samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>; 222 + }; 223 + }; 224 + 225 + &serial_0 { 226 + status = "okay"; 227 + }; 228 + 229 + &ufs_0 { 230 + status = "okay"; 231 + vcc-supply = <&ufs_0_fixed_vcc_reg>; 232 + }; 233 + 234 + &ufs_0_phy { 235 + status = "okay"; 236 + }; 237 + 238 + &usbdrd31 { 239 + vdd10-supply = <&reg_placeholder>; 240 + vdd33-supply = <&reg_placeholder>; 241 + status = "okay"; 242 + }; 243 + 244 + &usbdrd31_dwc3 { 245 + dr_mode = "otg"; 246 + usb-role-switch; 247 + role-switch-default-mode = "peripheral"; 248 + maximum-speed = "super-speed-plus"; 249 + status = "okay"; 250 + 251 + port { 252 + usbdrd31_dwc3_role_switch: endpoint { 253 + remote-endpoint = <&usbc0_role_sw>; 254 + }; 255 + }; 256 + }; 257 + 258 + &usbdrd31_phy { 259 + orientation-switch; 260 + /* TODO: Update these once PMIC is implemented */ 261 + pll-supply = <&reg_placeholder>; 262 + dvdd-usb20-supply = <&reg_placeholder>; 263 + vddh-usb20-supply = <&reg_placeholder>; 264 + vdd33-usb20-supply = <&reg_placeholder>; 265 + vdda-usbdp-supply = <&reg_placeholder>; 266 + vddh-usbdp-supply = <&reg_placeholder>; 267 + status = "okay"; 268 + 269 + port { 270 + usbdrd31_phy_orien_switch: endpoint { 271 + remote-endpoint = <&usbc0_orien_sw>; 272 + }; 273 + }; 274 + }; 275 + 276 + &usi_uart { 277 + samsung,clkreq-on; /* needed for UART mode */ 278 + status = "okay"; 279 + }; 280 + 281 + &usi8 { 282 + samsung,mode = <USI_V2_I2C>; 283 + status = "okay"; 284 + }; 285 + 286 + &usi12 { 287 + samsung,mode = <USI_V2_I2C>; 288 + status = "okay"; 289 + }; 290 + 291 + &watchdog_cl0 { 292 + timeout-sec = <30>; 293 + status = "okay"; 294 + };

+29

arch/arm64/boot/dts/exynos/google/gs101-raven.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Raven Device Tree 4 + * 5 + * Copyright 2021-2023 Google LLC 6 + * Copyright 2023-2025 Linaro Ltd 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "gs101-pixel-common.dtsi" 12 + 13 + / { 14 + model = "Raven"; 15 + compatible = "google,gs101-raven", "google,gs101"; 16 + }; 17 + 18 + &cont_splash_mem { 19 + reg = <0x0 0xfac00000 (1440 * 3120 * 4)>; 20 + status = "okay"; 21 + }; 22 + 23 + &framebuffer0 { 24 + width = <1440>; 25 + height = <3120>; 26 + stride = <(1440 * 4)>; 27 + format = "a8r8g8b8"; 28 + status = "okay"; 29 + };

+52 -14

arch/arm64/boot/dts/exynos/google/gs101.dtsi

··· 73 73 compatible = "arm,cortex-a55"; 74 74 reg = <0x0000>; 75 75 enable-method = "psci"; 76 - cpu-idle-states = <&ANANKE_CPU_SLEEP>; 76 + cpu-idle-states = <&ananke_cpu_sleep>; 77 77 capacity-dmips-mhz = <250>; 78 78 dynamic-power-coefficient = <70>; 79 79 }; ··· 83 83 compatible = "arm,cortex-a55"; 84 84 reg = <0x0100>; 85 85 enable-method = "psci"; 86 - cpu-idle-states = <&ANANKE_CPU_SLEEP>; 86 + cpu-idle-states = <&ananke_cpu_sleep>; 87 87 capacity-dmips-mhz = <250>; 88 88 dynamic-power-coefficient = <70>; 89 89 }; ··· 93 93 compatible = "arm,cortex-a55"; 94 94 reg = <0x0200>; 95 95 enable-method = "psci"; 96 - cpu-idle-states = <&ANANKE_CPU_SLEEP>; 96 + cpu-idle-states = <&ananke_cpu_sleep>; 97 97 capacity-dmips-mhz = <250>; 98 98 dynamic-power-coefficient = <70>; 99 99 }; ··· 103 103 compatible = "arm,cortex-a55"; 104 104 reg = <0x0300>; 105 105 enable-method = "psci"; 106 - cpu-idle-states = <&ANANKE_CPU_SLEEP>; 106 + cpu-idle-states = <&ananke_cpu_sleep>; 107 107 capacity-dmips-mhz = <250>; 108 108 dynamic-power-coefficient = <70>; 109 109 }; ··· 113 113 compatible = "arm,cortex-a76"; 114 114 reg = <0x0400>; 115 115 enable-method = "psci"; 116 - cpu-idle-states = <&ENYO_CPU_SLEEP>; 116 + cpu-idle-states = <&enyo_cpu_sleep>; 117 117 capacity-dmips-mhz = <620>; 118 118 dynamic-power-coefficient = <284>; 119 119 }; ··· 123 123 compatible = "arm,cortex-a76"; 124 124 reg = <0x0500>; 125 125 enable-method = "psci"; 126 - cpu-idle-states = <&ENYO_CPU_SLEEP>; 126 + cpu-idle-states = <&enyo_cpu_sleep>; 127 127 capacity-dmips-mhz = <620>; 128 128 dynamic-power-coefficient = <284>; 129 129 }; ··· 133 133 compatible = "arm,cortex-x1"; 134 134 reg = <0x0600>; 135 135 enable-method = "psci"; 136 - cpu-idle-states = <&HERA_CPU_SLEEP>; 136 + cpu-idle-states = <&hera_cpu_sleep>; 137 137 capacity-dmips-mhz = <1024>; 138 138 dynamic-power-coefficient = <650>; 139 139 }; ··· 143 143 compatible = "arm,cortex-x1"; 144 144 reg = <0x0700>; 145 145 enable-method = "psci"; 146 - cpu-idle-states = <&HERA_CPU_SLEEP>; 146 + cpu-idle-states = <&hera_cpu_sleep>; 147 147 capacity-dmips-mhz = <1024>; 148 148 dynamic-power-coefficient = <650>; 149 149 }; ··· 151 151 idle-states { 152 152 entry-method = "psci"; 153 153 154 - ANANKE_CPU_SLEEP: cpu-ananke-sleep { 154 + ananke_cpu_sleep: cpu-ananke-sleep { 155 155 idle-state-name = "c2"; 156 156 compatible = "arm,idle-state"; 157 157 arm,psci-suspend-param = <0x0010000>; ··· 160 160 min-residency-us = <2000>; 161 161 }; 162 162 163 - ENYO_CPU_SLEEP: cpu-enyo-sleep { 163 + enyo_cpu_sleep: cpu-enyo-sleep { 164 164 idle-state-name = "c2"; 165 165 compatible = "arm,idle-state"; 166 166 arm,psci-suspend-param = <0x0010000>; ··· 169 169 min-residency-us = <2500>; 170 170 }; 171 171 172 - HERA_CPU_SLEEP: cpu-hera-sleep { 172 + hera_cpu_sleep: cpu-hera-sleep { 173 173 idle-state-name = "c2"; 174 174 compatible = "arm,idle-state"; 175 175 arm,psci-suspend-param = <0x0010000>; ··· 194 194 compatible = "fixed-clock"; 195 195 #clock-cells = <0>; 196 196 clock-output-names = "ext-200m"; 197 + }; 198 + 199 + firmware { 200 + acpm_ipc: power-management { 201 + compatible = "google,gs101-acpm-ipc"; 202 + mboxes = <&ap2apm_mailbox>; 203 + shmem = <&apm_sram>; 204 + }; 197 205 }; 198 206 199 207 pmu-0 { ··· 1408 1400 1409 1401 poweroff: syscon-poweroff { 1410 1402 compatible = "syscon-poweroff"; 1411 - regmap = <&pmu_system_controller>; 1412 1403 offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ 1413 - mask = <0x100>; /* reset value */ 1404 + mask = <0x00000100>; 1405 + value = <0x0>; 1414 1406 }; 1415 1407 1416 1408 reboot: syscon-reboot { 1417 1409 compatible = "syscon-reboot"; 1418 - regmap = <&pmu_system_controller>; 1419 1410 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 1420 1411 mask = <0x2>; /* SWRESET_SYSTEM */ 1421 1412 value = <0x2>; /* reset value */ 1413 + }; 1414 + 1415 + reboot-mode { 1416 + compatible = "syscon-reboot-mode"; 1417 + offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */ 1418 + mode-bootloader = <0xfc>; 1419 + mode-charge = <0x0a>; 1420 + mode-fastboot = <0xfa>; 1421 + mode-reboot-ab-update = <0x52>; 1422 + mode-recovery = <0xff>; 1423 + mode-rescue = <0xf9>; 1424 + mode-shutdown-thermal = <0x51>; 1425 + mode-shutdown-thermal-battery = <0x51>; 1422 1426 }; 1423 1427 }; 1424 1428 ··· 1460 1440 }; 1461 1441 }; 1462 1442 1443 + ap2apm_mailbox: mailbox@17610000 { 1444 + compatible = "google,gs101-mbox"; 1445 + reg = <0x17610000 0x1000>; 1446 + clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; 1447 + clock-names = "pclk"; 1448 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>; 1449 + #mbox-cells = <0>; 1450 + }; 1451 + 1463 1452 pinctrl_gsactrl: pinctrl@17940000 { 1464 1453 compatible = "google,gs101-pinctrl"; 1465 1454 reg = <0x17940000 0x00001000>; ··· 1483 1454 /* TODO: update once support for this CMU exists */ 1484 1455 clocks = <0>; 1485 1456 clock-names = "pclk"; 1457 + status = "disabled"; 1486 1458 }; 1487 1459 1488 1460 cmu_top: clock-controller@1e080000 { ··· 1494 1464 clocks = <&ext_24_5m>; 1495 1465 clock-names = "oscclk"; 1496 1466 }; 1467 + }; 1468 + 1469 + apm_sram: sram@2039000 { 1470 + compatible = "mmio-sram"; 1471 + reg = <0x0 0x2039000 0x40000>; 1472 + #address-cells = <1>; 1473 + #size-cells = <1>; 1474 + ranges = <0x0 0x0 0x2039000 0x40000>; 1497 1475 }; 1498 1476 1499 1477 timer {

+13 -13

arch/arm64/boot/dts/tesla/fsd.dtsi

··· 92 92 reg = <0x0 0x000>; 93 93 enable-method = "psci"; 94 94 clock-frequency = <2400000000>; 95 - cpu-idle-states = <&CPU_SLEEP>; 95 + cpu-idle-states = <&cpu_sleep>; 96 96 i-cache-size = <0xc000>; 97 97 i-cache-line-size = <64>; 98 98 i-cache-sets = <256>; ··· 108 108 reg = <0x0 0x001>; 109 109 enable-method = "psci"; 110 110 clock-frequency = <2400000000>; 111 - cpu-idle-states = <&CPU_SLEEP>; 111 + cpu-idle-states = <&cpu_sleep>; 112 112 i-cache-size = <0xc000>; 113 113 i-cache-line-size = <64>; 114 114 i-cache-sets = <256>; ··· 124 124 reg = <0x0 0x002>; 125 125 enable-method = "psci"; 126 126 clock-frequency = <2400000000>; 127 - cpu-idle-states = <&CPU_SLEEP>; 127 + cpu-idle-states = <&cpu_sleep>; 128 128 i-cache-size = <0xc000>; 129 129 i-cache-line-size = <64>; 130 130 i-cache-sets = <256>; ··· 139 139 compatible = "arm,cortex-a72"; 140 140 reg = <0x0 0x003>; 141 141 enable-method = "psci"; 142 - cpu-idle-states = <&CPU_SLEEP>; 142 + cpu-idle-states = <&cpu_sleep>; 143 143 i-cache-size = <0xc000>; 144 144 i-cache-line-size = <64>; 145 145 i-cache-sets = <256>; ··· 156 156 reg = <0x0 0x100>; 157 157 enable-method = "psci"; 158 158 clock-frequency = <2400000000>; 159 - cpu-idle-states = <&CPU_SLEEP>; 159 + cpu-idle-states = <&cpu_sleep>; 160 160 i-cache-size = <0xc000>; 161 161 i-cache-line-size = <64>; 162 162 i-cache-sets = <256>; ··· 172 172 reg = <0x0 0x101>; 173 173 enable-method = "psci"; 174 174 clock-frequency = <2400000000>; 175 - cpu-idle-states = <&CPU_SLEEP>; 175 + cpu-idle-states = <&cpu_sleep>; 176 176 i-cache-size = <0xc000>; 177 177 i-cache-line-size = <64>; 178 178 i-cache-sets = <256>; ··· 188 188 reg = <0x0 0x102>; 189 189 enable-method = "psci"; 190 190 clock-frequency = <2400000000>; 191 - cpu-idle-states = <&CPU_SLEEP>; 191 + cpu-idle-states = <&cpu_sleep>; 192 192 i-cache-size = <0xc000>; 193 193 i-cache-line-size = <64>; 194 194 i-cache-sets = <256>; ··· 204 204 reg = <0x0 0x103>; 205 205 enable-method = "psci"; 206 206 clock-frequency = <2400000000>; 207 - cpu-idle-states = <&CPU_SLEEP>; 207 + cpu-idle-states = <&cpu_sleep>; 208 208 i-cache-size = <0xc000>; 209 209 i-cache-line-size = <64>; 210 210 i-cache-sets = <256>; ··· 221 221 reg = <0x0 0x200>; 222 222 enable-method = "psci"; 223 223 clock-frequency = <2400000000>; 224 - cpu-idle-states = <&CPU_SLEEP>; 224 + cpu-idle-states = <&cpu_sleep>; 225 225 i-cache-size = <0xc000>; 226 226 i-cache-line-size = <64>; 227 227 i-cache-sets = <256>; ··· 237 237 reg = <0x0 0x201>; 238 238 enable-method = "psci"; 239 239 clock-frequency = <2400000000>; 240 - cpu-idle-states = <&CPU_SLEEP>; 240 + cpu-idle-states = <&cpu_sleep>; 241 241 i-cache-size = <0xc000>; 242 242 i-cache-line-size = <64>; 243 243 i-cache-sets = <256>; ··· 253 253 reg = <0x0 0x202>; 254 254 enable-method = "psci"; 255 255 clock-frequency = <2400000000>; 256 - cpu-idle-states = <&CPU_SLEEP>; 256 + cpu-idle-states = <&cpu_sleep>; 257 257 i-cache-size = <0xc000>; 258 258 i-cache-line-size = <64>; 259 259 i-cache-sets = <256>; ··· 269 269 reg = <0x0 0x203>; 270 270 enable-method = "psci"; 271 271 clock-frequency = <2400000000>; 272 - cpu-idle-states = <&CPU_SLEEP>; 272 + cpu-idle-states = <&cpu_sleep>; 273 273 i-cache-size = <0xc000>; 274 274 i-cache-line-size = <64>; 275 275 i-cache-sets = <256>; ··· 291 291 idle-states { 292 292 entry-method = "psci"; 293 293 294 - CPU_SLEEP: cpu-sleep { 294 + cpu_sleep: cpu-sleep { 295 295 idle-state-name = "c2"; 296 296 compatible = "arm,idle-state"; 297 297 local-timer-stop;

+21

include/dt-bindings/clock/samsung,exynos990.h

··· 233 233 #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 234 234 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 235 235 236 + /* CMU_PERIS */ 237 + #define CLK_MOUT_PERIS_BUS_USER 1 238 + #define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 239 + #define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3 240 + #define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4 241 + #define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5 242 + #define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6 243 + #define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7 244 + #define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8 245 + #define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9 246 + #define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10 247 + #define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11 248 + #define CLK_GOUT_PERIS_GIC_CLK 12 249 + #define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13 250 + #define CLK_GOUT_PERIS_MCT_PCLK 14 251 + #define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15 252 + #define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16 253 + #define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 254 + #define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 255 + #define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 256 + 236 257 #endif

+13 -4

include/dt-bindings/soc/samsung,exynos-usi.h

··· 9 9 #ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H 10 10 #define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H 11 11 12 - #define USI_V2_NONE 0 13 - #define USI_V2_UART 1 14 - #define USI_V2_SPI 2 15 - #define USI_V2_I2C 3 12 + #define USI_MODE_NONE 0 13 + #define USI_MODE_UART 1 14 + #define USI_MODE_SPI 2 15 + #define USI_MODE_I2C 3 16 + #define USI_MODE_I2C1 4 17 + #define USI_MODE_I2C0_1 5 18 + #define USI_MODE_UART_I2C1 6 19 + 20 + /* Deprecated */ 21 + #define USI_V2_NONE USI_MODE_NONE 22 + #define USI_V2_UART USI_MODE_UART 23 + #define USI_V2_SPI USI_MODE_SPI 24 + #define USI_V2_I2C USI_MODE_I2C 16 25 17 26 #endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */