tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/vcn: use inst_idx relacing inst
Use inst_idx relacing inst in SOC15_DPG_MODE macro to avoid confusion.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
James Zhu
and committed by
Alex Deucher
55bbb747
a4555732
+12
-12
+12
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drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+12
-12
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
···
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/* 1 second timeout */
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#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
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#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
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({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask, sram_sel) \
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({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__MASK_EN_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
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RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
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})
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#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
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#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask, sram_sel) \
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do { \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
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WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
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UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
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((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
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((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
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<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
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(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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} while (0)
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#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \
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#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst_idx, reg) \
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({ \
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uint32_t internal_reg_offset, addr; \
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bool video_range, aon_range; \
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\
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addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
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addr <<= 2; \
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video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
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((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \