clk: rockchip: mark noc and some special clk as critical on rk3288

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.

The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Elaine Zhang and committed by

Heiko Stuebner 8 years ago 55bb6a63 f18c0994

+10 -4

1 changed file

expand all

drivers

clk

rockchip

clk-rk3288.c

+10 -4

drivers/clk/rockchip/clk-rk3288.c

··· 292 292 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED, 293 293 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 294 294 RK3288_CLKGATE_CON(12), 6, GFLAGS), 295 - COMPOSITE_NOMUX(0, "atclk", "armclk", 0, 295 + COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED, 296 296 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 297 297 RK3288_CLKGATE_CON(12), 7, GFLAGS), 298 298 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED, 299 299 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 300 300 RK3288_CLKGATE_CON(12), 8, GFLAGS), 301 - GATE(0, "pclk_dbg", "pclk_dbg_pre", 0, 301 + GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED, 302 302 RK3288_CLKGATE_CON(12), 9, GFLAGS), 303 303 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED, 304 304 RK3288_CLKGATE_CON(12), 10, GFLAGS), ··· 626 626 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", 627 627 RK3288_CLKSEL_CON(22), 7, IFLAGS), 628 628 629 - GATE(0, "jtag", "ext_jtag", 0, 629 + GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, 630 630 RK3288_CLKGATE_CON(4), 14, GFLAGS), 631 631 632 632 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0, ··· 635 635 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, 636 636 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS, 637 637 RK3288_CLKGATE_CON(3), 6, GFLAGS), 638 - GATE(0, "hsicphy12m_xin12m", "xin12m", 0, 638 + GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED, 639 639 RK3288_CLKGATE_CON(13), 9, GFLAGS), 640 640 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0, 641 641 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS), ··· 816 816 "pclk_alive_niu", 817 817 "pclk_pd_pmu", 818 818 "pclk_pmu_niu", 819 + "pclk_core_niu", 820 + "pclk_ddrupctl0", 821 + "pclk_publ0", 822 + "pclk_ddrupctl1", 823 + "pclk_publ1", 824 + "pmu_hclk_otg0", 819 825 }; 820 826 821 827 static void __iomem *rk3288_cru_base;