tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
sh: Add support for SH7786 CPU subtype.
This adds preliminary support for the SH7786 CPU subtype.
While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.
More information on this particular CPU subtype is available at:
http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
authored by
Kuninori Morimoto
and committed by
Paul Mundt
55ba99eb
93fde774
+1734
-6
+7
arch/sh/Kconfig
+7
arch/sh/Kconfig
···
356
356
select ARCH_SPARSEMEM_ENABLE
357
357
select SYS_SUPPORTS_NUMA
358
358
359
+
config CPU_SUBTYPE_SH7786
360
+
bool "Support SH7786 processor"
361
+
select CPU_SH4A
362
+
select CPU_SHX2
363
+
select ARCH_SPARSEMEM_ENABLE
364
+
select SYS_SUPPORTS_NUMA
365
+
359
366
config CPU_SUBTYPE_SHX3
360
367
bool "Support SH-X3 processor"
361
368
select CPU_SH4A
+1
-1
arch/sh/include/asm/processor.h
+1
-1
arch/sh/include/asm/processor.h
+4
arch/sh/include/cpu-sh4/cpu/freq.h
+4
arch/sh/include/cpu-sh4/cpu/freq.h
···
29
29
#define FRQCR0 0xffc80000
30
30
#define FRQCR1 0xffc80004
31
31
#define FRQMR1 0xffc80014
32
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
33
+
#define FRQCR0 0xffc40000
34
+
#define FRQCR1 0xffc40004
35
+
#define FRQMR1 0xffc40014
32
36
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
33
37
#define FRQCR 0xffc00014
34
38
#else
+192
arch/sh/include/cpu-sh4/cpu/sh7786.h
+192
arch/sh/include/cpu-sh4/cpu/sh7786.h
···
1
+
/*
2
+
* SH7786 Pinmux
3
+
*
4
+
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
5
+
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
6
+
*
7
+
* Based on sh7785.h
8
+
*
9
+
* This file is subject to the terms and conditions of the GNU General Public
10
+
* License. See the file "COPYING" in the main directory of this archive
11
+
* for more details.
12
+
*/
13
+
14
+
#ifndef __CPU_SH7786_H__
15
+
#define __CPU_SH7786_H__
16
+
17
+
enum {
18
+
/* PA */
19
+
GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
20
+
GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
21
+
22
+
/* PB */
23
+
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
24
+
GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
25
+
26
+
/* PC */
27
+
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
28
+
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
29
+
30
+
/* PD */
31
+
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
32
+
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
33
+
34
+
/* PE */
35
+
GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
36
+
GPIO_PE1, GPIO_PE0,
37
+
38
+
/* PF */
39
+
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
40
+
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
41
+
42
+
/* PG */
43
+
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
44
+
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
45
+
46
+
/* PH */
47
+
GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
48
+
GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
49
+
50
+
/* PJ */
51
+
GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
52
+
GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
53
+
54
+
GPIO_FN_CDE,
55
+
GPIO_FN_ETH_MAGIC,
56
+
GPIO_FN_DISP,
57
+
GPIO_FN_ETH_LINK,
58
+
GPIO_FN_DR5,
59
+
GPIO_FN_ETH_TX_ER,
60
+
GPIO_FN_DR4,
61
+
GPIO_FN_ETH_TX_EN,
62
+
GPIO_FN_DR3,
63
+
GPIO_FN_ETH_TXD3,
64
+
GPIO_FN_DR2,
65
+
GPIO_FN_ETH_TXD2,
66
+
GPIO_FN_DR1,
67
+
GPIO_FN_ETH_TXD1,
68
+
GPIO_FN_DR0,
69
+
GPIO_FN_ETH_TXD0,
70
+
GPIO_FN_VSYNC,
71
+
GPIO_FN_HSPI_CLK,
72
+
GPIO_FN_ODDF,
73
+
GPIO_FN_HSPI_CS,
74
+
GPIO_FN_DG5,
75
+
GPIO_FN_ETH_MDIO,
76
+
GPIO_FN_DG4,
77
+
GPIO_FN_ETH_RX_CLK,
78
+
GPIO_FN_DG3,
79
+
GPIO_FN_ETH_MDC,
80
+
GPIO_FN_DG2,
81
+
GPIO_FN_ETH_COL,
82
+
GPIO_FN_DG1,
83
+
GPIO_FN_ETH_TX_CLK,
84
+
GPIO_FN_DG0,
85
+
GPIO_FN_ETH_CRS,
86
+
GPIO_FN_DCLKIN,
87
+
GPIO_FN_HSPI_RX,
88
+
GPIO_FN_HSYNC,
89
+
GPIO_FN_HSPI_TX,
90
+
GPIO_FN_DB5,
91
+
GPIO_FN_ETH_RXD3,
92
+
GPIO_FN_DB4,
93
+
GPIO_FN_ETH_RXD2,
94
+
GPIO_FN_DB3,
95
+
GPIO_FN_ETH_RXD1,
96
+
GPIO_FN_DB2,
97
+
GPIO_FN_ETH_RXD0,
98
+
GPIO_FN_DB1,
99
+
GPIO_FN_ETH_RX_DV,
100
+
GPIO_FN_DB0,
101
+
GPIO_FN_ETH_RX_ER,
102
+
GPIO_FN_DCLKOUT,
103
+
GPIO_FN_SCIF1_SLK,
104
+
GPIO_FN_SCIF1_RXD,
105
+
GPIO_FN_SCIF1_TXD,
106
+
GPIO_FN_DACK1,
107
+
GPIO_FN_BACK,
108
+
GPIO_FN_FALE,
109
+
GPIO_FN_DACK0,
110
+
GPIO_FN_FCLE,
111
+
GPIO_FN_DREQ1,
112
+
GPIO_FN_BREQ,
113
+
GPIO_FN_USB_OVC1,
114
+
GPIO_FN_DREQ0,
115
+
GPIO_FN_USB_OVC0,
116
+
GPIO_FN_USB_PENC1,
117
+
GPIO_FN_USB_PENC0,
118
+
GPIO_FN_HAC1_SDOUT,
119
+
GPIO_FN_SSI1_SDATA,
120
+
GPIO_FN_SDIF1CMD,
121
+
GPIO_FN_HAC1_SDIN,
122
+
GPIO_FN_SSI1_SCK,
123
+
GPIO_FN_SDIF1CD,
124
+
GPIO_FN_HAC1_SYNC,
125
+
GPIO_FN_SSI1_WS,
126
+
GPIO_FN_SDIF1WP,
127
+
GPIO_FN_HAC1_BITCLK,
128
+
GPIO_FN_SSI1_CLK,
129
+
GPIO_FN_SDIF1CLK,
130
+
GPIO_FN_HAC0_SDOUT,
131
+
GPIO_FN_SSI0_SDATA,
132
+
GPIO_FN_SDIF1D3,
133
+
GPIO_FN_HAC0_SDIN,
134
+
GPIO_FN_SSI0_SCK,
135
+
GPIO_FN_SDIF1D2,
136
+
GPIO_FN_HAC0_SYNC,
137
+
GPIO_FN_SSI0_WS,
138
+
GPIO_FN_SDIF1D1,
139
+
GPIO_FN_HAC0_BITCLK,
140
+
GPIO_FN_SSI0_CLK,
141
+
GPIO_FN_SDIF1D0,
142
+
GPIO_FN_SCIF3_SCK,
143
+
GPIO_FN_SSI2_SDATA,
144
+
GPIO_FN_SCIF3_RXD,
145
+
GPIO_FN_TCLK,
146
+
GPIO_FN_SSI2_SCK,
147
+
GPIO_FN_SCIF3_TXD,
148
+
GPIO_FN_HAC_RES,
149
+
GPIO_FN_SSI2_WS,
150
+
GPIO_FN_DACK3,
151
+
GPIO_FN_SDIF0CMD,
152
+
GPIO_FN_DACK2,
153
+
GPIO_FN_SDIF0CD,
154
+
GPIO_FN_DREQ3,
155
+
GPIO_FN_SDIF0WP,
156
+
GPIO_FN_SCIF0_CTS,
157
+
GPIO_FN_DREQ2,
158
+
GPIO_FN_SDIF0CLK,
159
+
GPIO_FN_SCIF0_RTS,
160
+
GPIO_FN_IRL7,
161
+
GPIO_FN_SDIF0D3,
162
+
GPIO_FN_SCIF0_SCK,
163
+
GPIO_FN_IRL6,
164
+
GPIO_FN_SDIF0D2,
165
+
GPIO_FN_SCIF0_RXD,
166
+
GPIO_FN_IRL5,
167
+
GPIO_FN_SDIF0D1,
168
+
GPIO_FN_SCIF0_TXD,
169
+
GPIO_FN_IRL4,
170
+
GPIO_FN_SDIF0D0,
171
+
GPIO_FN_SCIF5_SCK,
172
+
GPIO_FN_FRB,
173
+
GPIO_FN_SCIF5_RXD,
174
+
GPIO_FN_IOIS16,
175
+
GPIO_FN_SCIF5_TXD,
176
+
GPIO_FN_CE2B,
177
+
GPIO_FN_DRAK3,
178
+
GPIO_FN_CE2A,
179
+
GPIO_FN_SCIF4_SCK,
180
+
GPIO_FN_DRAK2,
181
+
GPIO_FN_SSI3_WS,
182
+
GPIO_FN_SCIF4_RXD,
183
+
GPIO_FN_DRAK1,
184
+
GPIO_FN_SSI3_SDATA,
185
+
GPIO_FN_FSTATUS,
186
+
GPIO_FN_SCIF4_TXD,
187
+
GPIO_FN_DRAK0,
188
+
GPIO_FN_SSI3_SCK,
189
+
GPIO_FN_FSE,
190
+
};
191
+
192
+
#endif /* __CPU_SH7786_H__ */
+7
arch/sh/kernel/cpu/sh4/probe.c
+7
arch/sh/kernel/cpu/sh4/probe.c
···
129
129
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
130
130
CPU_HAS_LLSC;
131
131
break;
132
+
case 0x4004:
133
+
boot_cpu_data.type = CPU_SH7786;
134
+
boot_cpu_data.icache.ways = 4;
135
+
boot_cpu_data.dcache.ways = 4;
136
+
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
137
+
CPU_HAS_LLSC;
138
+
break;
132
139
case 0x3008:
133
140
boot_cpu_data.icache.ways = 4;
134
141
boot_cpu_data.dcache.ways = 4;
+3
arch/sh/kernel/cpu/sh4a/Makefile
+3
arch/sh/kernel/cpu/sh4a/Makefile
···
7
7
obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
8
8
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
9
9
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
10
+
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
10
11
obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
11
12
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
12
13
obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
···
22
21
clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
23
22
clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
24
23
clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
24
+
clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
25
25
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
26
26
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
27
27
clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
···
33
31
pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
34
32
pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
35
33
pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
34
+
pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
36
35
37
36
obj-y += $(clock-y)
38
37
obj-$(CONFIG_SMP) += $(smp-y)
+148
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+148
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
···
1
+
/*
2
+
* arch/sh/kernel/cpu/sh4a/clock-sh7786.c
3
+
*
4
+
* SH7786 support for the clock framework
5
+
*
6
+
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
7
+
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
8
+
*
9
+
* Based on SH7785
10
+
* Copyright (C) 2007 Paul Mundt
11
+
*
12
+
* This file is subject to the terms and conditions of the GNU General Public
13
+
* License. See the file "COPYING" in the main directory of this archive
14
+
* for more details.
15
+
*/
16
+
#include <linux/init.h>
17
+
#include <linux/kernel.h>
18
+
#include <asm/clock.h>
19
+
#include <asm/freq.h>
20
+
#include <asm/io.h>
21
+
22
+
static int ifc_divisors[] = { 1, 2, 4, 1 };
23
+
static int sfc_divisors[] = { 1, 1, 4, 1 };
24
+
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
25
+
24, 32, 1, 1, 1, 1, 1, 1 };
26
+
static int mfc_divisors[] = { 1, 1, 4, 1 };
27
+
static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
28
+
24, 32, 1, 48, 1, 1, 1, 1 };
29
+
30
+
static void master_clk_init(struct clk *clk)
31
+
{
32
+
clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
33
+
}
34
+
35
+
static struct clk_ops sh7786_master_clk_ops = {
36
+
.init = master_clk_init,
37
+
};
38
+
39
+
static void module_clk_recalc(struct clk *clk)
40
+
{
41
+
int idx = (ctrl_inl(FRQMR1) & 0x000f);
42
+
clk->rate = clk->parent->rate / pfc_divisors[idx];
43
+
}
44
+
45
+
static struct clk_ops sh7786_module_clk_ops = {
46
+
.recalc = module_clk_recalc,
47
+
};
48
+
49
+
static void bus_clk_recalc(struct clk *clk)
50
+
{
51
+
int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52
+
clk->rate = clk->parent->rate / bfc_divisors[idx];
53
+
}
54
+
55
+
static struct clk_ops sh7786_bus_clk_ops = {
56
+
.recalc = bus_clk_recalc,
57
+
};
58
+
59
+
static void cpu_clk_recalc(struct clk *clk)
60
+
{
61
+
int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62
+
clk->rate = clk->parent->rate / ifc_divisors[idx];
63
+
}
64
+
65
+
static struct clk_ops sh7786_cpu_clk_ops = {
66
+
.recalc = cpu_clk_recalc,
67
+
};
68
+
69
+
static struct clk_ops *sh7786_clk_ops[] = {
70
+
&sh7786_master_clk_ops,
71
+
&sh7786_module_clk_ops,
72
+
&sh7786_bus_clk_ops,
73
+
&sh7786_cpu_clk_ops,
74
+
};
75
+
76
+
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
77
+
{
78
+
if (idx < ARRAY_SIZE(sh7786_clk_ops))
79
+
*ops = sh7786_clk_ops[idx];
80
+
}
81
+
82
+
static void shyway_clk_recalc(struct clk *clk)
83
+
{
84
+
int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85
+
clk->rate = clk->parent->rate / sfc_divisors[idx];
86
+
}
87
+
88
+
static struct clk_ops sh7786_shyway_clk_ops = {
89
+
.recalc = shyway_clk_recalc,
90
+
};
91
+
92
+
static struct clk sh7786_shyway_clk = {
93
+
.name = "shyway_clk",
94
+
.flags = CLK_ALWAYS_ENABLED,
95
+
.ops = &sh7786_shyway_clk_ops,
96
+
};
97
+
98
+
static void ddr_clk_recalc(struct clk *clk)
99
+
{
100
+
int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101
+
clk->rate = clk->parent->rate / mfc_divisors[idx];
102
+
}
103
+
104
+
static struct clk_ops sh7786_ddr_clk_ops = {
105
+
.recalc = ddr_clk_recalc,
106
+
};
107
+
108
+
static struct clk sh7786_ddr_clk = {
109
+
.name = "ddr_clk",
110
+
.flags = CLK_ALWAYS_ENABLED,
111
+
.ops = &sh7786_ddr_clk_ops,
112
+
};
113
+
114
+
/*
115
+
* Additional SH7786-specific on-chip clocks that aren't already part of the
116
+
* clock framework
117
+
*/
118
+
static struct clk *sh7786_onchip_clocks[] = {
119
+
&sh7786_shyway_clk,
120
+
&sh7786_ddr_clk,
121
+
};
122
+
123
+
static int __init sh7786_clk_init(void)
124
+
{
125
+
struct clk *clk = clk_get(NULL, "master_clk");
126
+
int i;
127
+
128
+
for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
129
+
struct clk *clkp = sh7786_onchip_clocks[i];
130
+
131
+
clkp->parent = clk;
132
+
clk_register(clkp);
133
+
clk_enable(clkp);
134
+
}
135
+
136
+
/*
137
+
* Now that we have the rest of the clocks registered, we need to
138
+
* force the parent clock to propagate so that these clocks will
139
+
* automatically figure out their rate. We cheat by handing the
140
+
* parent clock its current rate and forcing child propagation.
141
+
*/
142
+
clk_set_rate(clk, clk_get_rate(clk));
143
+
144
+
clk_put(clk);
145
+
146
+
return 0;
147
+
}
148
+
arch_initcall(sh7786_clk_init);
+950
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
+950
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
···
1
+
/*
2
+
* SH7786 Pinmux
3
+
*
4
+
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
5
+
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
6
+
*
7
+
* Based on SH7785 pinmux
8
+
*
9
+
* Copyright (C) 2008 Magnus Damm
10
+
*
11
+
* This file is subject to the terms and conditions of the GNU General Public
12
+
* License. See the file "COPYING" in the main directory of this archive
13
+
* for more details.
14
+
*/
15
+
16
+
#include <linux/init.h>
17
+
#include <linux/kernel.h>
18
+
#include <linux/gpio.h>
19
+
#include <cpu/sh7786.h>
20
+
21
+
enum {
22
+
PINMUX_RESERVED = 0,
23
+
24
+
PINMUX_DATA_BEGIN,
25
+
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
26
+
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
27
+
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
28
+
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
29
+
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
30
+
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
31
+
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
32
+
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
33
+
PE7_DATA, PE6_DATA,
34
+
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
35
+
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
36
+
PG7_DATA, PG6_DATA, PG5_DATA,
37
+
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
38
+
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
39
+
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
40
+
PJ3_DATA, PJ2_DATA, PJ1_DATA,
41
+
PINMUX_DATA_END,
42
+
43
+
PINMUX_INPUT_BEGIN,
44
+
PA7_IN, PA6_IN, PA5_IN, PA4_IN,
45
+
PA3_IN, PA2_IN, PA1_IN, PA0_IN,
46
+
PB7_IN, PB6_IN, PB5_IN, PB4_IN,
47
+
PB3_IN, PB2_IN, PB1_IN, PB0_IN,
48
+
PC7_IN, PC6_IN, PC5_IN, PC4_IN,
49
+
PC3_IN, PC2_IN, PC1_IN, PC0_IN,
50
+
PD7_IN, PD6_IN, PD5_IN, PD4_IN,
51
+
PD3_IN, PD2_IN, PD1_IN, PD0_IN,
52
+
PE7_IN, PE6_IN,
53
+
PF7_IN, PF6_IN, PF5_IN, PF4_IN,
54
+
PF3_IN, PF2_IN, PF1_IN, PF0_IN,
55
+
PG7_IN, PG6_IN, PG5_IN,
56
+
PH7_IN, PH6_IN, PH5_IN, PH4_IN,
57
+
PH3_IN, PH2_IN, PH1_IN, PH0_IN,
58
+
PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
59
+
PJ3_IN, PJ2_IN, PJ1_IN,
60
+
PINMUX_INPUT_END,
61
+
62
+
PINMUX_INPUT_PULLUP_BEGIN,
63
+
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
64
+
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
65
+
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
66
+
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
67
+
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
68
+
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
69
+
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
70
+
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
71
+
PE7_IN_PU, PE6_IN_PU,
72
+
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
73
+
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
74
+
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
75
+
PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
76
+
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
77
+
PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
78
+
PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
79
+
PINMUX_INPUT_PULLUP_END,
80
+
81
+
PINMUX_OUTPUT_BEGIN,
82
+
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
83
+
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
84
+
PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
85
+
PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
86
+
PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
87
+
PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
88
+
PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
89
+
PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
90
+
PE7_OUT, PE6_OUT,
91
+
PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
92
+
PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
93
+
PG7_OUT, PG6_OUT, PG5_OUT,
94
+
PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
95
+
PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96
+
PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
97
+
PJ3_OUT, PJ2_OUT, PJ1_OUT,
98
+
PINMUX_OUTPUT_END,
99
+
100
+
PINMUX_FUNCTION_BEGIN,
101
+
PA7_FN, PA6_FN, PA5_FN, PA4_FN,
102
+
PA3_FN, PA2_FN, PA1_FN, PA0_FN,
103
+
PB7_FN, PB6_FN, PB5_FN, PB4_FN,
104
+
PB3_FN, PB2_FN, PB1_FN, PB0_FN,
105
+
PC7_FN, PC6_FN, PC5_FN, PC4_FN,
106
+
PC3_FN, PC2_FN, PC1_FN, PC0_FN,
107
+
PD7_FN, PD6_FN, PD5_FN, PD4_FN,
108
+
PD3_FN, PD2_FN, PD1_FN, PD0_FN,
109
+
PE7_FN, PE6_FN,
110
+
PF7_FN, PF6_FN, PF5_FN, PF4_FN,
111
+
PF3_FN, PF2_FN, PF1_FN, PF0_FN,
112
+
PG7_FN, PG6_FN, PG5_FN,
113
+
PH7_FN, PH6_FN, PH5_FN, PH4_FN,
114
+
PH3_FN, PH2_FN, PH1_FN, PH0_FN,
115
+
PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
116
+
PJ3_FN, PJ2_FN, PJ1_FN,
117
+
P1MSEL14_0, P1MSEL14_1,
118
+
P1MSEL13_0, P1MSEL13_1,
119
+
P1MSEL12_0, P1MSEL12_1,
120
+
P1MSEL11_0, P1MSEL11_1,
121
+
P1MSEL10_0, P1MSEL10_1,
122
+
P1MSEL9_0, P1MSEL9_1,
123
+
P1MSEL8_0, P1MSEL8_1,
124
+
P1MSEL7_0, P1MSEL7_1,
125
+
P1MSEL6_0, P1MSEL6_1,
126
+
P1MSEL5_0, P1MSEL5_1,
127
+
P1MSEL4_0, P1MSEL4_1,
128
+
P1MSEL3_0, P1MSEL3_1,
129
+
P1MSEL2_0, P1MSEL2_1,
130
+
P1MSEL1_0, P1MSEL1_1,
131
+
P1MSEL0_0, P1MSEL0_1,
132
+
133
+
P2MSEL15_0, P2MSEL15_1,
134
+
P2MSEL14_0, P2MSEL14_1,
135
+
P2MSEL13_0, P2MSEL13_1,
136
+
P2MSEL12_0, P2MSEL12_1,
137
+
P2MSEL11_0, P2MSEL11_1,
138
+
P2MSEL10_0, P2MSEL10_1,
139
+
P2MSEL9_0, P2MSEL9_1,
140
+
P2MSEL8_0, P2MSEL8_1,
141
+
P2MSEL7_0, P2MSEL7_1,
142
+
P2MSEL6_0, P2MSEL6_1,
143
+
P2MSEL5_0, P2MSEL5_1,
144
+
P2MSEL4_0, P2MSEL4_1,
145
+
P2MSEL3_0, P2MSEL3_1,
146
+
P2MSEL2_0, P2MSEL2_1,
147
+
P2MSEL1_0, P2MSEL1_1,
148
+
P2MSEL0_0, P2MSEL0_1,
149
+
PINMUX_FUNCTION_END,
150
+
151
+
PINMUX_MARK_BEGIN,
152
+
CDE_MARK,
153
+
ETH_MAGIC_MARK,
154
+
DISP_MARK,
155
+
ETH_LINK_MARK,
156
+
DR5_MARK,
157
+
ETH_TX_ER_MARK,
158
+
DR4_MARK,
159
+
ETH_TX_EN_MARK,
160
+
DR3_MARK,
161
+
ETH_TXD3_MARK,
162
+
DR2_MARK,
163
+
ETH_TXD2_MARK,
164
+
DR1_MARK,
165
+
ETH_TXD1_MARK,
166
+
DR0_MARK,
167
+
ETH_TXD0_MARK,
168
+
169
+
VSYNC_MARK,
170
+
HSPI_CLK_MARK,
171
+
ODDF_MARK,
172
+
HSPI_CS_MARK,
173
+
DG5_MARK,
174
+
ETH_MDIO_MARK,
175
+
DG4_MARK,
176
+
ETH_RX_CLK_MARK,
177
+
DG3_MARK,
178
+
ETH_MDC_MARK,
179
+
DG2_MARK,
180
+
ETH_COL_MARK,
181
+
DG1_MARK,
182
+
ETH_TX_CLK_MARK,
183
+
DG0_MARK,
184
+
ETH_CRS_MARK,
185
+
186
+
DCLKIN_MARK,
187
+
HSPI_RX_MARK,
188
+
HSYNC_MARK,
189
+
HSPI_TX_MARK,
190
+
DB5_MARK,
191
+
ETH_RXD3_MARK,
192
+
DB4_MARK,
193
+
ETH_RXD2_MARK,
194
+
DB3_MARK,
195
+
ETH_RXD1_MARK,
196
+
DB2_MARK,
197
+
ETH_RXD0_MARK,
198
+
DB1_MARK,
199
+
ETH_RX_DV_MARK,
200
+
DB0_MARK,
201
+
ETH_RX_ER_MARK,
202
+
203
+
DCLKOUT_MARK,
204
+
SCIF1_SLK_MARK,
205
+
SCIF1_RXD_MARK,
206
+
SCIF1_TXD_MARK,
207
+
DACK1_MARK,
208
+
BACK_MARK,
209
+
FALE_MARK,
210
+
DACK0_MARK,
211
+
FCLE_MARK,
212
+
DREQ1_MARK,
213
+
BREQ_MARK,
214
+
USB_OVC1_MARK,
215
+
DREQ0_MARK,
216
+
USB_OVC0_MARK,
217
+
218
+
USB_PENC1_MARK,
219
+
USB_PENC0_MARK,
220
+
221
+
HAC1_SDOUT_MARK,
222
+
SSI1_SDATA_MARK,
223
+
SDIF1CMD_MARK,
224
+
HAC1_SDIN_MARK,
225
+
SSI1_SCK_MARK,
226
+
SDIF1CD_MARK,
227
+
HAC1_SYNC_MARK,
228
+
SSI1_WS_MARK,
229
+
SDIF1WP_MARK,
230
+
HAC1_BITCLK_MARK,
231
+
SSI1_CLK_MARK,
232
+
SDIF1CLK_MARK,
233
+
HAC0_SDOUT_MARK,
234
+
SSI0_SDATA_MARK,
235
+
SDIF1D3_MARK,
236
+
HAC0_SDIN_MARK,
237
+
SSI0_SCK_MARK,
238
+
SDIF1D2_MARK,
239
+
HAC0_SYNC_MARK,
240
+
SSI0_WS_MARK,
241
+
SDIF1D1_MARK,
242
+
HAC0_BITCLK_MARK,
243
+
SSI0_CLK_MARK,
244
+
SDIF1D0_MARK,
245
+
246
+
SCIF3_SCK_MARK,
247
+
SSI2_SDATA_MARK,
248
+
SCIF3_RXD_MARK,
249
+
TCLK_MARK,
250
+
SSI2_SCK_MARK,
251
+
SCIF3_TXD_MARK,
252
+
HAC_RES_MARK,
253
+
SSI2_WS_MARK,
254
+
255
+
DACK3_MARK,
256
+
SDIF0CMD_MARK,
257
+
DACK2_MARK,
258
+
SDIF0CD_MARK,
259
+
DREQ3_MARK,
260
+
SDIF0WP_MARK,
261
+
SCIF0_CTS_MARK,
262
+
DREQ2_MARK,
263
+
SDIF0CLK_MARK,
264
+
SCIF0_RTS_MARK,
265
+
IRL7_MARK,
266
+
SDIF0D3_MARK,
267
+
SCIF0_SCK_MARK,
268
+
IRL6_MARK,
269
+
SDIF0D2_MARK,
270
+
SCIF0_RXD_MARK,
271
+
IRL5_MARK,
272
+
SDIF0D1_MARK,
273
+
SCIF0_TXD_MARK,
274
+
IRL4_MARK,
275
+
SDIF0D0_MARK,
276
+
277
+
SCIF5_SCK_MARK,
278
+
FRB_MARK,
279
+
SCIF5_RXD_MARK,
280
+
IOIS16_MARK,
281
+
SCIF5_TXD_MARK,
282
+
CE2B_MARK,
283
+
DRAK3_MARK,
284
+
CE2A_MARK,
285
+
SCIF4_SCK_MARK,
286
+
DRAK2_MARK,
287
+
SSI3_WS_MARK,
288
+
SCIF4_RXD_MARK,
289
+
DRAK1_MARK,
290
+
SSI3_SDATA_MARK,
291
+
FSTATUS_MARK,
292
+
SCIF4_TXD_MARK,
293
+
DRAK0_MARK,
294
+
SSI3_SCK_MARK,
295
+
FSE_MARK,
296
+
PINMUX_MARK_END,
297
+
};
298
+
299
+
static pinmux_enum_t pinmux_data[] = {
300
+
301
+
/* PA GPIO */
302
+
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
303
+
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
304
+
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
305
+
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
306
+
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
307
+
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
308
+
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
309
+
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
310
+
311
+
/* PB GPIO */
312
+
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
313
+
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
314
+
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
315
+
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
316
+
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
317
+
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
318
+
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
319
+
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
320
+
321
+
/* PC GPIO */
322
+
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
323
+
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
324
+
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
325
+
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
326
+
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
327
+
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
328
+
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
329
+
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
330
+
331
+
/* PD GPIO */
332
+
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
333
+
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
334
+
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
335
+
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
336
+
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
337
+
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
338
+
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
339
+
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
340
+
341
+
/* PE GPIO */
342
+
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
343
+
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
344
+
345
+
/* PF GPIO */
346
+
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
347
+
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
348
+
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
349
+
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
350
+
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
351
+
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
352
+
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
353
+
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
354
+
355
+
/* PG GPIO */
356
+
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
357
+
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
358
+
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
359
+
360
+
/* PH GPIO */
361
+
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
362
+
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
363
+
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
364
+
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
365
+
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
366
+
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
367
+
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
368
+
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
369
+
370
+
/* PJ GPIO */
371
+
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
372
+
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
373
+
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
374
+
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
375
+
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
376
+
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
377
+
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
378
+
379
+
/* PA FN */
380
+
PINMUX_MARK_BEGIN,
381
+
PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
382
+
PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
383
+
PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
384
+
PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
385
+
PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
386
+
PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
387
+
PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
388
+
PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
389
+
PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
390
+
PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
391
+
PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
392
+
PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
393
+
PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
394
+
PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
395
+
PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
396
+
PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
397
+
398
+
/* PB FN */
399
+
PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
400
+
PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
401
+
PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
402
+
PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
403
+
PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
404
+
PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
405
+
PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
406
+
PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
407
+
PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
408
+
PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
409
+
PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
410
+
PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
411
+
PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
412
+
PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
413
+
PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
414
+
PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
415
+
416
+
/* PC FN */
417
+
PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
418
+
PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
419
+
PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
420
+
PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
421
+
PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
422
+
PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
423
+
PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
424
+
PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
425
+
426
+
PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
427
+
PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
428
+
PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
429
+
PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
430
+
PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
431
+
PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
432
+
PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
433
+
PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
434
+
435
+
/* PD FN */
436
+
PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
437
+
PINMUX_DATA(SCIF1_SLK_MARK, PD6_FN),
438
+
PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
439
+
PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
440
+
PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
441
+
PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
442
+
PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
443
+
PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
444
+
PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
445
+
PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
446
+
PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
447
+
PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
448
+
PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
449
+
PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
450
+
451
+
/* PE FN */
452
+
PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
453
+
PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
454
+
455
+
/* PF FN */
456
+
PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
457
+
PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
458
+
PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
459
+
PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
460
+
PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
461
+
PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
462
+
PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
463
+
PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
464
+
PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
465
+
PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
466
+
PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
467
+
PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
468
+
PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
469
+
PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
470
+
PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
471
+
PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
472
+
PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
473
+
PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
474
+
PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
475
+
PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
476
+
PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
477
+
PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
478
+
PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
479
+
PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
480
+
481
+
/* PG FN */
482
+
PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
483
+
PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
484
+
PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
485
+
PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
486
+
PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
487
+
PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
488
+
PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
489
+
PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
490
+
491
+
/* PH FN */
492
+
PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
493
+
PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
494
+
PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
495
+
PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
496
+
PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
497
+
PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
498
+
PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
499
+
PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
500
+
PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
501
+
PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
502
+
PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
503
+
PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
504
+
PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
505
+
PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
506
+
PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
507
+
PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
508
+
PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
509
+
PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
510
+
PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
511
+
PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
512
+
PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
513
+
514
+
/* PJ FN */
515
+
PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
516
+
PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
517
+
PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
518
+
PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
519
+
PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
520
+
PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
521
+
PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
522
+
PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
523
+
PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
524
+
PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
525
+
PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
526
+
PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
527
+
PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
528
+
PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
529
+
PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
530
+
PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
531
+
PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
532
+
PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
533
+
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
534
+
};
535
+
536
+
static struct pinmux_gpio pinmux_gpios[] = {
537
+
/* PA */
538
+
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
539
+
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
540
+
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
541
+
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
542
+
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
543
+
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
544
+
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
545
+
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
546
+
547
+
/* PB */
548
+
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
549
+
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
550
+
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
551
+
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
552
+
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
553
+
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
554
+
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
555
+
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
556
+
557
+
/* PC */
558
+
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
559
+
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
560
+
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
561
+
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
562
+
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
563
+
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
564
+
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
565
+
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
566
+
567
+
/* PD */
568
+
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
569
+
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
570
+
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
571
+
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
572
+
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
573
+
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
574
+
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
575
+
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
576
+
577
+
/* PE */
578
+
PINMUX_GPIO(GPIO_PE5, PE7_DATA),
579
+
PINMUX_GPIO(GPIO_PE4, PE6_DATA),
580
+
581
+
/* PF */
582
+
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
583
+
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
584
+
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
585
+
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
586
+
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
587
+
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
588
+
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
589
+
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
590
+
591
+
/* PG */
592
+
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
593
+
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
594
+
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
595
+
596
+
/* PH */
597
+
PINMUX_GPIO(GPIO_PH7, PH7_DATA),
598
+
PINMUX_GPIO(GPIO_PH6, PH6_DATA),
599
+
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
600
+
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
601
+
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
602
+
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
603
+
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
604
+
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
605
+
606
+
/* PJ */
607
+
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
608
+
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
609
+
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
610
+
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
611
+
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
612
+
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
613
+
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
614
+
615
+
/* FN */
616
+
PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
617
+
PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
618
+
PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
619
+
PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
620
+
PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
621
+
PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
622
+
PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
623
+
PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
624
+
PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
625
+
PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
626
+
PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
627
+
PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
628
+
PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
629
+
PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
630
+
PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
631
+
PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
632
+
PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
633
+
PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
634
+
PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
635
+
PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
636
+
PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
637
+
PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
638
+
PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
639
+
PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
640
+
PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
641
+
PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
642
+
PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
643
+
PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
644
+
PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
645
+
PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
646
+
PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
647
+
PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
648
+
PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
649
+
PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
650
+
PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
651
+
PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
652
+
PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
653
+
PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
654
+
PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
655
+
PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
656
+
PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
657
+
PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
658
+
PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
659
+
PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
660
+
PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
661
+
PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
662
+
PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
663
+
PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
664
+
PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
665
+
PINMUX_GPIO(GPIO_FN_SCIF1_SLK, SCIF1_SLK_MARK),
666
+
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
667
+
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
668
+
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
669
+
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
670
+
PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
671
+
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
672
+
PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
673
+
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
674
+
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
675
+
PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
676
+
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
677
+
PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
678
+
PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
679
+
PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
680
+
PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
681
+
PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
682
+
PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
683
+
PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
684
+
PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
685
+
PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
686
+
PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
687
+
PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
688
+
PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
689
+
PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
690
+
PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
691
+
PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
692
+
PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
693
+
PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
694
+
PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
695
+
PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
696
+
PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
697
+
PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
698
+
PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
699
+
PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
700
+
PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
701
+
PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
702
+
PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
703
+
PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
704
+
PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
705
+
PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
706
+
PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
707
+
PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
708
+
PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
709
+
PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
710
+
PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
711
+
PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
712
+
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
713
+
PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
714
+
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
715
+
PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
716
+
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
717
+
PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
718
+
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
719
+
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
720
+
PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
721
+
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
722
+
PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
723
+
PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
724
+
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
725
+
PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
726
+
PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
727
+
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
728
+
PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
729
+
PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
730
+
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
731
+
PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
732
+
PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
733
+
PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
734
+
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
735
+
PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
736
+
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
737
+
PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
738
+
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
739
+
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
740
+
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
741
+
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
742
+
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
743
+
PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
744
+
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
745
+
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
746
+
PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
747
+
PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
748
+
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
749
+
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
750
+
PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
751
+
PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
752
+
};
753
+
754
+
static struct pinmux_cfg_reg pinmux_config_regs[] = {
755
+
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
756
+
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
757
+
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
758
+
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
759
+
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
760
+
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
761
+
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
762
+
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
763
+
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
764
+
},
765
+
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
766
+
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
767
+
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
768
+
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
769
+
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
770
+
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
771
+
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
772
+
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
773
+
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
774
+
},
775
+
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
776
+
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
777
+
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
778
+
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
779
+
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
780
+
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
781
+
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
782
+
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
783
+
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
784
+
},
785
+
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
786
+
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
787
+
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
788
+
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
789
+
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
790
+
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
791
+
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
792
+
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
793
+
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
794
+
},
795
+
{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
796
+
PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
797
+
PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
798
+
0, 0, 0, 0,
799
+
0, 0, 0, 0,
800
+
0, 0, 0, 0,
801
+
0, 0, 0, 0,
802
+
0, 0, 0, 0,
803
+
0, 0, 0, 0, }
804
+
},
805
+
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
806
+
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
807
+
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
808
+
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
809
+
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
810
+
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
811
+
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
812
+
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
813
+
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
814
+
},
815
+
{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
816
+
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
817
+
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
818
+
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
819
+
0, 0, 0, 0,
820
+
0, 0, 0, 0,
821
+
0, 0, 0, 0,
822
+
0, 0, 0, 0,
823
+
0, 0, 0, 0, }
824
+
},
825
+
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
826
+
PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
827
+
PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
828
+
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
829
+
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
830
+
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
831
+
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
832
+
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
833
+
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
834
+
},
835
+
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
836
+
PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
837
+
PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
838
+
PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
839
+
PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
840
+
PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
841
+
PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
842
+
PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
843
+
0, 0, 0, 0, }
844
+
},
845
+
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
846
+
0, 0,
847
+
P1MSEL14_0, P1MSEL14_1,
848
+
P1MSEL13_0, P1MSEL13_1,
849
+
P1MSEL12_0, P1MSEL12_1,
850
+
P1MSEL11_0, P1MSEL11_1,
851
+
P1MSEL10_0, P1MSEL10_1,
852
+
P1MSEL9_0, P1MSEL9_1,
853
+
P1MSEL8_0, P1MSEL8_1,
854
+
P1MSEL7_0, P1MSEL7_1,
855
+
P1MSEL6_0, P1MSEL6_1,
856
+
P1MSEL5_0, P1MSEL5_1,
857
+
P1MSEL4_0, P1MSEL4_1,
858
+
P1MSEL3_0, P1MSEL3_1,
859
+
P1MSEL2_0, P1MSEL2_1,
860
+
P1MSEL1_0, P1MSEL1_1,
861
+
P1MSEL0_0, P1MSEL0_1 }
862
+
},
863
+
{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
864
+
P2MSEL15_0, P2MSEL15_1,
865
+
P2MSEL14_0, P2MSEL14_1,
866
+
P2MSEL13_0, P2MSEL13_1,
867
+
P2MSEL12_0, P2MSEL12_1,
868
+
P2MSEL11_0, P2MSEL11_1,
869
+
P2MSEL10_0, P2MSEL10_1,
870
+
P2MSEL9_0, P2MSEL9_1,
871
+
P2MSEL8_0, P2MSEL8_1,
872
+
P2MSEL7_0, P2MSEL7_1,
873
+
P2MSEL6_0, P2MSEL6_1,
874
+
P2MSEL5_0, P2MSEL5_1,
875
+
P2MSEL4_0, P2MSEL4_1,
876
+
P2MSEL3_0, P2MSEL3_1,
877
+
P2MSEL2_0, P2MSEL2_1,
878
+
P2MSEL1_0, P2MSEL1_1,
879
+
P2MSEL0_0, P2MSEL0_1 }
880
+
},
881
+
{}
882
+
};
883
+
884
+
static struct pinmux_data_reg pinmux_data_regs[] = {
885
+
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
886
+
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
887
+
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
888
+
},
889
+
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
890
+
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
891
+
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
892
+
},
893
+
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
894
+
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
895
+
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
896
+
},
897
+
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
898
+
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
899
+
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
900
+
},
901
+
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
902
+
PE7_DATA, PE6_DATA,
903
+
0, 0, 0, 0, 0, 0 }
904
+
},
905
+
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
906
+
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
907
+
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
908
+
},
909
+
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
910
+
PG7_DATA, PG6_DATA, PG5_DATA, 0,
911
+
0, 0, 0, 0 }
912
+
},
913
+
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
914
+
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
915
+
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
916
+
},
917
+
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
918
+
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
919
+
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
920
+
},
921
+
{ },
922
+
};
923
+
924
+
static struct pinmux_info sh7786_pinmux_info = {
925
+
.name = "sh7786_pfc",
926
+
.reserved_id = PINMUX_RESERVED,
927
+
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
928
+
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
929
+
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
930
+
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
931
+
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
932
+
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
933
+
934
+
.first_gpio = GPIO_PA7,
935
+
.last_gpio = GPIO_FN_FSE,
936
+
937
+
.gpios = pinmux_gpios,
938
+
.cfg_regs = pinmux_config_regs,
939
+
.data_regs = pinmux_data_regs,
940
+
941
+
.gpio_data = pinmux_data,
942
+
.gpio_data_size = ARRAY_SIZE(pinmux_data),
943
+
};
944
+
945
+
static int __init plat_pinmux_setup(void)
946
+
{
947
+
return register_pinmux(&sh7786_pinmux_info);
948
+
}
949
+
950
+
arch_initcall(plat_pinmux_setup);
+407
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+407
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
···
1
+
/*
2
+
* SH7786 Setup
3
+
*
4
+
* Copyright (C) 2009 Renesas Solutions Corp.
5
+
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
6
+
*
7
+
* Based on SH7785 Setup
8
+
*
9
+
* Copyright (C) 2007 Paul Mundt
10
+
*
11
+
* This file is subject to the terms and conditions of the GNU General Public
12
+
* License. See the file "COPYING" in the main directory of this archive
13
+
* for more details.
14
+
*/
15
+
#include <linux/platform_device.h>
16
+
#include <linux/init.h>
17
+
#include <linux/serial.h>
18
+
#include <linux/serial_sci.h>
19
+
#include <linux/io.h>
20
+
#include <linux/mm.h>
21
+
#include <asm/mmzone.h>
22
+
23
+
static struct plat_sci_port sci_platform_data[] = {
24
+
{
25
+
.mapbase = 0xffea0000,
26
+
.flags = UPF_BOOT_AUTOCONF,
27
+
.type = PORT_SCIF,
28
+
.irqs = { 40, 41, 43, 42 },
29
+
},
30
+
/*
31
+
* The rest of these all have multiplexed IRQs
32
+
*/
33
+
{
34
+
.mapbase = 0xffeb0000,
35
+
.flags = UPF_BOOT_AUTOCONF,
36
+
.type = PORT_SCIF,
37
+
.irqs = { 44, 44, 44, 44 },
38
+
}, {
39
+
.mapbase = 0xffec0000,
40
+
.flags = UPF_BOOT_AUTOCONF,
41
+
.type = PORT_SCIF,
42
+
.irqs = { 50, 50, 50, 50 },
43
+
}, {
44
+
.mapbase = 0xffed0000,
45
+
.flags = UPF_BOOT_AUTOCONF,
46
+
.type = PORT_SCIF,
47
+
.irqs = { 51, 51, 51, 51 },
48
+
}, {
49
+
.mapbase = 0xffee0000,
50
+
.flags = UPF_BOOT_AUTOCONF,
51
+
.type = PORT_SCIF,
52
+
.irqs = { 52, 52, 52, 52 },
53
+
}, {
54
+
.mapbase = 0xffef0000,
55
+
.flags = UPF_BOOT_AUTOCONF,
56
+
.type = PORT_SCIF,
57
+
.irqs = { 53, 53, 53, 53 },
58
+
}, {
59
+
.flags = 0,
60
+
}
61
+
};
62
+
63
+
static struct platform_device sci_device = {
64
+
.name = "sh-sci",
65
+
.id = -1,
66
+
.dev = {
67
+
.platform_data = sci_platform_data,
68
+
},
69
+
};
70
+
71
+
static struct platform_device *sh7786_devices[] __initdata = {
72
+
&sci_device,
73
+
};
74
+
75
+
static int __init sh7786_devices_setup(void)
76
+
{
77
+
return platform_add_devices(sh7786_devices,
78
+
ARRAY_SIZE(sh7786_devices));
79
+
}
80
+
device_initcall(sh7786_devices_setup);
81
+
82
+
enum {
83
+
UNUSED = 0,
84
+
85
+
/* interrupt sources */
86
+
87
+
IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
88
+
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
89
+
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
90
+
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
91
+
92
+
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
93
+
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
94
+
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
95
+
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
96
+
97
+
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
98
+
WDT,
99
+
TMU0_0, TMU0_1, TMU0_2, TMU0_3,
100
+
TMU1_0, TMU1_1, TMU1_2,
101
+
DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
102
+
HUDI1, HUDI0,
103
+
DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
104
+
HPB_0, HPB_1, HPB_2,
105
+
SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
106
+
SCIF1,
107
+
TMU2, TMU3,
108
+
SCIF2, SCIF3, SCIF4, SCIF5,
109
+
Eth_0, Eth_1,
110
+
PCIeC0_0, PCIeC0_1, PCIeC0_2,
111
+
PCIeC1_0, PCIeC1_1, PCIeC1_2,
112
+
USB,
113
+
I2C0, I2C1,
114
+
DU,
115
+
SSI0, SSI1, SSI2, SSI3,
116
+
PCIeC2_0, PCIeC2_1, PCIeC2_2,
117
+
HAC0, HAC1,
118
+
FLCTL,
119
+
HSPI,
120
+
GPIO0, GPIO1,
121
+
Thermal,
122
+
INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
123
+
124
+
/* interrupt groups */
125
+
};
126
+
127
+
static struct intc_vect vectors[] __initdata = {
128
+
INTC_VECT(WDT, 0x3e0),
129
+
INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
130
+
INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
131
+
INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
132
+
INTC_VECT(TMU1_2, 0x4c0),
133
+
INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
134
+
INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
135
+
INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
136
+
INTC_VECT(DMAC0_6, 0x5c0),
137
+
INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
138
+
INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
139
+
INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
140
+
INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
141
+
INTC_VECT(HPB_2, 0x6e0),
142
+
INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
143
+
INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
144
+
INTC_VECT(SCIF1, 0x780),
145
+
INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
146
+
INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
147
+
INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
148
+
INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
149
+
INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
150
+
INTC_VECT(PCIeC0_2, 0xb20),
151
+
INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
152
+
INTC_VECT(PCIeC1_2, 0xb80),
153
+
INTC_VECT(USB, 0xba0),
154
+
INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
155
+
INTC_VECT(DU, 0xd00),
156
+
INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
157
+
INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
158
+
INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
159
+
INTC_VECT(PCIeC2_2, 0xde0),
160
+
INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
161
+
INTC_VECT(FLCTL, 0xe40),
162
+
INTC_VECT(HSPI, 0xe80),
163
+
INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
164
+
INTC_VECT(Thermal, 0xee0),
165
+
};
166
+
167
+
/* FIXME: Main CPU support only now */
168
+
#if 1 /* Main CPU */
169
+
#define CnINTMSK0 0xfe410030
170
+
#define CnINTMSK1 0xfe410040
171
+
#define CnINTMSKCLR0 0xfe410050
172
+
#define CnINTMSKCLR1 0xfe410060
173
+
#define CnINT2MSKR0 0xfe410a20
174
+
#define CnINT2MSKR1 0xfe410a24
175
+
#define CnINT2MSKR2 0xfe410a28
176
+
#define CnINT2MSKR3 0xfe410a2c
177
+
#define CnINT2MSKCR0 0xfe410a30
178
+
#define CnINT2MSKCR1 0xfe410a34
179
+
#define CnINT2MSKCR2 0xfe410a38
180
+
#define CnINT2MSKCR3 0xfe410a3c
181
+
#else /* Sub CPU */
182
+
#define CnINTMSK0 0xfe410034
183
+
#define CnINTMSK1 0xfe410044
184
+
#define CnINTMSKCLR0 0xfe410054
185
+
#define CnINTMSKCLR1 0xfe410064
186
+
#define CnINT2MSKR0 0xfe410b20
187
+
#define CnINT2MSKR1 0xfe410b24
188
+
#define CnINT2MSKR2 0xfe410b28
189
+
#define CnINT2MSKR3 0xfe410b2c
190
+
#define CnINT2MSKCR0 0xfe410b30
191
+
#define CnINT2MSKCR1 0xfe410b34
192
+
#define CnINT2MSKCR2 0xfe410b38
193
+
#define CnINT2MSKCR3 0xfe410b3c
194
+
#endif
195
+
196
+
#define INTMSK2 0xfe410068
197
+
#define INTMSKCLR2 0xfe41006c
198
+
199
+
static struct intc_mask_reg mask_registers[] __initdata = {
200
+
{ CnINTMSK0, CnINTMSKCLR0, 32,
201
+
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
202
+
{ INTMSK2, INTMSKCLR2, 32,
203
+
{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
204
+
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
205
+
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
206
+
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
207
+
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
208
+
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
209
+
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
210
+
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
211
+
{ CnINT2MSKR0, CnINT2MSKCR0 , 32,
212
+
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
213
+
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
214
+
{ CnINT2MSKR1, CnINT2MSKCR1, 32,
215
+
{ TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
216
+
DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
217
+
HUDI1, HUDI0,
218
+
DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
219
+
HPB_0, HPB_1, HPB_2,
220
+
SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
221
+
SCIF1,
222
+
TMU2, TMU3, 0, } },
223
+
{ CnINT2MSKR2, CnINT2MSKCR2, 32,
224
+
{ 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
225
+
Eth_0, Eth_1,
226
+
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
227
+
PCIeC0_0, PCIeC0_1, PCIeC0_2,
228
+
PCIeC1_0, PCIeC1_1, PCIeC1_2,
229
+
USB, 0, 0 } },
230
+
{ CnINT2MSKR3, CnINT2MSKCR3, 32,
231
+
{ 0, 0, 0, 0, 0, 0,
232
+
I2C0, I2C1,
233
+
DU, SSI0, SSI1, SSI2, SSI3,
234
+
PCIeC2_0, PCIeC2_1, PCIeC2_2,
235
+
HAC0, HAC1,
236
+
FLCTL, 0,
237
+
HSPI, GPIO0, GPIO1, Thermal,
238
+
0, 0, 0, 0, 0, 0, 0, 0 } },
239
+
};
240
+
241
+
static struct intc_prio_reg prio_registers[] __initdata = {
242
+
{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
243
+
IRQ4, IRQ5, IRQ6, IRQ7 } },
244
+
{ 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
245
+
{ 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
246
+
TMU0_2, TMU0_3 } },
247
+
{ 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
248
+
TMU1_2, 0 } },
249
+
{ 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
250
+
DMAC0_2, DMAC0_3 } },
251
+
{ 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
252
+
DMAC0_6, HUDI1 } },
253
+
{ 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
254
+
DMAC1_1, DMAC1_2 } },
255
+
{ 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
256
+
HPB_1, HPB_2 } },
257
+
{ 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
258
+
SCIF0_2, SCIF0_3 } },
259
+
{ 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
260
+
{ 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
261
+
{ 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
262
+
Eth_0, Eth_1 } },
263
+
{ 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
264
+
{ 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
265
+
{ 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
266
+
{ 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
267
+
{ 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
268
+
PCIeC1_0, PCIeC1_1 } },
269
+
{ 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
270
+
{ 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
271
+
{ 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
272
+
{ 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
273
+
{ 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
274
+
PCIeC2_1, PCIeC2_2 } },
275
+
{ 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
276
+
{ 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
277
+
GPIO1, Thermal } },
278
+
{ 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
279
+
{ 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
280
+
};
281
+
282
+
static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
283
+
mask_registers, prio_registers, NULL);
284
+
285
+
/* Support for external interrupt pins in IRQ mode */
286
+
287
+
static struct intc_vect vectors_irq0123[] __initdata = {
288
+
INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
289
+
INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
290
+
};
291
+
292
+
static struct intc_vect vectors_irq4567[] __initdata = {
293
+
INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
294
+
INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
295
+
};
296
+
297
+
static struct intc_sense_reg sense_registers[] __initdata = {
298
+
{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
299
+
IRQ4, IRQ5, IRQ6, IRQ7 } },
300
+
};
301
+
302
+
static struct intc_mask_reg ack_registers[] __initdata = {
303
+
{ 0xfe410024, 0, 32, /* INTREQ */
304
+
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
305
+
};
306
+
307
+
static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
308
+
vectors_irq0123, NULL, mask_registers,
309
+
prio_registers, sense_registers, ack_registers);
310
+
311
+
static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
312
+
vectors_irq4567, NULL, mask_registers,
313
+
prio_registers, sense_registers, ack_registers);
314
+
315
+
/* External interrupt pins in IRL mode */
316
+
317
+
static struct intc_vect vectors_irl0123[] __initdata = {
318
+
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
319
+
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
320
+
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
321
+
INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
322
+
INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
323
+
INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
324
+
INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
325
+
INTC_VECT(IRL0_HHHL, 0x3c0),
326
+
};
327
+
328
+
static struct intc_vect vectors_irl4567[] __initdata = {
329
+
INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
330
+
INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
331
+
INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
332
+
INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
333
+
INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
334
+
INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
335
+
INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
336
+
INTC_VECT(IRL4_HHHL, 0xac0),
337
+
};
338
+
339
+
static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
340
+
NULL, mask_registers, NULL, NULL);
341
+
342
+
static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
343
+
NULL, mask_registers, NULL, NULL);
344
+
345
+
#define INTC_ICR0 0xfe410000
346
+
#define INTC_INTMSK0 CnINTMSK0
347
+
#define INTC_INTMSK1 CnINTMSK1
348
+
#define INTC_INTMSK2 INTMSK2
349
+
#define INTC_INTMSKCLR1 CnINTMSKCLR1
350
+
#define INTC_INTMSKCLR2 INTMSKCLR2
351
+
352
+
void __init plat_irq_setup(void)
353
+
{
354
+
/* disable IRQ3-0 + IRQ7-4 */
355
+
ctrl_outl(0xff000000, INTC_INTMSK0);
356
+
357
+
/* disable IRL3-0 + IRL7-4 */
358
+
ctrl_outl(0xc0000000, INTC_INTMSK1);
359
+
ctrl_outl(0xfffefffe, INTC_INTMSK2);
360
+
361
+
/* select IRL mode for IRL3-0 + IRL7-4 */
362
+
ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
363
+
364
+
register_intc_controller(&intc_desc);
365
+
}
366
+
367
+
void __init plat_irq_setup_pins(int mode)
368
+
{
369
+
switch (mode) {
370
+
case IRQ_MODE_IRQ7654:
371
+
/* select IRQ mode for IRL7-4 */
372
+
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
373
+
register_intc_controller(&intc_desc_irq4567);
374
+
break;
375
+
case IRQ_MODE_IRQ3210:
376
+
/* select IRQ mode for IRL3-0 */
377
+
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
378
+
register_intc_controller(&intc_desc_irq0123);
379
+
break;
380
+
case IRQ_MODE_IRL7654:
381
+
/* enable IRL7-4 but don't provide any masking */
382
+
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
383
+
ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
384
+
break;
385
+
case IRQ_MODE_IRL3210:
386
+
/* enable IRL0-3 but don't provide any masking */
387
+
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
388
+
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
389
+
break;
390
+
case IRQ_MODE_IRL7654_MASK:
391
+
/* enable IRL7-4 and mask using cpu intc controller */
392
+
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
393
+
register_intc_controller(&intc_desc_irl4567);
394
+
break;
395
+
case IRQ_MODE_IRL3210_MASK:
396
+
/* enable IRL0-3 and mask using cpu intc controller */
397
+
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
398
+
register_intc_controller(&intc_desc_irl0123);
399
+
break;
400
+
default:
401
+
BUG();
402
+
}
403
+
}
404
+
405
+
void __init plat_mem_setup(void)
406
+
{
407
+
}
+1
arch/sh/kernel/setup.c
+1
arch/sh/kernel/setup.c
···
432
432
[CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
433
433
[CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
434
434
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
435
+
[CPU_SH7786] = "SH7786",
435
436
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
436
437
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
437
438
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
+1
arch/sh/kernel/timers/timer-tmu.c
+1
arch/sh/kernel/timers/timer-tmu.c
+1
arch/sh/oprofile/common.c
+1
arch/sh/oprofile/common.c
+3
-1
drivers/serial/sh-sci.c
+3
-1
drivers/serial/sh-sci.c
···
263
263
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
264
264
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
265
265
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
266
+
defined(CONFIG_CPU_SUBTYPE_SH7786) || \
266
267
defined(CONFIG_CPU_SUBTYPE_SHX3)
267
268
static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
268
269
{
···
285
284
286
285
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
287
286
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
288
-
defined(CONFIG_CPU_SUBTYPE_SH7785)
287
+
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
288
+
defined(CONFIG_CPU_SUBTYPE_SH7786)
289
289
static inline int scif_txroom(struct uart_port *port)
290
290
{
291
291
return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
+9
-4
drivers/serial/sh-sci.h
+9
-4
drivers/serial/sh-sci.h
···
126
126
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
127
127
# define SCIF_ORER 0x0001 /* Overrun error bit */
128
128
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
129
-
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
129
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
130
+
defined(CONFIG_CPU_SUBTYPE_SH7786)
130
131
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
131
132
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
132
133
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
···
183
182
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
184
183
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
185
184
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
185
+
defined(CONFIG_CPU_SUBTYPE_SH7786) || \
186
186
defined(CONFIG_CPU_SUBTYPE_SHX3)
187
187
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
188
188
#else
···
415
413
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
416
414
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
417
415
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
418
-
defined(CONFIG_CPU_SUBTYPE_SH7785)
416
+
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
417
+
defined(CONFIG_CPU_SUBTYPE_SH7786)
419
418
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
420
419
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
421
420
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
···
647
644
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
648
645
return 1;
649
646
}
650
-
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
647
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
648
+
defined(CONFIG_CPU_SUBTYPE_SH7786)
651
649
static inline int sci_rxd_in(struct uart_port *port)
652
650
{
653
651
if (port->mapbase == 0xffea0000)
···
750
746
*/
751
747
752
748
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
753
-
defined(CONFIG_CPU_SUBTYPE_SH7785)
749
+
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
750
+
defined(CONFIG_CPU_SUBTYPE_SH7786)
754
751
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
755
752
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
756
753
defined(CONFIG_CPU_SUBTYPE_SH7720) || \