tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

General rockchip clock changes for 4.12. Contains some new clock-ids
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.

* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add pll_wait_lock for pll_enable
clk: rockchip: rename RK1108 to RV1108
dt-bindings: rk1108-cru: rename RK1108 to RV1108
clk: rockchip: mark some rk3368 core-clks as critical
clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
clk: rockchip: fix up rk3368 timer-ids
clk: rockchip: add rk3328 clk_mac2io_ext ID
clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399

Michael Turquette 55798360 0d4ae360

+276 -255
+6 -6
Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt
··· 1 - * Rockchip RK1108 Clock and Reset Unit 1 + * Rockchip RV1108 Clock and Reset Unit 2 2 3 - The RK1108 clock controller generates and supplies clock to various 3 + The RV1108 clock controller generates and supplies clock to various 4 4 controllers within the SoC and also implements a reset controller for SoC 5 5 peripherals. 6 6 7 7 Required Properties: 8 8 9 - - compatible: should be "rockchip,rk1108-cru" 9 + - compatible: should be "rockchip,rv1108-cru" 10 10 - reg: physical base address of the controller and length of memory mapped 11 11 region. 12 12 - #clock-cells: should be 1. ··· 19 19 20 20 Each clock is assigned an identifier and client nodes can use this identifier 21 21 to specify the clock which they consume. All available clocks are defined as 22 - preprocessor macros in the dt-bindings/clock/rk1108-cru.h headers and can be 22 + preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be 23 23 used in device tree sources. Similar macros exist for the reset sources in 24 24 these files. 25 25 ··· 38 38 Example: Clock controller node: 39 39 40 40 cru: cru@20200000 { 41 - compatible = "rockchip,rk1108-cru"; 41 + compatible = "rockchip,rv1108-cru"; 42 42 reg = <0x20200000 0x1000>; 43 43 rockchip,grf = <&grf>; 44 44 ··· 50 50 controller: 51 51 52 52 uart0: serial@10230000 { 53 - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; 53 + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 54 54 reg = <0x10230000 0x100>; 55 55 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 56 56 reg-shift = <2>;
+1 -1
arch/arm/boot/dts/rk1108.dtsi
··· 41 41 #include <dt-bindings/gpio/gpio.h> 42 42 #include <dt-bindings/interrupt-controller/irq.h> 43 43 #include <dt-bindings/interrupt-controller/arm-gic.h> 44 - #include <dt-bindings/clock/rk1108-cru.h> 44 + #include <dt-bindings/clock/rv1108-cru.h> 45 45 #include <dt-bindings/pinctrl/rockchip.h> 46 46 / { 47 47 #address-cells = <1>;
+1 -1
drivers/clk/rockchip/Makefile
··· 12 12 obj-y += clk-ddr.o 13 13 obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 14 14 15 - obj-y += clk-rk1108.o 15 + obj-y += clk-rv1108.o 16 16 obj-y += clk-rk3036.o 17 17 obj-y += clk-rk3188.o 18 18 obj-y += clk-rk3228.o
+3
drivers/clk/rockchip/clk-pll.c
··· 269 269 270 270 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), 271 271 pll->reg_base + RK3036_PLLCON(1)); 272 + rockchip_pll_wait_lock(pll); 272 273 273 274 return 0; 274 275 } ··· 502 501 503 502 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), 504 503 pll->reg_base + RK3066_PLLCON(3)); 504 + rockchip_pll_wait_lock(pll); 505 505 506 506 return 0; 507 507 } ··· 748 746 749 747 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), 750 748 pll->reg_base + RK3399_PLLCON(3)); 749 + rockchip_rk3399_pll_wait_lock(pll); 751 750 752 751 return 0; 753 752 }
+207 -207
drivers/clk/rockchip/clk-rk1108.c drivers/clk/rockchip/clk-rv1108.c
··· 18 18 #include <linux/of.h> 19 19 #include <linux/of_address.h> 20 20 #include <linux/syscore_ops.h> 21 - #include <dt-bindings/clock/rk1108-cru.h> 21 + #include <dt-bindings/clock/rv1108-cru.h> 22 22 #include "clk.h" 23 23 24 - #define RK1108_GRF_SOC_STATUS0 0x480 24 + #define RV1108_GRF_SOC_STATUS0 0x480 25 25 26 - enum rk1108_plls { 26 + enum rv1108_plls { 27 27 apll, dpll, gpll, 28 28 }; 29 29 30 - static struct rockchip_pll_rate_table rk1108_pll_rates[] = { 30 + static struct rockchip_pll_rate_table rv1108_pll_rates[] = { 31 31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 32 32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 33 33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), ··· 74 74 { /* sentinel */ }, 75 75 }; 76 76 77 - #define RK1108_DIV_CORE_MASK 0xf 78 - #define RK1108_DIV_CORE_SHIFT 4 77 + #define RV1108_DIV_CORE_MASK 0xf 78 + #define RV1108_DIV_CORE_SHIFT 4 79 79 80 - #define RK1108_CLKSEL0(_core_peri_div) \ 80 + #define RV1108_CLKSEL0(_core_peri_div) \ 81 81 { \ 82 - .reg = RK1108_CLKSEL_CON(1), \ 83 - .val = HIWORD_UPDATE(_core_peri_div, RK1108_DIV_CORE_MASK,\ 84 - RK1108_DIV_CORE_SHIFT) \ 82 + .reg = RV1108_CLKSEL_CON(1), \ 83 + .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\ 84 + RV1108_DIV_CORE_SHIFT) \ 85 85 } 86 86 87 - #define RK1108_CPUCLK_RATE(_prate, _core_peri_div) \ 87 + #define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \ 88 88 { \ 89 89 .prate = _prate, \ 90 90 .divs = { \ 91 - RK1108_CLKSEL0(_core_peri_div), \ 91 + RV1108_CLKSEL0(_core_peri_div), \ 92 92 }, \ 93 93 } 94 94 95 - static struct rockchip_cpuclk_rate_table rk1108_cpuclk_rates[] __initdata = { 96 - RK1108_CPUCLK_RATE(816000000, 4), 97 - RK1108_CPUCLK_RATE(600000000, 4), 98 - RK1108_CPUCLK_RATE(312000000, 4), 95 + static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { 96 + RV1108_CPUCLK_RATE(816000000, 4), 97 + RV1108_CPUCLK_RATE(600000000, 4), 98 + RV1108_CPUCLK_RATE(312000000, 4), 99 99 }; 100 100 101 - static const struct rockchip_cpuclk_reg_data rk1108_cpuclk_data = { 102 - .core_reg = RK1108_CLKSEL_CON(0), 101 + static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { 102 + .core_reg = RV1108_CLKSEL_CON(0), 103 103 .div_core_shift = 0, 104 104 .div_core_mask = 0x1f, 105 105 .mux_core_alt = 1, ··· 131 131 PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" }; 132 132 PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; 133 133 134 - static struct rockchip_pll_clock rk1108_pll_clks[] __initdata = { 135 - [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RK1108_PLL_CON(0), 136 - RK1108_PLL_CON(3), 8, 31, 0, rk1108_pll_rates), 137 - [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK1108_PLL_CON(8), 138 - RK1108_PLL_CON(11), 8, 31, 0, NULL), 139 - [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK1108_PLL_CON(16), 140 - RK1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk1108_pll_rates), 134 + static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { 135 + [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), 136 + RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates), 137 + [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), 138 + RV1108_PLL_CON(11), 8, 31, 0, NULL), 139 + [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), 140 + RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates), 141 141 }; 142 142 143 143 #define MFLAGS CLK_MUX_HIWORD_MASK ··· 145 145 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 146 146 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 147 147 148 - static struct rockchip_clk_branch rk1108_uart0_fracmux __initdata = 148 + static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata = 149 149 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 150 - RK1108_CLKSEL_CON(13), 8, 2, MFLAGS); 150 + RV1108_CLKSEL_CON(13), 8, 2, MFLAGS); 151 151 152 - static struct rockchip_clk_branch rk1108_uart1_fracmux __initdata = 152 + static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata = 153 153 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 154 - RK1108_CLKSEL_CON(14), 8, 2, MFLAGS); 154 + RV1108_CLKSEL_CON(14), 8, 2, MFLAGS); 155 155 156 - static struct rockchip_clk_branch rk1108_uart2_fracmux __initdata = 156 + static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata = 157 157 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 158 - RK1108_CLKSEL_CON(15), 8, 2, MFLAGS); 158 + RV1108_CLKSEL_CON(15), 8, 2, MFLAGS); 159 159 160 - static struct rockchip_clk_branch rk1108_i2s0_fracmux __initdata = 160 + static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata = 161 161 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, 162 - RK1108_CLKSEL_CON(5), 12, 2, MFLAGS); 162 + RV1108_CLKSEL_CON(5), 12, 2, MFLAGS); 163 163 164 - static struct rockchip_clk_branch rk1108_i2s1_fracmux __initdata = 164 + static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata = 165 165 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, 166 - RK1108_CLKSEL_CON(6), 12, 2, MFLAGS); 166 + RV1108_CLKSEL_CON(6), 12, 2, MFLAGS); 167 167 168 - static struct rockchip_clk_branch rk1108_i2s2_fracmux __initdata = 168 + static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata = 169 169 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, 170 - RK1108_CLKSEL_CON(7), 12, 2, MFLAGS); 170 + RV1108_CLKSEL_CON(7), 12, 2, MFLAGS); 171 171 172 - static struct rockchip_clk_branch rk1108_clk_branches[] __initdata = { 172 + static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { 173 173 MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, 174 - RK1108_MISC_CON, 13, 2, MFLAGS), 174 + RV1108_MISC_CON, 13, 2, MFLAGS), 175 175 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, 176 - RK1108_MISC_CON, 15, 2, MFLAGS), 176 + RV1108_MISC_CON, 15, 2, MFLAGS), 177 177 /* 178 178 * Clock-Architecture Diagram 2 179 179 */ 180 180 181 181 /* PD_CORE */ 182 182 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, 183 - RK1108_CLKGATE_CON(0), 1, GFLAGS), 183 + RV1108_CLKGATE_CON(0), 1, GFLAGS), 184 184 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 185 - RK1108_CLKGATE_CON(0), 0, GFLAGS), 185 + RV1108_CLKGATE_CON(0), 0, GFLAGS), 186 186 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 187 - RK1108_CLKGATE_CON(0), 2, GFLAGS), 187 + RV1108_CLKGATE_CON(0), 2, GFLAGS), 188 188 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED, 189 - RK1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 190 - RK1108_CLKGATE_CON(0), 5, GFLAGS), 189 + RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 190 + RV1108_CLKGATE_CON(0), 5, GFLAGS), 191 191 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED, 192 - RK1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 193 - RK1108_CLKGATE_CON(0), 4, GFLAGS), 192 + RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 193 + RV1108_CLKGATE_CON(0), 4, GFLAGS), 194 194 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED, 195 - RK1108_CLKGATE_CON(11), 0, GFLAGS), 195 + RV1108_CLKGATE_CON(11), 0, GFLAGS), 196 196 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED, 197 - RK1108_CLKGATE_CON(11), 1, GFLAGS), 197 + RV1108_CLKGATE_CON(11), 1, GFLAGS), 198 198 199 199 /* PD_RKVENC */ 200 200 ··· 202 202 203 203 /* PD_PMU_wrapper */ 204 204 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, 205 - RK1108_CLKSEL_CON(38), 0, 5, DFLAGS, 206 - RK1108_CLKGATE_CON(8), 12, GFLAGS), 205 + RV1108_CLKSEL_CON(38), 0, 5, DFLAGS, 206 + RV1108_CLKGATE_CON(8), 12, GFLAGS), 207 207 GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 208 - RK1108_CLKGATE_CON(10), 0, GFLAGS), 208 + RV1108_CLKGATE_CON(10), 0, GFLAGS), 209 209 GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, 210 - RK1108_CLKGATE_CON(10), 1, GFLAGS), 210 + RV1108_CLKGATE_CON(10), 1, GFLAGS), 211 211 GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 212 - RK1108_CLKGATE_CON(10), 2, GFLAGS), 212 + RV1108_CLKGATE_CON(10), 2, GFLAGS), 213 213 GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, 214 - RK1108_CLKGATE_CON(10), 3, GFLAGS), 214 + RV1108_CLKGATE_CON(10), 3, GFLAGS), 215 215 GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED, 216 - RK1108_CLKGATE_CON(10), 4, GFLAGS), 216 + RV1108_CLKGATE_CON(10), 4, GFLAGS), 217 217 GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 218 - RK1108_CLKGATE_CON(10), 5, GFLAGS), 218 + RV1108_CLKGATE_CON(10), 5, GFLAGS), 219 219 GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 220 - RK1108_CLKGATE_CON(10), 6, GFLAGS), 220 + RV1108_CLKGATE_CON(10), 6, GFLAGS), 221 221 COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 222 - RK1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 223 - RK1108_CLKGATE_CON(8), 15, GFLAGS), 222 + RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 223 + RV1108_CLKGATE_CON(8), 15, GFLAGS), 224 224 COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 225 - RK1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 226 - RK1108_CLKGATE_CON(8), 14, GFLAGS), 225 + RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 226 + RV1108_CLKGATE_CON(8), 14, GFLAGS), 227 227 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, 228 - RK1108_CLKGATE_CON(8), 13, GFLAGS), 228 + RV1108_CLKGATE_CON(8), 13, GFLAGS), 229 229 230 230 /* 231 231 * Clock-Architecture Diagram 4 232 232 */ 233 233 COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 234 - RK1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 235 - RK1108_CLKGATE_CON(6), 0, GFLAGS), 234 + RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 235 + RV1108_CLKGATE_CON(6), 0, GFLAGS), 236 236 GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED, 237 - RK1108_CLKGATE_CON(17), 0, GFLAGS), 237 + RV1108_CLKGATE_CON(17), 0, GFLAGS), 238 238 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, 239 - RK1108_CLKSEL_CON(29), 0, 5, DFLAGS, 240 - RK1108_CLKGATE_CON(7), 2, GFLAGS), 239 + RV1108_CLKSEL_CON(29), 0, 5, DFLAGS, 240 + RV1108_CLKGATE_CON(7), 2, GFLAGS), 241 241 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, 242 - RK1108_CLKSEL_CON(29), 8, 5, DFLAGS, 243 - RK1108_CLKGATE_CON(7), 3, GFLAGS), 242 + RV1108_CLKSEL_CON(29), 8, 5, DFLAGS, 243 + RV1108_CLKGATE_CON(7), 3, GFLAGS), 244 244 245 245 INVERTER(0, "pclk_vip", "ext_vip", 246 - RK1108_CLKSEL_CON(31), 8, IFLAGS), 246 + RV1108_CLKSEL_CON(31), 8, IFLAGS), 247 247 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, 248 - RK1108_CLKGATE_CON(7), 6, GFLAGS), 248 + RV1108_CLKGATE_CON(7), 6, GFLAGS), 249 249 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED, 250 - RK1108_CLKGATE_CON(18), 10, GFLAGS), 250 + RV1108_CLKGATE_CON(18), 10, GFLAGS), 251 251 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED, 252 - RK1108_CLKGATE_CON(6), 5, GFLAGS), 252 + RV1108_CLKGATE_CON(6), 5, GFLAGS), 253 253 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, 254 - RK1108_CLKGATE_CON(6), 4, GFLAGS), 254 + RV1108_CLKGATE_CON(6), 4, GFLAGS), 255 255 COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0, 256 - RK1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS), 256 + RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS), 257 257 258 258 /* 259 259 * Clock-Architecture Diagram 5 ··· 262 262 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 263 263 264 264 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, 265 - RK1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 266 - RK1108_CLKGATE_CON(2), 0, GFLAGS), 265 + RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 266 + RV1108_CLKGATE_CON(2), 0, GFLAGS), 267 267 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 268 - RK1108_CLKSEL_CON(8), 0, 269 - RK1108_CLKGATE_CON(2), 1, GFLAGS, 270 - &rk1108_i2s0_fracmux), 268 + RV1108_CLKSEL_CON(8), 0, 269 + RV1108_CLKGATE_CON(2), 1, GFLAGS, 270 + &rv1108_i2s0_fracmux), 271 271 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 272 - RK1108_CLKGATE_CON(2), 2, GFLAGS), 272 + RV1108_CLKGATE_CON(2), 2, GFLAGS), 273 273 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0, 274 - RK1108_CLKSEL_CON(5), 15, 1, MFLAGS, 275 - RK1108_CLKGATE_CON(2), 3, GFLAGS), 274 + RV1108_CLKSEL_CON(5), 15, 1, MFLAGS, 275 + RV1108_CLKGATE_CON(2), 3, GFLAGS), 276 276 277 277 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, 278 - RK1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 279 - RK1108_CLKGATE_CON(2), 4, GFLAGS), 278 + RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 279 + RV1108_CLKGATE_CON(2), 4, GFLAGS), 280 280 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 281 281 RK2928_CLKSEL_CON(9), 0, 282 282 RK2928_CLKGATE_CON(2), 5, GFLAGS, 283 - &rk1108_i2s1_fracmux), 283 + &rv1108_i2s1_fracmux), 284 284 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 285 - RK1108_CLKGATE_CON(2), 6, GFLAGS), 285 + RV1108_CLKGATE_CON(2), 6, GFLAGS), 286 286 287 287 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, 288 - RK1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 289 - RK1108_CLKGATE_CON(3), 8, GFLAGS), 288 + RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 289 + RV1108_CLKGATE_CON(3), 8, GFLAGS), 290 290 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 291 - RK1108_CLKSEL_CON(10), 0, 292 - RK1108_CLKGATE_CON(2), 9, GFLAGS, 293 - &rk1108_i2s2_fracmux), 291 + RV1108_CLKSEL_CON(10), 0, 292 + RV1108_CLKGATE_CON(2), 9, GFLAGS, 293 + &rv1108_i2s2_fracmux), 294 294 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, 295 - RK1108_CLKGATE_CON(2), 10, GFLAGS), 295 + RV1108_CLKGATE_CON(2), 10, GFLAGS), 296 296 297 297 /* PD_BUS */ 298 298 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, 299 - RK1108_CLKGATE_CON(1), 0, GFLAGS), 299 + RV1108_CLKGATE_CON(1), 0, GFLAGS), 300 300 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, 301 - RK1108_CLKGATE_CON(1), 1, GFLAGS), 301 + RV1108_CLKGATE_CON(1), 1, GFLAGS), 302 302 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, 303 - RK1108_CLKGATE_CON(1), 2, GFLAGS), 303 + RV1108_CLKGATE_CON(1), 2, GFLAGS), 304 304 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, 305 - RK1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 305 + RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 306 306 COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0, 307 - RK1108_CLKSEL_CON(3), 0, 5, DFLAGS, 308 - RK1108_CLKGATE_CON(1), 4, GFLAGS), 307 + RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, 308 + RV1108_CLKGATE_CON(1), 4, GFLAGS), 309 309 COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0, 310 - RK1108_CLKSEL_CON(3), 8, 5, DFLAGS, 311 - RK1108_CLKGATE_CON(1), 5, GFLAGS), 310 + RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, 311 + RV1108_CLKGATE_CON(1), 5, GFLAGS), 312 312 GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED, 313 - RK1108_CLKGATE_CON(1), 6, GFLAGS), 313 + RV1108_CLKGATE_CON(1), 6, GFLAGS), 314 314 GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED, 315 - RK1108_CLKGATE_CON(1), 7, GFLAGS), 315 + RV1108_CLKGATE_CON(1), 7, GFLAGS), 316 316 GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED, 317 - RK1108_CLKGATE_CON(1), 8, GFLAGS), 317 + RV1108_CLKGATE_CON(1), 8, GFLAGS), 318 318 GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED, 319 - RK1108_CLKGATE_CON(1), 9, GFLAGS), 319 + RV1108_CLKGATE_CON(1), 9, GFLAGS), 320 320 GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED, 321 - RK1108_CLKGATE_CON(1), 10, GFLAGS), 321 + RV1108_CLKGATE_CON(1), 10, GFLAGS), 322 322 GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, 323 - RK1108_CLKGATE_CON(13), 4, GFLAGS), 323 + RV1108_CLKGATE_CON(13), 4, GFLAGS), 324 324 325 325 COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 326 - RK1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 327 - RK1108_CLKGATE_CON(3), 1, GFLAGS), 326 + RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 327 + RV1108_CLKGATE_CON(3), 1, GFLAGS), 328 328 COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 329 - RK1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 330 - RK1108_CLKGATE_CON(3), 3, GFLAGS), 329 + RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 330 + RV1108_CLKGATE_CON(3), 3, GFLAGS), 331 331 COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 332 - RK1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 333 - RK1108_CLKGATE_CON(3), 5, GFLAGS), 332 + RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 333 + RV1108_CLKGATE_CON(3), 5, GFLAGS), 334 334 335 335 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 336 - RK1108_CLKSEL_CON(16), 0, 337 - RK1108_CLKGATE_CON(3), 2, GFLAGS, 338 - &rk1108_uart0_fracmux), 336 + RV1108_CLKSEL_CON(16), 0, 337 + RV1108_CLKGATE_CON(3), 2, GFLAGS, 338 + &rv1108_uart0_fracmux), 339 339 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 340 - RK1108_CLKSEL_CON(17), 0, 341 - RK1108_CLKGATE_CON(3), 4, GFLAGS, 342 - &rk1108_uart1_fracmux), 340 + RV1108_CLKSEL_CON(17), 0, 341 + RV1108_CLKGATE_CON(3), 4, GFLAGS, 342 + &rv1108_uart1_fracmux), 343 343 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 344 - RK1108_CLKSEL_CON(18), 0, 345 - RK1108_CLKGATE_CON(3), 6, GFLAGS, 346 - &rk1108_uart2_fracmux), 344 + RV1108_CLKSEL_CON(18), 0, 345 + RV1108_CLKGATE_CON(3), 6, GFLAGS, 346 + &rv1108_uart2_fracmux), 347 347 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED, 348 - RK1108_CLKGATE_CON(13), 10, GFLAGS), 348 + RV1108_CLKGATE_CON(13), 10, GFLAGS), 349 349 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 350 - RK1108_CLKGATE_CON(13), 11, GFLAGS), 350 + RV1108_CLKGATE_CON(13), 11, GFLAGS), 351 351 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 352 - RK1108_CLKGATE_CON(13), 12, GFLAGS), 352 + RV1108_CLKGATE_CON(13), 12, GFLAGS), 353 353 354 354 COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 355 - RK1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS, 356 - RK1108_CLKGATE_CON(3), 7, GFLAGS), 355 + RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS, 356 + RV1108_CLKGATE_CON(3), 7, GFLAGS), 357 357 COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 358 - RK1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS, 359 - RK1108_CLKGATE_CON(3), 8, GFLAGS), 358 + RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS, 359 + RV1108_CLKGATE_CON(3), 8, GFLAGS), 360 360 COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 361 - RK1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS, 362 - RK1108_CLKGATE_CON(3), 9, GFLAGS), 361 + RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS, 362 + RV1108_CLKGATE_CON(3), 9, GFLAGS), 363 363 GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 364 - RK1108_CLKGATE_CON(13), 0, GFLAGS), 364 + RV1108_CLKGATE_CON(13), 0, GFLAGS), 365 365 GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 366 - RK1108_CLKGATE_CON(13), 1, GFLAGS), 366 + RV1108_CLKGATE_CON(13), 1, GFLAGS), 367 367 GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 368 - RK1108_CLKGATE_CON(13), 2, GFLAGS), 368 + RV1108_CLKGATE_CON(13), 2, GFLAGS), 369 369 COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 370 - RK1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 371 - RK1108_CLKGATE_CON(3), 10, GFLAGS), 370 + RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 371 + RV1108_CLKGATE_CON(3), 10, GFLAGS), 372 372 GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 373 - RK1108_CLKGATE_CON(13), 6, GFLAGS), 373 + RV1108_CLKGATE_CON(13), 6, GFLAGS), 374 374 GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED, 375 - RK1108_CLKGATE_CON(13), 3, GFLAGS), 375 + RV1108_CLKGATE_CON(13), 3, GFLAGS), 376 376 GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 377 - RK1108_CLKGATE_CON(13), 7, GFLAGS), 377 + RV1108_CLKGATE_CON(13), 7, GFLAGS), 378 378 GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 379 - RK1108_CLKGATE_CON(13), 8, GFLAGS), 379 + RV1108_CLKGATE_CON(13), 8, GFLAGS), 380 380 GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 381 - RK1108_CLKGATE_CON(13), 9, GFLAGS), 381 + RV1108_CLKGATE_CON(13), 9, GFLAGS), 382 382 383 383 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, 384 - RK1108_CLKGATE_CON(14), 0, GFLAGS), 384 + RV1108_CLKGATE_CON(14), 0, GFLAGS), 385 385 386 386 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, 387 - RK1108_CLKGATE_CON(12), 2, GFLAGS), 387 + RV1108_CLKGATE_CON(12), 2, GFLAGS), 388 388 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, 389 - RK1108_CLKGATE_CON(12), 3, GFLAGS), 389 + RV1108_CLKGATE_CON(12), 3, GFLAGS), 390 390 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, 391 - RK1108_CLKGATE_CON(12), 1, GFLAGS), 391 + RV1108_CLKGATE_CON(12), 1, GFLAGS), 392 392 393 393 /* PD_DDR */ 394 394 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, 395 - RK1108_CLKGATE_CON(0), 8, GFLAGS), 395 + RV1108_CLKGATE_CON(0), 8, GFLAGS), 396 396 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 397 - RK1108_CLKGATE_CON(0), 9, GFLAGS), 397 + RV1108_CLKGATE_CON(0), 9, GFLAGS), 398 398 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 399 - RK1108_CLKGATE_CON(0), 10, GFLAGS), 399 + RV1108_CLKGATE_CON(0), 10, GFLAGS), 400 400 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 401 - RK1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 401 + RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 402 402 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 403 - RK1108_CLKGATE_CON(10), 9, GFLAGS), 403 + RV1108_CLKGATE_CON(10), 9, GFLAGS), 404 404 GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED, 405 - RK1108_CLKGATE_CON(12), 4, GFLAGS), 405 + RV1108_CLKGATE_CON(12), 4, GFLAGS), 406 406 GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED, 407 - RK1108_CLKGATE_CON(12), 5, GFLAGS), 407 + RV1108_CLKGATE_CON(12), 5, GFLAGS), 408 408 GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED, 409 - RK1108_CLKGATE_CON(12), 6, GFLAGS), 409 + RV1108_CLKGATE_CON(12), 6, GFLAGS), 410 410 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, 411 - RK1108_CLKGATE_CON(0), 11, GFLAGS), 411 + RV1108_CLKGATE_CON(0), 11, GFLAGS), 412 412 413 413 /* 414 414 * Clock-Architecture Diagram 6 ··· 416 416 417 417 /* PD_PERI */ 418 418 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, 419 - RK1108_CLKSEL_CON(23), 10, 5, DFLAGS, 420 - RK1108_CLKGATE_CON(4), 5, GFLAGS), 419 + RV1108_CLKSEL_CON(23), 10, 5, DFLAGS, 420 + RV1108_CLKGATE_CON(4), 5, GFLAGS), 421 421 GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, 422 - RK1108_CLKGATE_CON(15), 13, GFLAGS), 422 + RV1108_CLKGATE_CON(15), 13, GFLAGS), 423 423 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, 424 - RK1108_CLKSEL_CON(23), 5, 5, DFLAGS, 425 - RK1108_CLKGATE_CON(4), 4, GFLAGS), 424 + RV1108_CLKSEL_CON(23), 5, 5, DFLAGS, 425 + RV1108_CLKGATE_CON(4), 4, GFLAGS), 426 426 GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, 427 - RK1108_CLKGATE_CON(15), 12, GFLAGS), 427 + RV1108_CLKGATE_CON(15), 12, GFLAGS), 428 428 429 429 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, 430 - RK1108_CLKGATE_CON(4), 1, GFLAGS), 430 + RV1108_CLKGATE_CON(4), 1, GFLAGS), 431 431 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, 432 - RK1108_CLKGATE_CON(4), 2, GFLAGS), 432 + RV1108_CLKGATE_CON(4), 2, GFLAGS), 433 433 COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED, 434 - RK1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS, 435 - RK1108_CLKGATE_CON(15), 11, GFLAGS), 434 + RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS, 435 + RV1108_CLKGATE_CON(15), 11, GFLAGS), 436 436 437 437 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, 438 - RK1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 439 - RK1108_CLKGATE_CON(5), 0, GFLAGS), 438 + RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 439 + RV1108_CLKGATE_CON(5), 0, GFLAGS), 440 440 441 441 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 442 - RK1108_CLKSEL_CON(25), 10, 2, MFLAGS, 443 - RK1108_CLKGATE_CON(5), 2, GFLAGS), 442 + RV1108_CLKSEL_CON(25), 10, 2, MFLAGS, 443 + RV1108_CLKGATE_CON(5), 2, GFLAGS), 444 444 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 445 - RK1108_CLKSEL_CON(26), 0, 8, DFLAGS), 445 + RV1108_CLKSEL_CON(26), 0, 8, DFLAGS), 446 446 447 447 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, 448 - RK1108_CLKSEL_CON(25), 12, 2, MFLAGS, 449 - RK1108_CLKGATE_CON(5), 1, GFLAGS), 448 + RV1108_CLKSEL_CON(25), 12, 2, MFLAGS, 449 + RV1108_CLKGATE_CON(5), 1, GFLAGS), 450 450 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, 451 451 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS), 452 - GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 0, GFLAGS), 453 - GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 1, GFLAGS), 454 - GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 2, GFLAGS), 452 + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS), 453 + GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS), 454 + GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS), 455 455 456 456 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 457 - RK1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS, 458 - RK1108_CLKGATE_CON(5), 3, GFLAGS), 459 - GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 3, GFLAGS), 457 + RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS, 458 + RV1108_CLKGATE_CON(5), 3, GFLAGS), 459 + GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS), 460 460 461 461 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, 462 - RK1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS, 463 - RK1108_CLKGATE_CON(5), 4, GFLAGS), 464 - GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 10, GFLAGS), 462 + RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS, 463 + RV1108_CLKGATE_CON(5), 4, GFLAGS), 464 + GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS), 465 465 466 466 COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0, 467 - RK1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS, 468 - RK1108_CLKGATE_CON(4), 10, GFLAGS), 467 + RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS, 468 + RV1108_CLKGATE_CON(4), 10, GFLAGS), 469 469 MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT, 470 - RK1108_CLKSEL_CON(24), 8, 2, MFLAGS), 471 - GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RK1108_CLKGATE_CON(4), 8, GFLAGS), 472 - GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RK1108_CLKGATE_CON(4), 6, GFLAGS), 473 - GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RK1108_CLKGATE_CON(4), 7, GFLAGS), 470 + RV1108_CLKSEL_CON(24), 8, 2, MFLAGS), 471 + GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), 472 + GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), 473 + GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), 474 474 475 - MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK1108_SDMMC_CON0, 1), 476 - MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK1108_SDMMC_CON1, 1), 475 + MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1), 476 + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1), 477 477 478 - MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK1108_SDIO_CON0, 1), 479 - MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK1108_SDIO_CON1, 1), 478 + MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1), 479 + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1), 480 480 481 - MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK1108_EMMC_CON0, 1), 482 - MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK1108_EMMC_CON1, 1), 481 + MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1), 482 + MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1), 483 483 }; 484 484 485 - static const char *const rk1108_critical_clocks[] __initconst = { 485 + static const char *const rv1108_critical_clocks[] __initconst = { 486 486 "aclk_core", 487 487 "aclk_bus_src_gpll", 488 488 "aclk_periph", ··· 490 490 "pclk_periph", 491 491 }; 492 492 493 - static void __init rk1108_clk_init(struct device_node *np) 493 + static void __init rv1108_clk_init(struct device_node *np) 494 494 { 495 495 struct rockchip_clk_provider *ctx; 496 496 void __iomem *reg_base; ··· 508 508 return; 509 509 } 510 510 511 - rockchip_clk_register_plls(ctx, rk1108_pll_clks, 512 - ARRAY_SIZE(rk1108_pll_clks), 513 - RK1108_GRF_SOC_STATUS0); 514 - rockchip_clk_register_branches(ctx, rk1108_clk_branches, 515 - ARRAY_SIZE(rk1108_clk_branches)); 516 - rockchip_clk_protect_critical(rk1108_critical_clocks, 517 - ARRAY_SIZE(rk1108_critical_clocks)); 511 + rockchip_clk_register_plls(ctx, rv1108_pll_clks, 512 + ARRAY_SIZE(rv1108_pll_clks), 513 + RV1108_GRF_SOC_STATUS0); 514 + rockchip_clk_register_branches(ctx, rv1108_clk_branches, 515 + ARRAY_SIZE(rv1108_clk_branches)); 516 + rockchip_clk_protect_critical(rv1108_critical_clocks, 517 + ARRAY_SIZE(rv1108_critical_clocks)); 518 518 519 519 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 520 520 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 521 - &rk1108_cpuclk_data, rk1108_cpuclk_rates, 522 - ARRAY_SIZE(rk1108_cpuclk_rates)); 521 + &rv1108_cpuclk_data, rv1108_cpuclk_rates, 522 + ARRAY_SIZE(rv1108_cpuclk_rates)); 523 523 524 - rockchip_register_softrst(np, 13, reg_base + RK1108_SOFTRST_CON(0), 524 + rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0), 525 525 ROCKCHIP_SOFTRST_HIWORD_MASK); 526 526 527 - rockchip_register_restart_notifier(ctx, RK1108_GLB_SRST_FST, NULL); 527 + rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL); 528 528 529 529 rockchip_clk_of_add_provider(np, ctx); 530 530 } 531 - CLK_OF_DECLARE(rk1108_cru, "rockchip,rk1108-cru", rk1108_clk_init); 531 + CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);
+9
drivers/clk/rockchip/clk-rk3328.c
··· 20 20 #include <dt-bindings/clock/rk3328-cru.h> 21 21 #include "clk.h" 22 22 23 + #define RK3328_GRF_SOC_CON4 0x410 23 24 #define RK3328_GRF_SOC_STATUS0 0x480 24 25 #define RK3328_GRF_MAC_CON1 0x904 25 26 #define RK3328_GRF_MAC_CON2 0x908 ··· 215 214 "gmac_clkin" }; 216 215 PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src", 217 216 "phy_50m_out" }; 217 + PNAME(mux_mac2io_ext_p) = { "clk_mac2io", 218 + "gmac_clkin" }; 218 219 219 220 static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = { 220 221 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, ··· 683 680 COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0, 684 681 RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS, 685 682 RK3328_CLKGATE_CON(3), 5, GFLAGS), 683 + MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT, 684 + RK3328_GRF_MAC_CON1, 10, 1, MFLAGS), 685 + MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT, 686 + RK3328_GRF_SOC_CON4, 14, 1, MFLAGS), 686 687 687 688 COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0, 688 689 RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS, ··· 698 691 COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0, 699 692 RK3328_CLKSEL_CON(26), 8, 2, DFLAGS, 700 693 RK3328_CLKGATE_CON(9), 2, GFLAGS), 694 + MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT, 695 + RK3328_GRF_MAC_CON2, 10, 1, MFLAGS), 701 696 702 697 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 703 698
+15 -12
drivers/clk/rockchip/clk-rk3368.c
··· 835 835 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS), 836 836 837 837 /* timer gates */ 838 - GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS), 839 - GATE(0, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS), 840 - GATE(0, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS), 841 - GATE(0, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS), 842 - GATE(0, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS), 843 - GATE(0, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS), 844 - GATE(0, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS), 845 - GATE(0, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS), 846 - GATE(0, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS), 847 - GATE(0, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS), 848 - GATE(0, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS), 849 - GATE(0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS), 838 + GATE(SCLK_TIMER15, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS), 839 + GATE(SCLK_TIMER14, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS), 840 + GATE(SCLK_TIMER13, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS), 841 + GATE(SCLK_TIMER12, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS), 842 + GATE(SCLK_TIMER11, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS), 843 + GATE(SCLK_TIMER10, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS), 844 + GATE(SCLK_TIMER05, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS), 845 + GATE(SCLK_TIMER04, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS), 846 + GATE(SCLK_TIMER03, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS), 847 + GATE(SCLK_TIMER02, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS), 848 + GATE(SCLK_TIMER01, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS), 849 + GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS), 850 850 }; 851 851 852 852 static const char *const rk3368_critical_clocks[] __initconst = { ··· 858 858 */ 859 859 "pclk_pwm1", 860 860 "pclk_pd_pmu", 861 + "pclk_pd_alive", 862 + "pclk_peri", 863 + "hclk_peri", 861 864 }; 862 865 863 866 static void __init rk3368_clk_init(struct device_node *np)
+4 -4
drivers/clk/rockchip/clk-rk3399.c
··· 1477 1477 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), 1478 1478 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), 1479 1479 1480 - GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), 1481 - GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), 1482 - GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), 1483 - GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), 1480 + GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), 1481 + GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), 1482 + GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), 1483 + GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), 1484 1484 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), 1485 1485 }; 1486 1486
+14 -14
drivers/clk/rockchip/clk.h
··· 34 34 #define HIWORD_UPDATE(val, mask, shift) \ 35 35 ((val) << (shift) | (mask) << ((shift) + 16)) 36 36 37 - /* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ 38 - #define RK1108_PLL_CON(x) ((x) * 0x4) 39 - #define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 40 - #define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) 41 - #define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) 42 - #define RK1108_GLB_SRST_FST 0x1c0 43 - #define RK1108_GLB_SRST_SND 0x1c4 44 - #define RK1108_MISC_CON 0x1cc 45 - #define RK1108_SDMMC_CON0 0x1d8 46 - #define RK1108_SDMMC_CON1 0x1dc 47 - #define RK1108_SDIO_CON0 0x1e0 48 - #define RK1108_SDIO_CON1 0x1e4 49 - #define RK1108_EMMC_CON0 0x1e8 50 - #define RK1108_EMMC_CON1 0x1ec 37 + /* register positions shared by RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ 38 + #define RV1108_PLL_CON(x) ((x) * 0x4) 39 + #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 40 + #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) 41 + #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) 42 + #define RV1108_GLB_SRST_FST 0x1c0 43 + #define RV1108_GLB_SRST_SND 0x1c4 44 + #define RV1108_MISC_CON 0x1cc 45 + #define RV1108_SDMMC_CON0 0x1d8 46 + #define RV1108_SDMMC_CON1 0x1dc 47 + #define RV1108_SDIO_CON0 0x1e0 48 + #define RV1108_SDIO_CON1 0x1e4 49 + #define RV1108_EMMC_CON0 0x1e8 50 + #define RV1108_EMMC_CON1 0x1ec 51 51 52 52 #define RK2928_PLL_CON(x) ((x) * 0x4) 53 53 #define RK2928_MODE_CON 0x40
+3 -3
include/dt-bindings/clock/rk1108-cru.h include/dt-bindings/clock/rv1108-cru.h
··· 13 13 * GNU General Public License for more details. 14 14 */ 15 15 16 - #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H 17 - #define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H 16 + #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 17 + #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 18 18 19 19 /* pll id */ 20 20 #define PLL_APLL 0 ··· 266 266 #define ARST_DSP_EDP_PERF 184 267 267 #define ARST_DSP_EPP_PERF 185 268 268 269 - #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */ 269 + #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
+1
include/dt-bindings/clock/rk3328-cru.h
··· 97 97 #define SCLK_MAC2IO_SRC 99 98 98 #define SCLK_MAC2IO 100 99 99 #define SCLK_MAC2PHY 101 100 + #define SCLK_MAC2IO_EXT 102 100 101 101 102 /* dclk gates */ 102 103 #define DCLK_LCDC 120
+12 -7
include/dt-bindings/clock/rk3368-cru.h
··· 44 44 #define SCLK_I2S_8CH 82 45 45 #define SCLK_SPDIF_8CH 83 46 46 #define SCLK_I2S_2CH 84 47 - #define SCLK_TIMER0 85 48 - #define SCLK_TIMER1 86 49 - #define SCLK_TIMER2 87 50 - #define SCLK_TIMER3 88 51 - #define SCLK_TIMER4 89 52 - #define SCLK_TIMER5 90 53 - #define SCLK_TIMER6 91 47 + #define SCLK_TIMER00 85 48 + #define SCLK_TIMER01 86 49 + #define SCLK_TIMER02 87 50 + #define SCLK_TIMER03 88 51 + #define SCLK_TIMER04 89 52 + #define SCLK_TIMER05 90 54 53 #define SCLK_OTGPHY0 93 55 54 #define SCLK_OTG_ADP 96 56 55 #define SCLK_HSICPHY480M 97 ··· 81 82 #define SCLK_SFC 126 82 83 #define SCLK_MAC 127 83 84 #define SCLK_MACREF_OUT 128 85 + #define SCLK_TIMER10 133 86 + #define SCLK_TIMER11 134 87 + #define SCLK_TIMER12 135 88 + #define SCLK_TIMER13 136 89 + #define SCLK_TIMER14 137 90 + #define SCLK_TIMER15 138 84 91 85 92 #define DCLK_VOP 190 86 93 #define MCLK_CRYPTO 191