tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/radeon/kms: add rn50/r100/r200 CS tracker.

This adds the command stream checker for the RN50, R100 and R200 cards.

It stops any access to 3D registers on RN50, and does checks
on buffer sizes on the r100/r200 cards. It also fixes some texture
sizing checks on r300.

Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie 551ebd83 11670d3c

+1712 -440
+14 -1
drivers/gpu/drm/radeon/Makefile
··· 11 11 quiet_cmd_mkregtable = MKREGTABLE $@ 12 12 cmd_mkregtable = $(obj)/mkregtable $< > $@ 13 13 14 + $(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable 15 + $(call if_changed,mkregtable) 16 + 17 + $(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable 18 + $(call if_changed,mkregtable) 19 + 20 + $(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable 21 + $(call if_changed,mkregtable) 22 + 14 23 $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable 15 24 $(call if_changed,mkregtable) 16 25 ··· 28 19 29 20 $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable 30 21 $(call if_changed,mkregtable) 22 + 23 + $(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h 24 + 25 + $(obj)/r200.o: $(obj)/r200_reg_safe.h 31 26 32 27 $(obj)/rv515.o: $(obj)/rv515_reg_safe.h 33 28 ··· 47 34 radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ 48 35 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ 49 36 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \ 50 - radeon_test.o 37 + radeon_test.o r200.o 51 38 52 39 radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 53 40
+691 -120
drivers/gpu/drm/radeon/r100.c
··· 34 34 #include <linux/firmware.h> 35 35 #include <linux/platform_device.h> 36 36 37 + #include "r100_reg_safe.h" 38 + #include "rn50_reg_safe.h" 39 + 37 40 /* Firmware Names */ 38 41 #define FIRMWARE_R100 "radeon/R100_cp.bin" 39 42 #define FIRMWARE_R200 "radeon/R200_cp.bin" ··· 54 51 MODULE_FIRMWARE(FIRMWARE_RS600); 55 52 MODULE_FIRMWARE(FIRMWARE_R520); 56 53 54 + #include "r100_track.h" 55 + 57 56 /* This files gather functions specifics to: 58 57 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 59 58 * 60 59 * Some of these functions might be used by newer ASICs. 61 60 */ 61 + int r200_init(struct radeon_device *rdev); 62 62 void r100_hdp_reset(struct radeon_device *rdev); 63 63 void r100_gpu_init(struct radeon_device *rdev); 64 64 int r100_gui_wait_for_idle(struct radeon_device *rdev); ··· 1023 1017 return 0; 1024 1018 } 1025 1019 1020 + static int r100_get_vtx_size(uint32_t vtx_fmt) 1021 + { 1022 + int vtx_size; 1023 + vtx_size = 2; 1024 + /* ordered according to bits in spec */ 1025 + if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1026 + vtx_size++; 1027 + if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1028 + vtx_size += 3; 1029 + if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1030 + vtx_size++; 1031 + if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1032 + vtx_size++; 1033 + if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1034 + vtx_size += 3; 1035 + if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1036 + vtx_size++; 1037 + if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1038 + vtx_size++; 1039 + if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1040 + vtx_size += 2; 1041 + if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1042 + vtx_size += 2; 1043 + if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1044 + vtx_size++; 1045 + if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1046 + vtx_size += 2; 1047 + if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1048 + vtx_size++; 1049 + if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1050 + vtx_size += 2; 1051 + if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1052 + vtx_size++; 1053 + if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1054 + vtx_size++; 1055 + /* blend weight */ 1056 + if (vtx_fmt & (0x7 << 15)) 1057 + vtx_size += (vtx_fmt >> 15) & 0x7; 1058 + if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1059 + vtx_size += 3; 1060 + if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1061 + vtx_size += 2; 1062 + if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1063 + vtx_size++; 1064 + if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1065 + vtx_size++; 1066 + if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1067 + vtx_size++; 1068 + if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1069 + vtx_size++; 1070 + return vtx_size; 1071 + } 1072 + 1026 1073 static int r100_packet0_check(struct radeon_cs_parser *p, 1027 - struct radeon_cs_packet *pkt) 1074 + struct radeon_cs_packet *pkt, 1075 + unsigned idx, unsigned reg) 1028 1076 { 1029 1077 struct radeon_cs_chunk *ib_chunk; 1030 1078 struct radeon_cs_reloc *reloc; 1079 + struct r100_cs_track *track; 1031 1080 volatile uint32_t *ib; 1032 1081 uint32_t tmp; 1033 - unsigned reg; 1034 - unsigned i; 1035 - unsigned idx; 1036 - bool onereg; 1037 1082 int r; 1083 + int i, face; 1038 1084 u32 tile_flags = 0; 1039 1085 1040 1086 ib = p->ib->ptr; 1041 1087 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1042 - idx = pkt->idx + 1; 1043 - reg = pkt->reg; 1044 - onereg = false; 1045 - if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) { 1046 - onereg = true; 1047 - } 1048 - for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 1049 - switch (reg) { 1050 - case RADEON_CRTC_GUI_TRIG_VLINE: 1051 - r = r100_cs_packet_parse_vline(p); 1052 - if (r) { 1053 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1054 - idx, reg); 1055 - r100_cs_dump_packet(p, pkt); 1056 - return r; 1057 - } 1058 - break; 1088 + track = (struct r100_cs_track *)p->track; 1089 + 1090 + switch (reg) { 1091 + case RADEON_CRTC_GUI_TRIG_VLINE: 1092 + r = r100_cs_packet_parse_vline(p); 1093 + if (r) { 1094 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1095 + idx, reg); 1096 + r100_cs_dump_packet(p, pkt); 1097 + return r; 1098 + } 1099 + break; 1059 1100 /* FIXME: only allow PACKET3 blit? easier to check for out of 1060 1101 * range access */ 1061 - case RADEON_DST_PITCH_OFFSET: 1062 - case RADEON_SRC_PITCH_OFFSET: 1063 - r = r100_cs_packet_next_reloc(p, &reloc); 1064 - if (r) { 1065 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1066 - idx, reg); 1067 - r100_cs_dump_packet(p, pkt); 1068 - return r; 1069 - } 1070 - tmp = ib_chunk->kdata[idx] & 0x003fffff; 1071 - tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1102 + case RADEON_DST_PITCH_OFFSET: 1103 + case RADEON_SRC_PITCH_OFFSET: 1104 + r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1105 + if (r) 1106 + return r; 1107 + break; 1108 + case RADEON_RB3D_DEPTHOFFSET: 1109 + r = r100_cs_packet_next_reloc(p, &reloc); 1110 + if (r) { 1111 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1112 + idx, reg); 1113 + r100_cs_dump_packet(p, pkt); 1114 + return r; 1115 + } 1116 + track->zb.robj = reloc->robj; 1117 + track->zb.offset = ib_chunk->kdata[idx]; 1118 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1119 + break; 1120 + case RADEON_RB3D_COLOROFFSET: 1121 + r = r100_cs_packet_next_reloc(p, &reloc); 1122 + if (r) { 1123 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1124 + idx, reg); 1125 + r100_cs_dump_packet(p, pkt); 1126 + return r; 1127 + } 1128 + track->cb[0].robj = reloc->robj; 1129 + track->cb[0].offset = ib_chunk->kdata[idx]; 1130 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1131 + break; 1132 + case RADEON_PP_TXOFFSET_0: 1133 + case RADEON_PP_TXOFFSET_1: 1134 + case RADEON_PP_TXOFFSET_2: 1135 + i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1136 + r = r100_cs_packet_next_reloc(p, &reloc); 1137 + if (r) { 1138 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1139 + idx, reg); 1140 + r100_cs_dump_packet(p, pkt); 1141 + return r; 1142 + } 1143 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1144 + track->textures[i].robj = reloc->robj; 1145 + break; 1146 + case RADEON_PP_CUBIC_OFFSET_T0_0: 1147 + case RADEON_PP_CUBIC_OFFSET_T0_1: 1148 + case RADEON_PP_CUBIC_OFFSET_T0_2: 1149 + case RADEON_PP_CUBIC_OFFSET_T0_3: 1150 + case RADEON_PP_CUBIC_OFFSET_T0_4: 1151 + i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1152 + r = r100_cs_packet_next_reloc(p, &reloc); 1153 + if (r) { 1154 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1155 + idx, reg); 1156 + r100_cs_dump_packet(p, pkt); 1157 + return r; 1158 + } 1159 + track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx]; 1160 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1161 + track->textures[0].cube_info[i].robj = reloc->robj; 1162 + break; 1163 + case RADEON_PP_CUBIC_OFFSET_T1_0: 1164 + case RADEON_PP_CUBIC_OFFSET_T1_1: 1165 + case RADEON_PP_CUBIC_OFFSET_T1_2: 1166 + case RADEON_PP_CUBIC_OFFSET_T1_3: 1167 + case RADEON_PP_CUBIC_OFFSET_T1_4: 1168 + i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1169 + r = r100_cs_packet_next_reloc(p, &reloc); 1170 + if (r) { 1171 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1172 + idx, reg); 1173 + r100_cs_dump_packet(p, pkt); 1174 + return r; 1175 + } 1176 + track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx]; 1177 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1178 + track->textures[1].cube_info[i].robj = reloc->robj; 1179 + break; 1180 + case RADEON_PP_CUBIC_OFFSET_T2_0: 1181 + case RADEON_PP_CUBIC_OFFSET_T2_1: 1182 + case RADEON_PP_CUBIC_OFFSET_T2_2: 1183 + case RADEON_PP_CUBIC_OFFSET_T2_3: 1184 + case RADEON_PP_CUBIC_OFFSET_T2_4: 1185 + i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1186 + r = r100_cs_packet_next_reloc(p, &reloc); 1187 + if (r) { 1188 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1189 + idx, reg); 1190 + r100_cs_dump_packet(p, pkt); 1191 + return r; 1192 + } 1193 + track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx]; 1194 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1195 + track->textures[2].cube_info[i].robj = reloc->robj; 1196 + break; 1197 + case RADEON_RE_WIDTH_HEIGHT: 1198 + track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); 1199 + break; 1200 + case RADEON_RB3D_COLORPITCH: 1201 + r = r100_cs_packet_next_reloc(p, &reloc); 1202 + if (r) { 1203 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1204 + idx, reg); 1205 + r100_cs_dump_packet(p, pkt); 1206 + return r; 1207 + } 1072 1208 1073 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1074 - tile_flags |= RADEON_DST_TILE_MACRO; 1075 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1076 - if (reg == RADEON_SRC_PITCH_OFFSET) { 1077 - DRM_ERROR("Cannot src blit from microtiled surface\n"); 1078 - r100_cs_dump_packet(p, pkt); 1079 - return -EINVAL; 1080 - } 1081 - tile_flags |= RADEON_DST_TILE_MICRO; 1082 - } 1209 + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1210 + tile_flags |= RADEON_COLOR_TILE_ENABLE; 1211 + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1212 + tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1083 1213 1084 - tmp |= tile_flags; 1085 - ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; 1214 + tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); 1215 + tmp |= tile_flags; 1216 + ib[idx] = tmp; 1217 + 1218 + track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; 1219 + break; 1220 + case RADEON_RB3D_DEPTHPITCH: 1221 + track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; 1222 + break; 1223 + case RADEON_RB3D_CNTL: 1224 + switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1225 + case 7: 1226 + case 8: 1227 + case 9: 1228 + case 11: 1229 + case 12: 1230 + track->cb[0].cpp = 1; 1086 1231 break; 1087 - case RADEON_RB3D_DEPTHOFFSET: 1088 - case RADEON_RB3D_COLOROFFSET: 1089 - case R300_RB3D_COLOROFFSET0: 1090 - case R300_ZB_DEPTHOFFSET: 1091 - case R200_PP_TXOFFSET_0: 1092 - case R200_PP_TXOFFSET_1: 1093 - case R200_PP_TXOFFSET_2: 1094 - case R200_PP_TXOFFSET_3: 1095 - case R200_PP_TXOFFSET_4: 1096 - case R200_PP_TXOFFSET_5: 1097 - case RADEON_PP_TXOFFSET_0: 1098 - case RADEON_PP_TXOFFSET_1: 1099 - case RADEON_PP_TXOFFSET_2: 1100 - case R300_TX_OFFSET_0: 1101 - case R300_TX_OFFSET_0+4: 1102 - case R300_TX_OFFSET_0+8: 1103 - case R300_TX_OFFSET_0+12: 1104 - case R300_TX_OFFSET_0+16: 1105 - case R300_TX_OFFSET_0+20: 1106 - case R300_TX_OFFSET_0+24: 1107 - case R300_TX_OFFSET_0+28: 1108 - case R300_TX_OFFSET_0+32: 1109 - case R300_TX_OFFSET_0+36: 1110 - case R300_TX_OFFSET_0+40: 1111 - case R300_TX_OFFSET_0+44: 1112 - case R300_TX_OFFSET_0+48: 1113 - case R300_TX_OFFSET_0+52: 1114 - case R300_TX_OFFSET_0+56: 1115 - case R300_TX_OFFSET_0+60: 1116 - /* rn50 has no 3D engine so fail on any 3d setup */ 1117 - if (ASIC_IS_RN50(p->rdev)) { 1118 - DRM_ERROR("attempt to use RN50 3D engine failed\n"); 1119 - return -EINVAL; 1120 - } 1121 - r = r100_cs_packet_next_reloc(p, &reloc); 1122 - if (r) { 1123 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1124 - idx, reg); 1125 - r100_cs_dump_packet(p, pkt); 1126 - return r; 1127 - } 1128 - ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1232 + case 3: 1233 + case 4: 1234 + case 15: 1235 + track->cb[0].cpp = 2; 1129 1236 break; 1130 - case R300_RB3D_COLORPITCH0: 1131 - case RADEON_RB3D_COLORPITCH: 1132 - r = r100_cs_packet_next_reloc(p, &reloc); 1133 - if (r) { 1134 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1135 - idx, reg); 1136 - r100_cs_dump_packet(p, pkt); 1137 - return r; 1138 - } 1139 - 1140 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1141 - tile_flags |= RADEON_COLOR_TILE_ENABLE; 1142 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1143 - tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1144 - 1145 - tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); 1146 - tmp |= tile_flags; 1147 - ib[idx] = tmp; 1148 - break; 1149 - case RADEON_RB3D_ZPASS_ADDR: 1150 - r = r100_cs_packet_next_reloc(p, &reloc); 1151 - if (r) { 1152 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1153 - idx, reg); 1154 - r100_cs_dump_packet(p, pkt); 1155 - return r; 1156 - } 1157 - ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1237 + case 6: 1238 + track->cb[0].cpp = 4; 1158 1239 break; 1159 1240 default: 1160 - /* FIXME: we don't want to allow anyothers packet */ 1241 + DRM_ERROR("Invalid color buffer format (%d) !\n", 1242 + ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1243 + return -EINVAL; 1244 + } 1245 + track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); 1246 + break; 1247 + case RADEON_RB3D_ZSTENCILCNTL: 1248 + switch (ib_chunk->kdata[idx] & 0xf) { 1249 + case 0: 1250 + track->zb.cpp = 2; 1251 + break; 1252 + case 2: 1253 + case 3: 1254 + case 4: 1255 + case 5: 1256 + case 9: 1257 + case 11: 1258 + track->zb.cpp = 4; 1259 + break; 1260 + default: 1161 1261 break; 1162 1262 } 1163 - if (onereg) { 1164 - /* FIXME: forbid onereg write to register on relocate */ 1263 + break; 1264 + case RADEON_RB3D_ZPASS_ADDR: 1265 + r = r100_cs_packet_next_reloc(p, &reloc); 1266 + if (r) { 1267 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1268 + idx, reg); 1269 + r100_cs_dump_packet(p, pkt); 1270 + return r; 1271 + } 1272 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1273 + break; 1274 + case RADEON_PP_CNTL: 1275 + { 1276 + uint32_t temp = ib_chunk->kdata[idx] >> 4; 1277 + for (i = 0; i < track->num_texture; i++) 1278 + track->textures[i].enabled = !!(temp & (1 << i)); 1279 + } 1280 + break; 1281 + case RADEON_SE_VF_CNTL: 1282 + track->vap_vf_cntl = ib_chunk->kdata[idx]; 1283 + break; 1284 + case RADEON_SE_VTX_FMT: 1285 + track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]); 1286 + break; 1287 + case RADEON_PP_TEX_SIZE_0: 1288 + case RADEON_PP_TEX_SIZE_1: 1289 + case RADEON_PP_TEX_SIZE_2: 1290 + i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1291 + track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; 1292 + track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1293 + break; 1294 + case RADEON_PP_TEX_PITCH_0: 1295 + case RADEON_PP_TEX_PITCH_1: 1296 + case RADEON_PP_TEX_PITCH_2: 1297 + i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1298 + track->textures[i].pitch = ib_chunk->kdata[idx] + 32; 1299 + break; 1300 + case RADEON_PP_TXFILTER_0: 1301 + case RADEON_PP_TXFILTER_1: 1302 + case RADEON_PP_TXFILTER_2: 1303 + i = (reg - RADEON_PP_TXFILTER_0) / 24; 1304 + track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK) 1305 + >> RADEON_MAX_MIP_LEVEL_SHIFT); 1306 + tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; 1307 + if (tmp == 2 || tmp == 6) 1308 + track->textures[i].roundup_w = false; 1309 + tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; 1310 + if (tmp == 2 || tmp == 6) 1311 + track->textures[i].roundup_h = false; 1312 + break; 1313 + case RADEON_PP_TXFORMAT_0: 1314 + case RADEON_PP_TXFORMAT_1: 1315 + case RADEON_PP_TXFORMAT_2: 1316 + i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1317 + if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) { 1318 + track->textures[i].use_pitch = 1; 1319 + } else { 1320 + track->textures[i].use_pitch = 0; 1321 + track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1322 + track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1323 + } 1324 + if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1325 + track->textures[i].tex_coord_type = 2; 1326 + switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { 1327 + case RADEON_TXFORMAT_I8: 1328 + case RADEON_TXFORMAT_RGB332: 1329 + case RADEON_TXFORMAT_Y8: 1330 + track->textures[i].cpp = 1; 1331 + break; 1332 + case RADEON_TXFORMAT_AI88: 1333 + case RADEON_TXFORMAT_ARGB1555: 1334 + case RADEON_TXFORMAT_RGB565: 1335 + case RADEON_TXFORMAT_ARGB4444: 1336 + case RADEON_TXFORMAT_VYUY422: 1337 + case RADEON_TXFORMAT_YVYU422: 1338 + case RADEON_TXFORMAT_DXT1: 1339 + case RADEON_TXFORMAT_SHADOW16: 1340 + case RADEON_TXFORMAT_LDUDV655: 1341 + case RADEON_TXFORMAT_DUDV88: 1342 + track->textures[i].cpp = 2; 1343 + break; 1344 + case RADEON_TXFORMAT_ARGB8888: 1345 + case RADEON_TXFORMAT_RGBA8888: 1346 + case RADEON_TXFORMAT_DXT23: 1347 + case RADEON_TXFORMAT_DXT45: 1348 + case RADEON_TXFORMAT_SHADOW32: 1349 + case RADEON_TXFORMAT_LDUDUV8888: 1350 + track->textures[i].cpp = 4; 1165 1351 break; 1166 1352 } 1353 + track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); 1354 + track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); 1355 + break; 1356 + case RADEON_PP_CUBIC_FACES_0: 1357 + case RADEON_PP_CUBIC_FACES_1: 1358 + case RADEON_PP_CUBIC_FACES_2: 1359 + tmp = ib_chunk->kdata[idx]; 1360 + i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1361 + for (face = 0; face < 4; face++) { 1362 + track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1363 + track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1364 + } 1365 + break; 1366 + default: 1367 + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1368 + reg, idx); 1369 + return -EINVAL; 1167 1370 } 1168 1371 return 0; 1169 1372 } ··· 1401 1186 { 1402 1187 struct radeon_cs_chunk *ib_chunk; 1403 1188 struct radeon_cs_reloc *reloc; 1189 + struct r100_cs_track *track; 1404 1190 unsigned idx; 1405 1191 unsigned i, c; 1406 1192 volatile uint32_t *ib; ··· 1410 1194 ib = p->ib->ptr; 1411 1195 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1412 1196 idx = pkt->idx + 1; 1197 + track = (struct r100_cs_track *)p->track; 1413 1198 switch (pkt->opcode) { 1414 1199 case PACKET3_3D_LOAD_VBPNTR: 1415 1200 c = ib_chunk->kdata[idx++]; 1201 + track->num_arrays = c; 1416 1202 for (i = 0; i < (c - 1); i += 2, idx += 3) { 1417 1203 r = r100_cs_packet_next_reloc(p, &reloc); 1418 1204 if (r) { ··· 1424 1206 return r; 1425 1207 } 1426 1208 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); 1209 + track->arrays[i + 0].robj = reloc->robj; 1210 + track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; 1211 + track->arrays[i + 0].esize &= 0x7F; 1427 1212 r = r100_cs_packet_next_reloc(p, &reloc); 1428 1213 if (r) { 1429 1214 DRM_ERROR("No reloc for packet3 %d\n", ··· 1435 1214 return r; 1436 1215 } 1437 1216 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); 1217 + track->arrays[i + 1].robj = reloc->robj; 1218 + track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; 1219 + track->arrays[i + 1].esize &= 0x7F; 1438 1220 } 1439 1221 if (c & 1) { 1440 1222 r = r100_cs_packet_next_reloc(p, &reloc); ··· 1448 1224 return r; 1449 1225 } 1450 1226 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); 1227 + track->arrays[i + 0].robj = reloc->robj; 1228 + track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; 1229 + track->arrays[i + 0].esize &= 0x7F; 1451 1230 } 1452 1231 break; 1453 1232 case PACKET3_INDX_BUFFER: ··· 1467 1240 } 1468 1241 break; 1469 1242 case 0x23: 1470 - /* FIXME: cleanup */ 1471 1243 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1472 1244 r = r100_cs_packet_next_reloc(p, &reloc); 1473 1245 if (r) { ··· 1475 1249 return r; 1476 1250 } 1477 1251 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 1252 + track->num_arrays = 1; 1253 + track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]); 1254 + 1255 + track->arrays[0].robj = reloc->robj; 1256 + track->arrays[0].esize = track->vtx_size; 1257 + 1258 + track->max_indx = ib_chunk->kdata[idx+1]; 1259 + 1260 + track->vap_vf_cntl = ib_chunk->kdata[idx+3]; 1261 + track->immd_dwords = pkt->count - 1; 1262 + r = r100_cs_track_check(p->rdev, track); 1263 + if (r) 1264 + return r; 1478 1265 break; 1479 1266 case PACKET3_3D_DRAW_IMMD: 1267 + if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { 1268 + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1269 + return -EINVAL; 1270 + } 1271 + track->vap_vf_cntl = ib_chunk->kdata[idx+1]; 1272 + track->immd_dwords = pkt->count - 1; 1273 + r = r100_cs_track_check(p->rdev, track); 1274 + if (r) 1275 + return r; 1276 + break; 1480 1277 /* triggers drawing using in-packet vertex data */ 1481 1278 case PACKET3_3D_DRAW_IMMD_2: 1279 + if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { 1280 + DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1281 + return -EINVAL; 1282 + } 1283 + track->vap_vf_cntl = ib_chunk->kdata[idx]; 1284 + track->immd_dwords = pkt->count; 1285 + r = r100_cs_track_check(p->rdev, track); 1286 + if (r) 1287 + return r; 1288 + break; 1482 1289 /* triggers drawing using in-packet vertex data */ 1483 1290 case PACKET3_3D_DRAW_VBUF_2: 1291 + track->vap_vf_cntl = ib_chunk->kdata[idx]; 1292 + r = r100_cs_track_check(p->rdev, track); 1293 + if (r) 1294 + return r; 1295 + break; 1484 1296 /* triggers drawing of vertex buffers setup elsewhere */ 1485 1297 case PACKET3_3D_DRAW_INDX_2: 1298 + track->vap_vf_cntl = ib_chunk->kdata[idx]; 1299 + r = r100_cs_track_check(p->rdev, track); 1300 + if (r) 1301 + return r; 1302 + break; 1486 1303 /* triggers drawing using indices to vertex buffer */ 1487 1304 case PACKET3_3D_DRAW_VBUF: 1305 + track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1306 + r = r100_cs_track_check(p->rdev, track); 1307 + if (r) 1308 + return r; 1309 + break; 1488 1310 /* triggers drawing of vertex buffers setup elsewhere */ 1489 1311 case PACKET3_3D_DRAW_INDX: 1312 + track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1313 + r = r100_cs_track_check(p->rdev, track); 1314 + if (r) 1315 + return r; 1316 + break; 1490 1317 /* triggers drawing using indices to vertex buffer */ 1491 1318 case PACKET3_NOP: 1492 1319 break; ··· 1553 1274 int r100_cs_parse(struct radeon_cs_parser *p) 1554 1275 { 1555 1276 struct radeon_cs_packet pkt; 1277 + struct r100_cs_track track; 1556 1278 int r; 1557 1279 1280 + r100_cs_track_clear(p->rdev, &track); 1281 + p->track = &track; 1558 1282 do { 1559 1283 r = r100_cs_packet_parse(p, &pkt, p->idx); 1560 1284 if (r) { ··· 1566 1284 p->idx += pkt.count + 2; 1567 1285 switch (pkt.type) { 1568 1286 case PACKET_TYPE0: 1569 - r = r100_packet0_check(p, &pkt); 1287 + if (p->rdev->family >= CHIP_R200) 1288 + r = r100_cs_parse_packet0(p, &pkt, 1289 + p->rdev->config.r100.reg_safe_bm, 1290 + p->rdev->config.r100.reg_safe_bm_size, 1291 + &r200_packet0_check); 1292 + else 1293 + r = r100_cs_parse_packet0(p, &pkt, 1294 + p->rdev->config.r100.reg_safe_bm, 1295 + p->rdev->config.r100.reg_safe_bm_size, 1296 + &r100_packet0_check); 1570 1297 break; 1571 1298 case PACKET_TYPE2: 1572 1299 break; ··· 1974 1683 1975 1684 int r100_init(struct radeon_device *rdev) 1976 1685 { 1686 + if (ASIC_IS_RN50(rdev)) { 1687 + rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 1688 + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 1689 + } else if (rdev->family < CHIP_R200) { 1690 + rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 1691 + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 1692 + } else { 1693 + return r200_init(rdev); 1694 + } 1977 1695 return 0; 1978 1696 } 1979 1697 ··· 2681 2381 2682 2382 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", 2683 2383 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 2384 + } 2385 + } 2386 + 2387 + static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2388 + { 2389 + DRM_ERROR("pitch %d\n", t->pitch); 2390 + DRM_ERROR("width %d\n", t->width); 2391 + DRM_ERROR("height %d\n", t->height); 2392 + DRM_ERROR("num levels %d\n", t->num_levels); 2393 + DRM_ERROR("depth %d\n", t->txdepth); 2394 + DRM_ERROR("bpp %d\n", t->cpp); 2395 + DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2396 + DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2397 + DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2398 + } 2399 + 2400 + static int r100_cs_track_cube(struct radeon_device *rdev, 2401 + struct r100_cs_track *track, unsigned idx) 2402 + { 2403 + unsigned face, w, h; 2404 + struct radeon_object *cube_robj; 2405 + unsigned long size; 2406 + 2407 + for (face = 0; face < 5; face++) { 2408 + cube_robj = track->textures[idx].cube_info[face].robj; 2409 + w = track->textures[idx].cube_info[face].width; 2410 + h = track->textures[idx].cube_info[face].height; 2411 + 2412 + size = w * h; 2413 + size *= track->textures[idx].cpp; 2414 + 2415 + size += track->textures[idx].cube_info[face].offset; 2416 + 2417 + if (size > radeon_object_size(cube_robj)) { 2418 + DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2419 + size, radeon_object_size(cube_robj)); 2420 + r100_cs_track_texture_print(&track->textures[idx]); 2421 + return -1; 2422 + } 2423 + } 2424 + return 0; 2425 + } 2426 + 2427 + static int r100_cs_track_texture_check(struct radeon_device *rdev, 2428 + struct r100_cs_track *track) 2429 + { 2430 + struct radeon_object *robj; 2431 + unsigned long size; 2432 + unsigned u, i, w, h; 2433 + int ret; 2434 + 2435 + for (u = 0; u < track->num_texture; u++) { 2436 + if (!track->textures[u].enabled) 2437 + continue; 2438 + robj = track->textures[u].robj; 2439 + if (robj == NULL) { 2440 + DRM_ERROR("No texture bound to unit %u\n", u); 2441 + return -EINVAL; 2442 + } 2443 + size = 0; 2444 + for (i = 0; i <= track->textures[u].num_levels; i++) { 2445 + if (track->textures[u].use_pitch) { 2446 + if (rdev->family < CHIP_R300) 2447 + w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2448 + else 2449 + w = track->textures[u].pitch / (1 << i); 2450 + } else { 2451 + w = track->textures[u].width / (1 << i); 2452 + if (rdev->family >= CHIP_RV515) 2453 + w |= track->textures[u].width_11; 2454 + if (track->textures[u].roundup_w) 2455 + w = roundup_pow_of_two(w); 2456 + } 2457 + h = track->textures[u].height / (1 << i); 2458 + if (rdev->family >= CHIP_RV515) 2459 + h |= track->textures[u].height_11; 2460 + if (track->textures[u].roundup_h) 2461 + h = roundup_pow_of_two(h); 2462 + size += w * h; 2463 + } 2464 + size *= track->textures[u].cpp; 2465 + switch (track->textures[u].tex_coord_type) { 2466 + case 0: 2467 + break; 2468 + case 1: 2469 + size *= (1 << track->textures[u].txdepth); 2470 + break; 2471 + case 2: 2472 + if (track->separate_cube) { 2473 + ret = r100_cs_track_cube(rdev, track, u); 2474 + if (ret) 2475 + return ret; 2476 + } else 2477 + size *= 6; 2478 + break; 2479 + default: 2480 + DRM_ERROR("Invalid texture coordinate type %u for unit " 2481 + "%u\n", track->textures[u].tex_coord_type, u); 2482 + return -EINVAL; 2483 + } 2484 + if (size > radeon_object_size(robj)) { 2485 + DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2486 + "%lu\n", u, size, radeon_object_size(robj)); 2487 + r100_cs_track_texture_print(&track->textures[u]); 2488 + return -EINVAL; 2489 + } 2490 + } 2491 + return 0; 2492 + } 2493 + 2494 + int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2495 + { 2496 + unsigned i; 2497 + unsigned long size; 2498 + unsigned prim_walk; 2499 + unsigned nverts; 2500 + 2501 + for (i = 0; i < track->num_cb; i++) { 2502 + if (track->cb[i].robj == NULL) { 2503 + DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2504 + return -EINVAL; 2505 + } 2506 + size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2507 + size += track->cb[i].offset; 2508 + if (size > radeon_object_size(track->cb[i].robj)) { 2509 + DRM_ERROR("[drm] Buffer too small for color buffer %d " 2510 + "(need %lu have %lu) !\n", i, size, 2511 + radeon_object_size(track->cb[i].robj)); 2512 + DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2513 + i, track->cb[i].pitch, track->cb[i].cpp, 2514 + track->cb[i].offset, track->maxy); 2515 + return -EINVAL; 2516 + } 2517 + } 2518 + if (track->z_enabled) { 2519 + if (track->zb.robj == NULL) { 2520 + DRM_ERROR("[drm] No buffer for z buffer !\n"); 2521 + return -EINVAL; 2522 + } 2523 + size = track->zb.pitch * track->zb.cpp * track->maxy; 2524 + size += track->zb.offset; 2525 + if (size > radeon_object_size(track->zb.robj)) { 2526 + DRM_ERROR("[drm] Buffer too small for z buffer " 2527 + "(need %lu have %lu) !\n", size, 2528 + radeon_object_size(track->zb.robj)); 2529 + DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2530 + track->zb.pitch, track->zb.cpp, 2531 + track->zb.offset, track->maxy); 2532 + return -EINVAL; 2533 + } 2534 + } 2535 + prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2536 + nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2537 + switch (prim_walk) { 2538 + case 1: 2539 + for (i = 0; i < track->num_arrays; i++) { 2540 + size = track->arrays[i].esize * track->max_indx * 4; 2541 + if (track->arrays[i].robj == NULL) { 2542 + DRM_ERROR("(PW %u) Vertex array %u no buffer " 2543 + "bound\n", prim_walk, i); 2544 + return -EINVAL; 2545 + } 2546 + if (size > radeon_object_size(track->arrays[i].robj)) { 2547 + DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " 2548 + "have %lu dwords\n", prim_walk, i, 2549 + size >> 2, 2550 + radeon_object_size(track->arrays[i].robj) >> 2); 2551 + DRM_ERROR("Max indices %u\n", track->max_indx); 2552 + return -EINVAL; 2553 + } 2554 + } 2555 + break; 2556 + case 2: 2557 + for (i = 0; i < track->num_arrays; i++) { 2558 + size = track->arrays[i].esize * (nverts - 1) * 4; 2559 + if (track->arrays[i].robj == NULL) { 2560 + DRM_ERROR("(PW %u) Vertex array %u no buffer " 2561 + "bound\n", prim_walk, i); 2562 + return -EINVAL; 2563 + } 2564 + if (size > radeon_object_size(track->arrays[i].robj)) { 2565 + DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " 2566 + "have %lu dwords\n", prim_walk, i, size >> 2, 2567 + radeon_object_size(track->arrays[i].robj) >> 2); 2568 + return -EINVAL; 2569 + } 2570 + } 2571 + break; 2572 + case 3: 2573 + size = track->vtx_size * nverts; 2574 + if (size != track->immd_dwords) { 2575 + DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2576 + track->immd_dwords, size); 2577 + DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2578 + nverts, track->vtx_size); 2579 + return -EINVAL; 2580 + } 2581 + break; 2582 + default: 2583 + DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2584 + prim_walk); 2585 + return -EINVAL; 2586 + } 2587 + return r100_cs_track_texture_check(rdev, track); 2588 + } 2589 + 2590 + void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2591 + { 2592 + unsigned i, face; 2593 + 2594 + if (rdev->family < CHIP_R300) { 2595 + track->num_cb = 1; 2596 + if (rdev->family <= CHIP_RS200) 2597 + track->num_texture = 3; 2598 + else 2599 + track->num_texture = 6; 2600 + track->maxy = 2048; 2601 + track->separate_cube = 1; 2602 + } else { 2603 + track->num_cb = 4; 2604 + track->num_texture = 16; 2605 + track->maxy = 4096; 2606 + track->separate_cube = 0; 2607 + } 2608 + 2609 + for (i = 0; i < track->num_cb; i++) { 2610 + track->cb[i].robj = NULL; 2611 + track->cb[i].pitch = 8192; 2612 + track->cb[i].cpp = 16; 2613 + track->cb[i].offset = 0; 2614 + } 2615 + track->z_enabled = true; 2616 + track->zb.robj = NULL; 2617 + track->zb.pitch = 8192; 2618 + track->zb.cpp = 4; 2619 + track->zb.offset = 0; 2620 + track->vtx_size = 0x7F; 2621 + track->immd_dwords = 0xFFFFFFFFUL; 2622 + track->num_arrays = 11; 2623 + track->max_indx = 0x00FFFFFFUL; 2624 + for (i = 0; i < track->num_arrays; i++) { 2625 + track->arrays[i].robj = NULL; 2626 + track->arrays[i].esize = 0x7F; 2627 + } 2628 + for (i = 0; i < track->num_texture; i++) { 2629 + track->textures[i].pitch = 16536; 2630 + track->textures[i].width = 16536; 2631 + track->textures[i].height = 16536; 2632 + track->textures[i].width_11 = 1 << 11; 2633 + track->textures[i].height_11 = 1 << 11; 2634 + track->textures[i].num_levels = 12; 2635 + if (rdev->family <= CHIP_RS200) { 2636 + track->textures[i].tex_coord_type = 0; 2637 + track->textures[i].txdepth = 0; 2638 + } else { 2639 + track->textures[i].txdepth = 16; 2640 + track->textures[i].tex_coord_type = 1; 2641 + } 2642 + track->textures[i].cpp = 64; 2643 + track->textures[i].robj = NULL; 2644 + /* CS IB emission code makes sure texture unit are disabled */ 2645 + track->textures[i].enabled = false; 2646 + track->textures[i].roundup_w = true; 2647 + track->textures[i].roundup_h = true; 2648 + if (track->separate_cube) 2649 + for (face = 0; face < 5; face++) { 2650 + track->textures[i].cube_info[face].robj = NULL; 2651 + track->textures[i].cube_info[face].width = 16536; 2652 + track->textures[i].cube_info[face].height = 16536; 2653 + track->textures[i].cube_info[face].offset = 0; 2654 + } 2684 2655 } 2685 2656 }
+124
drivers/gpu/drm/radeon/r100_track.h
··· 1 + 2 + #define R100_TRACK_MAX_TEXTURE 3 3 + #define R200_TRACK_MAX_TEXTURE 6 4 + #define R300_TRACK_MAX_TEXTURE 16 5 + 6 + #define R100_MAX_CB 1 7 + #define R300_MAX_CB 4 8 + 9 + /* 10 + * CS functions 11 + */ 12 + struct r100_cs_track_cb { 13 + struct radeon_object *robj; 14 + unsigned pitch; 15 + unsigned cpp; 16 + unsigned offset; 17 + }; 18 + 19 + struct r100_cs_track_array { 20 + struct radeon_object *robj; 21 + unsigned esize; 22 + }; 23 + 24 + struct r100_cs_cube_info { 25 + struct radeon_object *robj; 26 + unsigned offset; 27 + unsigned width; 28 + unsigned height; 29 + }; 30 + 31 + struct r100_cs_track_texture { 32 + struct radeon_object *robj; 33 + struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 34 + unsigned pitch; 35 + unsigned width; 36 + unsigned height; 37 + unsigned num_levels; 38 + unsigned cpp; 39 + unsigned tex_coord_type; 40 + unsigned txdepth; 41 + unsigned width_11; 42 + unsigned height_11; 43 + bool use_pitch; 44 + bool enabled; 45 + bool roundup_w; 46 + bool roundup_h; 47 + }; 48 + 49 + struct r100_cs_track_limits { 50 + unsigned num_cb; 51 + unsigned num_texture; 52 + unsigned max_levels; 53 + }; 54 + 55 + struct r100_cs_track { 56 + struct radeon_device *rdev; 57 + unsigned num_cb; 58 + unsigned num_texture; 59 + unsigned maxy; 60 + unsigned vtx_size; 61 + unsigned vap_vf_cntl; 62 + unsigned immd_dwords; 63 + unsigned num_arrays; 64 + unsigned max_indx; 65 + struct r100_cs_track_array arrays[11]; 66 + struct r100_cs_track_cb cb[R300_MAX_CB]; 67 + struct r100_cs_track_cb zb; 68 + struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 69 + bool z_enabled; 70 + bool separate_cube; 71 + 72 + }; 73 + 74 + int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 75 + void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 76 + int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 77 + struct radeon_cs_reloc **cs_reloc); 78 + void r100_cs_dump_packet(struct radeon_cs_parser *p, 79 + struct radeon_cs_packet *pkt); 80 + 81 + int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 82 + 83 + int r200_packet0_check(struct radeon_cs_parser *p, 84 + struct radeon_cs_packet *pkt, 85 + unsigned idx, unsigned reg); 86 + 87 + static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 88 + struct radeon_cs_packet *pkt, 89 + unsigned idx, 90 + unsigned reg) 91 + { 92 + int r; 93 + u32 tile_flags = 0; 94 + u32 tmp; 95 + struct radeon_cs_reloc *reloc; 96 + struct radeon_cs_chunk *ib_chunk; 97 + 98 + ib_chunk = &p->chunks[p->chunk_ib_idx]; 99 + 100 + r = r100_cs_packet_next_reloc(p, &reloc); 101 + if (r) { 102 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 103 + idx, reg); 104 + r100_cs_dump_packet(p, pkt); 105 + return r; 106 + } 107 + tmp = ib_chunk->kdata[idx] & 0x003fffff; 108 + tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 109 + 110 + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 111 + tile_flags |= RADEON_DST_TILE_MACRO; 112 + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 113 + if (reg == RADEON_SRC_PITCH_OFFSET) { 114 + DRM_ERROR("Cannot src blit from microtiled surface\n"); 115 + r100_cs_dump_packet(p, pkt); 116 + return -EINVAL; 117 + } 118 + tile_flags |= RADEON_DST_TILE_MICRO; 119 + } 120 + 121 + tmp |= tile_flags; 122 + p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; 123 + return 0; 124 + }
+456
drivers/gpu/drm/radeon/r200.c
··· 1 + /* 2 + * Copyright 2008 Advanced Micro Devices, Inc. 3 + * Copyright 2008 Red Hat Inc. 4 + * Copyright 2009 Jerome Glisse. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included in 14 + * all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 + * OTHER DEALINGS IN THE SOFTWARE. 23 + * 24 + * Authors: Dave Airlie 25 + * Alex Deucher 26 + * Jerome Glisse 27 + */ 28 + #include "drmP.h" 29 + #include "drm.h" 30 + #include "radeon_drm.h" 31 + #include "radeon_reg.h" 32 + #include "radeon.h" 33 + 34 + #include "r200_reg_safe.h" 35 + 36 + #include "r100_track.h" 37 + 38 + static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) 39 + { 40 + int vtx_size, i; 41 + vtx_size = 2; 42 + 43 + if (vtx_fmt_0 & R200_VTX_Z0) 44 + vtx_size++; 45 + if (vtx_fmt_0 & R200_VTX_W0) 46 + vtx_size++; 47 + /* blend weight */ 48 + if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) 49 + vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; 50 + if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) 51 + vtx_size++; 52 + if (vtx_fmt_0 & R200_VTX_N0) 53 + vtx_size += 3; 54 + if (vtx_fmt_0 & R200_VTX_POINT_SIZE) 55 + vtx_size++; 56 + if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) 57 + vtx_size++; 58 + if (vtx_fmt_0 & R200_VTX_SHININESS_0) 59 + vtx_size++; 60 + if (vtx_fmt_0 & R200_VTX_SHININESS_1) 61 + vtx_size++; 62 + for (i = 0; i < 8; i++) { 63 + int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; 64 + switch (color_size) { 65 + case 0: break; 66 + case 1: vtx_size++; break; 67 + case 2: vtx_size += 3; break; 68 + case 3: vtx_size += 4; break; 69 + } 70 + } 71 + if (vtx_fmt_0 & R200_VTX_XY1) 72 + vtx_size += 2; 73 + if (vtx_fmt_0 & R200_VTX_Z1) 74 + vtx_size++; 75 + if (vtx_fmt_0 & R200_VTX_W1) 76 + vtx_size++; 77 + if (vtx_fmt_0 & R200_VTX_N1) 78 + vtx_size += 3; 79 + return vtx_size; 80 + } 81 + 82 + static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) 83 + { 84 + int vtx_size, i, tex_size; 85 + vtx_size = 0; 86 + for (i = 0; i < 6; i++) { 87 + tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; 88 + if (tex_size > 4) 89 + continue; 90 + vtx_size += tex_size; 91 + } 92 + return vtx_size; 93 + } 94 + 95 + int r200_packet0_check(struct radeon_cs_parser *p, 96 + struct radeon_cs_packet *pkt, 97 + unsigned idx, unsigned reg) 98 + { 99 + struct radeon_cs_chunk *ib_chunk; 100 + struct radeon_cs_reloc *reloc; 101 + struct r100_cs_track *track; 102 + volatile uint32_t *ib; 103 + uint32_t tmp; 104 + int r; 105 + int i; 106 + int face; 107 + u32 tile_flags = 0; 108 + 109 + ib = p->ib->ptr; 110 + ib_chunk = &p->chunks[p->chunk_ib_idx]; 111 + track = (struct r100_cs_track *)p->track; 112 + 113 + switch (reg) { 114 + case RADEON_CRTC_GUI_TRIG_VLINE: 115 + r = r100_cs_packet_parse_vline(p); 116 + if (r) { 117 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 118 + idx, reg); 119 + r100_cs_dump_packet(p, pkt); 120 + return r; 121 + } 122 + break; 123 + /* FIXME: only allow PACKET3 blit? easier to check for out of 124 + * range access */ 125 + case RADEON_DST_PITCH_OFFSET: 126 + case RADEON_SRC_PITCH_OFFSET: 127 + r = r100_reloc_pitch_offset(p, pkt, idx, reg); 128 + if (r) 129 + return r; 130 + break; 131 + case RADEON_RB3D_DEPTHOFFSET: 132 + r = r100_cs_packet_next_reloc(p, &reloc); 133 + if (r) { 134 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 135 + idx, reg); 136 + r100_cs_dump_packet(p, pkt); 137 + return r; 138 + } 139 + track->zb.robj = reloc->robj; 140 + track->zb.offset = ib_chunk->kdata[idx]; 141 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 142 + break; 143 + case RADEON_RB3D_COLOROFFSET: 144 + r = r100_cs_packet_next_reloc(p, &reloc); 145 + if (r) { 146 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 147 + idx, reg); 148 + r100_cs_dump_packet(p, pkt); 149 + return r; 150 + } 151 + track->cb[0].robj = reloc->robj; 152 + track->cb[0].offset = ib_chunk->kdata[idx]; 153 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 154 + break; 155 + case R200_PP_TXOFFSET_0: 156 + case R200_PP_TXOFFSET_1: 157 + case R200_PP_TXOFFSET_2: 158 + case R200_PP_TXOFFSET_3: 159 + case R200_PP_TXOFFSET_4: 160 + case R200_PP_TXOFFSET_5: 161 + i = (reg - R200_PP_TXOFFSET_0) / 24; 162 + r = r100_cs_packet_next_reloc(p, &reloc); 163 + if (r) { 164 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 165 + idx, reg); 166 + r100_cs_dump_packet(p, pkt); 167 + return r; 168 + } 169 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 170 + track->textures[i].robj = reloc->robj; 171 + break; 172 + case R200_PP_CUBIC_OFFSET_F1_0: 173 + case R200_PP_CUBIC_OFFSET_F2_0: 174 + case R200_PP_CUBIC_OFFSET_F3_0: 175 + case R200_PP_CUBIC_OFFSET_F4_0: 176 + case R200_PP_CUBIC_OFFSET_F5_0: 177 + case R200_PP_CUBIC_OFFSET_F1_1: 178 + case R200_PP_CUBIC_OFFSET_F2_1: 179 + case R200_PP_CUBIC_OFFSET_F3_1: 180 + case R200_PP_CUBIC_OFFSET_F4_1: 181 + case R200_PP_CUBIC_OFFSET_F5_1: 182 + case R200_PP_CUBIC_OFFSET_F1_2: 183 + case R200_PP_CUBIC_OFFSET_F2_2: 184 + case R200_PP_CUBIC_OFFSET_F3_2: 185 + case R200_PP_CUBIC_OFFSET_F4_2: 186 + case R200_PP_CUBIC_OFFSET_F5_2: 187 + case R200_PP_CUBIC_OFFSET_F1_3: 188 + case R200_PP_CUBIC_OFFSET_F2_3: 189 + case R200_PP_CUBIC_OFFSET_F3_3: 190 + case R200_PP_CUBIC_OFFSET_F4_3: 191 + case R200_PP_CUBIC_OFFSET_F5_3: 192 + case R200_PP_CUBIC_OFFSET_F1_4: 193 + case R200_PP_CUBIC_OFFSET_F2_4: 194 + case R200_PP_CUBIC_OFFSET_F3_4: 195 + case R200_PP_CUBIC_OFFSET_F4_4: 196 + case R200_PP_CUBIC_OFFSET_F5_4: 197 + case R200_PP_CUBIC_OFFSET_F1_5: 198 + case R200_PP_CUBIC_OFFSET_F2_5: 199 + case R200_PP_CUBIC_OFFSET_F3_5: 200 + case R200_PP_CUBIC_OFFSET_F4_5: 201 + case R200_PP_CUBIC_OFFSET_F5_5: 202 + i = (reg - R200_PP_TXOFFSET_0) / 24; 203 + face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; 204 + r = r100_cs_packet_next_reloc(p, &reloc); 205 + if (r) { 206 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 207 + idx, reg); 208 + r100_cs_dump_packet(p, pkt); 209 + return r; 210 + } 211 + track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx]; 212 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 213 + track->textures[i].cube_info[face - 1].robj = reloc->robj; 214 + break; 215 + case RADEON_RE_WIDTH_HEIGHT: 216 + track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); 217 + break; 218 + case RADEON_RB3D_COLORPITCH: 219 + r = r100_cs_packet_next_reloc(p, &reloc); 220 + if (r) { 221 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 222 + idx, reg); 223 + r100_cs_dump_packet(p, pkt); 224 + return r; 225 + } 226 + 227 + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 228 + tile_flags |= RADEON_COLOR_TILE_ENABLE; 229 + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 230 + tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 231 + 232 + tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); 233 + tmp |= tile_flags; 234 + ib[idx] = tmp; 235 + 236 + track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; 237 + break; 238 + case RADEON_RB3D_DEPTHPITCH: 239 + track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; 240 + break; 241 + case RADEON_RB3D_CNTL: 242 + switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 243 + case 7: 244 + case 8: 245 + case 9: 246 + case 11: 247 + case 12: 248 + track->cb[0].cpp = 1; 249 + break; 250 + case 3: 251 + case 4: 252 + case 15: 253 + track->cb[0].cpp = 2; 254 + break; 255 + case 6: 256 + track->cb[0].cpp = 4; 257 + break; 258 + default: 259 + DRM_ERROR("Invalid color buffer format (%d) !\n", 260 + ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 261 + return -EINVAL; 262 + } 263 + if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) { 264 + DRM_ERROR("No support for depth xy offset in kms\n"); 265 + return -EINVAL; 266 + } 267 + 268 + track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); 269 + break; 270 + case RADEON_RB3D_ZSTENCILCNTL: 271 + switch (ib_chunk->kdata[idx] & 0xf) { 272 + case 0: 273 + track->zb.cpp = 2; 274 + break; 275 + case 2: 276 + case 3: 277 + case 4: 278 + case 5: 279 + case 9: 280 + case 11: 281 + track->zb.cpp = 4; 282 + break; 283 + default: 284 + break; 285 + } 286 + break; 287 + case RADEON_RB3D_ZPASS_ADDR: 288 + r = r100_cs_packet_next_reloc(p, &reloc); 289 + if (r) { 290 + DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 291 + idx, reg); 292 + r100_cs_dump_packet(p, pkt); 293 + return r; 294 + } 295 + ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); 296 + break; 297 + case RADEON_PP_CNTL: 298 + { 299 + uint32_t temp = ib_chunk->kdata[idx] >> 4; 300 + for (i = 0; i < track->num_texture; i++) 301 + track->textures[i].enabled = !!(temp & (1 << i)); 302 + } 303 + break; 304 + case RADEON_SE_VF_CNTL: 305 + track->vap_vf_cntl = ib_chunk->kdata[idx]; 306 + break; 307 + case 0x210c: 308 + /* VAP_VF_MAX_VTX_INDX */ 309 + track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; 310 + break; 311 + case R200_SE_VTX_FMT_0: 312 + track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]); 313 + break; 314 + case R200_SE_VTX_FMT_1: 315 + track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]); 316 + break; 317 + case R200_PP_TXSIZE_0: 318 + case R200_PP_TXSIZE_1: 319 + case R200_PP_TXSIZE_2: 320 + case R200_PP_TXSIZE_3: 321 + case R200_PP_TXSIZE_4: 322 + case R200_PP_TXSIZE_5: 323 + i = (reg - R200_PP_TXSIZE_0) / 32; 324 + track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; 325 + track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 326 + break; 327 + case R200_PP_TXPITCH_0: 328 + case R200_PP_TXPITCH_1: 329 + case R200_PP_TXPITCH_2: 330 + case R200_PP_TXPITCH_3: 331 + case R200_PP_TXPITCH_4: 332 + case R200_PP_TXPITCH_5: 333 + i = (reg - R200_PP_TXPITCH_0) / 32; 334 + track->textures[i].pitch = ib_chunk->kdata[idx] + 32; 335 + break; 336 + case R200_PP_TXFILTER_0: 337 + case R200_PP_TXFILTER_1: 338 + case R200_PP_TXFILTER_2: 339 + case R200_PP_TXFILTER_3: 340 + case R200_PP_TXFILTER_4: 341 + case R200_PP_TXFILTER_5: 342 + i = (reg - R200_PP_TXFILTER_0) / 32; 343 + track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK) 344 + >> R200_MAX_MIP_LEVEL_SHIFT); 345 + tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; 346 + if (tmp == 2 || tmp == 6) 347 + track->textures[i].roundup_w = false; 348 + tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; 349 + if (tmp == 2 || tmp == 6) 350 + track->textures[i].roundup_h = false; 351 + break; 352 + case R200_PP_TXMULTI_CTL_0: 353 + case R200_PP_TXMULTI_CTL_1: 354 + case R200_PP_TXMULTI_CTL_2: 355 + case R200_PP_TXMULTI_CTL_3: 356 + case R200_PP_TXMULTI_CTL_4: 357 + case R200_PP_TXMULTI_CTL_5: 358 + i = (reg - R200_PP_TXMULTI_CTL_0) / 32; 359 + break; 360 + case R200_PP_TXFORMAT_X_0: 361 + case R200_PP_TXFORMAT_X_1: 362 + case R200_PP_TXFORMAT_X_2: 363 + case R200_PP_TXFORMAT_X_3: 364 + case R200_PP_TXFORMAT_X_4: 365 + case R200_PP_TXFORMAT_X_5: 366 + i = (reg - R200_PP_TXFORMAT_X_0) / 32; 367 + track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7; 368 + tmp = (ib_chunk->kdata[idx] >> 16) & 0x3; 369 + /* 2D, 3D, CUBE */ 370 + switch (tmp) { 371 + case 0: 372 + case 5: 373 + case 6: 374 + case 7: 375 + track->textures[i].tex_coord_type = 0; 376 + break; 377 + case 1: 378 + track->textures[i].tex_coord_type = 1; 379 + break; 380 + case 2: 381 + track->textures[i].tex_coord_type = 2; 382 + break; 383 + } 384 + break; 385 + case R200_PP_TXFORMAT_0: 386 + case R200_PP_TXFORMAT_1: 387 + case R200_PP_TXFORMAT_2: 388 + case R200_PP_TXFORMAT_3: 389 + case R200_PP_TXFORMAT_4: 390 + case R200_PP_TXFORMAT_5: 391 + i = (reg - R200_PP_TXFORMAT_0) / 32; 392 + if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) { 393 + track->textures[i].use_pitch = 1; 394 + } else { 395 + track->textures[i].use_pitch = 0; 396 + track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 397 + track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 398 + } 399 + switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { 400 + case R200_TXFORMAT_I8: 401 + case R200_TXFORMAT_RGB332: 402 + case R200_TXFORMAT_Y8: 403 + track->textures[i].cpp = 1; 404 + break; 405 + case R200_TXFORMAT_DXT1: 406 + case R200_TXFORMAT_AI88: 407 + case R200_TXFORMAT_ARGB1555: 408 + case R200_TXFORMAT_RGB565: 409 + case R200_TXFORMAT_ARGB4444: 410 + case R200_TXFORMAT_VYUY422: 411 + case R200_TXFORMAT_YVYU422: 412 + case R200_TXFORMAT_LDVDU655: 413 + case R200_TXFORMAT_DVDU88: 414 + case R200_TXFORMAT_AVYU4444: 415 + track->textures[i].cpp = 2; 416 + break; 417 + case R200_TXFORMAT_ARGB8888: 418 + case R200_TXFORMAT_RGBA8888: 419 + case R200_TXFORMAT_ABGR8888: 420 + case R200_TXFORMAT_BGR111110: 421 + case R200_TXFORMAT_LDVDU8888: 422 + case R200_TXFORMAT_DXT23: 423 + case R200_TXFORMAT_DXT45: 424 + track->textures[i].cpp = 4; 425 + break; 426 + } 427 + track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); 428 + track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); 429 + break; 430 + case R200_PP_CUBIC_FACES_0: 431 + case R200_PP_CUBIC_FACES_1: 432 + case R200_PP_CUBIC_FACES_2: 433 + case R200_PP_CUBIC_FACES_3: 434 + case R200_PP_CUBIC_FACES_4: 435 + case R200_PP_CUBIC_FACES_5: 436 + tmp = ib_chunk->kdata[idx]; 437 + i = (reg - R200_PP_CUBIC_FACES_0) / 32; 438 + for (face = 0; face < 4; face++) { 439 + track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 440 + track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 441 + } 442 + break; 443 + default: 444 + printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 445 + reg, idx); 446 + return -EINVAL; 447 + } 448 + return 0; 449 + } 450 + 451 + int r200_init(struct radeon_device *rdev) 452 + { 453 + rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; 454 + rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); 455 + return 0; 456 + }
+45 -318
drivers/gpu/drm/radeon/r300.c
··· 32 32 #include "radeon.h" 33 33 #include "radeon_drm.h" 34 34 #include "radeon_share.h" 35 + #include "r100_track.h" 35 36 36 37 #include "r300_reg_safe.h" 37 38 ··· 50 49 struct radeon_cs_packet *pkt, 51 50 unsigned idx); 52 51 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 53 - int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 54 - struct radeon_cs_reloc **cs_reloc); 55 52 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 56 53 struct radeon_cs_packet *pkt, 57 54 const unsigned *auth, unsigned n, 58 55 radeon_packet0_check_t check); 59 - void r100_cs_dump_packet(struct radeon_cs_parser *p, 60 - struct radeon_cs_packet *pkt); 61 56 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 62 57 struct radeon_cs_packet *pkt, 63 58 struct radeon_object *robj); ··· 703 706 /* 704 707 * CS functions 705 708 */ 706 - struct r300_cs_track_cb { 707 - struct radeon_object *robj; 708 - unsigned pitch; 709 - unsigned cpp; 710 - unsigned offset; 711 - }; 712 - 713 - struct r300_cs_track_array { 714 - struct radeon_object *robj; 715 - unsigned esize; 716 - }; 717 - 718 - struct r300_cs_track_texture { 719 - struct radeon_object *robj; 720 - unsigned pitch; 721 - unsigned width; 722 - unsigned height; 723 - unsigned num_levels; 724 - unsigned cpp; 725 - unsigned tex_coord_type; 726 - unsigned txdepth; 727 - unsigned width_11; 728 - unsigned height_11; 729 - bool use_pitch; 730 - bool enabled; 731 - bool roundup_w; 732 - bool roundup_h; 733 - }; 734 - 735 - struct r300_cs_track { 736 - unsigned num_cb; 737 - unsigned maxy; 738 - unsigned vtx_size; 739 - unsigned vap_vf_cntl; 740 - unsigned immd_dwords; 741 - unsigned num_arrays; 742 - unsigned max_indx; 743 - struct r300_cs_track_array arrays[11]; 744 - struct r300_cs_track_cb cb[4]; 745 - struct r300_cs_track_cb zb; 746 - struct r300_cs_track_texture textures[16]; 747 - bool z_enabled; 748 - }; 749 - 750 - static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t) 751 - { 752 - DRM_ERROR("pitch %d\n", t->pitch); 753 - DRM_ERROR("width %d\n", t->width); 754 - DRM_ERROR("height %d\n", t->height); 755 - DRM_ERROR("num levels %d\n", t->num_levels); 756 - DRM_ERROR("depth %d\n", t->txdepth); 757 - DRM_ERROR("bpp %d\n", t->cpp); 758 - DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 759 - DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 760 - DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 761 - } 762 - 763 - static inline int r300_cs_track_texture_check(struct radeon_device *rdev, 764 - struct r300_cs_track *track) 765 - { 766 - struct radeon_object *robj; 767 - unsigned long size; 768 - unsigned u, i, w, h; 769 - 770 - for (u = 0; u < 16; u++) { 771 - if (!track->textures[u].enabled) 772 - continue; 773 - robj = track->textures[u].robj; 774 - if (robj == NULL) { 775 - DRM_ERROR("No texture bound to unit %u\n", u); 776 - return -EINVAL; 777 - } 778 - size = 0; 779 - for (i = 0; i <= track->textures[u].num_levels; i++) { 780 - if (track->textures[u].use_pitch) { 781 - w = track->textures[u].pitch / (1 << i); 782 - } else { 783 - w = track->textures[u].width / (1 << i); 784 - if (rdev->family >= CHIP_RV515) 785 - w |= track->textures[u].width_11; 786 - if (track->textures[u].roundup_w) 787 - w = roundup_pow_of_two(w); 788 - } 789 - h = track->textures[u].height / (1 << i); 790 - if (rdev->family >= CHIP_RV515) 791 - h |= track->textures[u].height_11; 792 - if (track->textures[u].roundup_h) 793 - h = roundup_pow_of_two(h); 794 - size += w * h; 795 - } 796 - size *= track->textures[u].cpp; 797 - switch (track->textures[u].tex_coord_type) { 798 - case 0: 799 - break; 800 - case 1: 801 - size *= (1 << track->textures[u].txdepth); 802 - break; 803 - case 2: 804 - size *= 6; 805 - break; 806 - default: 807 - DRM_ERROR("Invalid texture coordinate type %u for unit " 808 - "%u\n", track->textures[u].tex_coord_type, u); 809 - return -EINVAL; 810 - } 811 - if (size > radeon_object_size(robj)) { 812 - DRM_ERROR("Texture of unit %u needs %lu bytes but is " 813 - "%lu\n", u, size, radeon_object_size(robj)); 814 - r300_cs_track_texture_print(&track->textures[u]); 815 - return -EINVAL; 816 - } 817 - } 818 - return 0; 819 - } 820 - 821 - int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track) 822 - { 823 - unsigned i; 824 - unsigned long size; 825 - unsigned prim_walk; 826 - unsigned nverts; 827 - 828 - for (i = 0; i < track->num_cb; i++) { 829 - if (track->cb[i].robj == NULL) { 830 - DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 831 - return -EINVAL; 832 - } 833 - size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 834 - size += track->cb[i].offset; 835 - if (size > radeon_object_size(track->cb[i].robj)) { 836 - DRM_ERROR("[drm] Buffer too small for color buffer %d " 837 - "(need %lu have %lu) !\n", i, size, 838 - radeon_object_size(track->cb[i].robj)); 839 - DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 840 - i, track->cb[i].pitch, track->cb[i].cpp, 841 - track->cb[i].offset, track->maxy); 842 - return -EINVAL; 843 - } 844 - } 845 - if (track->z_enabled) { 846 - if (track->zb.robj == NULL) { 847 - DRM_ERROR("[drm] No buffer for z buffer !\n"); 848 - return -EINVAL; 849 - } 850 - size = track->zb.pitch * track->zb.cpp * track->maxy; 851 - size += track->zb.offset; 852 - if (size > radeon_object_size(track->zb.robj)) { 853 - DRM_ERROR("[drm] Buffer too small for z buffer " 854 - "(need %lu have %lu) !\n", size, 855 - radeon_object_size(track->zb.robj)); 856 - return -EINVAL; 857 - } 858 - } 859 - prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 860 - nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 861 - switch (prim_walk) { 862 - case 1: 863 - for (i = 0; i < track->num_arrays; i++) { 864 - size = track->arrays[i].esize * track->max_indx * 4; 865 - if (track->arrays[i].robj == NULL) { 866 - DRM_ERROR("(PW %u) Vertex array %u no buffer " 867 - "bound\n", prim_walk, i); 868 - return -EINVAL; 869 - } 870 - if (size > radeon_object_size(track->arrays[i].robj)) { 871 - DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " 872 - "have %lu dwords\n", prim_walk, i, 873 - size >> 2, 874 - radeon_object_size(track->arrays[i].robj) >> 2); 875 - DRM_ERROR("Max indices %u\n", track->max_indx); 876 - return -EINVAL; 877 - } 878 - } 879 - break; 880 - case 2: 881 - for (i = 0; i < track->num_arrays; i++) { 882 - size = track->arrays[i].esize * (nverts - 1) * 4; 883 - if (track->arrays[i].robj == NULL) { 884 - DRM_ERROR("(PW %u) Vertex array %u no buffer " 885 - "bound\n", prim_walk, i); 886 - return -EINVAL; 887 - } 888 - if (size > radeon_object_size(track->arrays[i].robj)) { 889 - DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " 890 - "have %lu dwords\n", prim_walk, i, size >> 2, 891 - radeon_object_size(track->arrays[i].robj) >> 2); 892 - return -EINVAL; 893 - } 894 - } 895 - break; 896 - case 3: 897 - size = track->vtx_size * nverts; 898 - if (size != track->immd_dwords) { 899 - DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 900 - track->immd_dwords, size); 901 - DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 902 - nverts, track->vtx_size); 903 - return -EINVAL; 904 - } 905 - break; 906 - default: 907 - DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 908 - prim_walk); 909 - return -EINVAL; 910 - } 911 - return r300_cs_track_texture_check(rdev, track); 912 - } 913 - 914 - static inline void r300_cs_track_clear(struct r300_cs_track *track) 915 - { 916 - unsigned i; 917 - 918 - track->num_cb = 4; 919 - track->maxy = 4096; 920 - for (i = 0; i < track->num_cb; i++) { 921 - track->cb[i].robj = NULL; 922 - track->cb[i].pitch = 8192; 923 - track->cb[i].cpp = 16; 924 - track->cb[i].offset = 0; 925 - } 926 - track->z_enabled = true; 927 - track->zb.robj = NULL; 928 - track->zb.pitch = 8192; 929 - track->zb.cpp = 4; 930 - track->zb.offset = 0; 931 - track->vtx_size = 0x7F; 932 - track->immd_dwords = 0xFFFFFFFFUL; 933 - track->num_arrays = 11; 934 - track->max_indx = 0x00FFFFFFUL; 935 - for (i = 0; i < track->num_arrays; i++) { 936 - track->arrays[i].robj = NULL; 937 - track->arrays[i].esize = 0x7F; 938 - } 939 - for (i = 0; i < 16; i++) { 940 - track->textures[i].pitch = 16536; 941 - track->textures[i].width = 16536; 942 - track->textures[i].height = 16536; 943 - track->textures[i].width_11 = 1 << 11; 944 - track->textures[i].height_11 = 1 << 11; 945 - track->textures[i].num_levels = 12; 946 - track->textures[i].txdepth = 16; 947 - track->textures[i].cpp = 64; 948 - track->textures[i].tex_coord_type = 1; 949 - track->textures[i].robj = NULL; 950 - /* CS IB emission code makes sure texture unit are disabled */ 951 - track->textures[i].enabled = false; 952 - track->textures[i].roundup_w = true; 953 - track->textures[i].roundup_h = true; 954 - } 955 - } 956 - 957 709 static int r300_packet0_check(struct radeon_cs_parser *p, 958 710 struct radeon_cs_packet *pkt, 959 711 unsigned idx, unsigned reg) 960 712 { 961 713 struct radeon_cs_chunk *ib_chunk; 962 714 struct radeon_cs_reloc *reloc; 963 - struct r300_cs_track *track; 715 + struct r100_cs_track *track; 964 716 volatile uint32_t *ib; 965 717 uint32_t tmp, tile_flags = 0; 966 718 unsigned i; ··· 717 971 718 972 ib = p->ib->ptr; 719 973 ib_chunk = &p->chunks[p->chunk_ib_idx]; 720 - track = (struct r300_cs_track*)p->track; 974 + track = (struct r100_cs_track *)p->track; 721 975 switch(reg) { 722 976 case AVIVO_D1MODE_VLINE_START_END: 723 977 case RADEON_CRTC_GUI_TRIG_VLINE: ··· 731 985 break; 732 986 case RADEON_DST_PITCH_OFFSET: 733 987 case RADEON_SRC_PITCH_OFFSET: 734 - r = r100_cs_packet_next_reloc(p, &reloc); 735 - if (r) { 736 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 737 - idx, reg); 738 - r100_cs_dump_packet(p, pkt); 988 + r = r100_reloc_pitch_offset(p, pkt, idx, reg); 989 + if (r) 739 990 return r; 740 - } 741 - tmp = ib_chunk->kdata[idx] & 0x003fffff; 742 - tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 743 - 744 - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 745 - tile_flags |= RADEON_DST_TILE_MACRO; 746 - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 747 - if (reg == RADEON_SRC_PITCH_OFFSET) { 748 - DRM_ERROR("Cannot src blit from microtiled surface\n"); 749 - r100_cs_dump_packet(p, pkt); 750 - return -EINVAL; 751 - } 752 - tile_flags |= RADEON_DST_TILE_MICRO; 753 - } 754 - tmp |= tile_flags; 755 - ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; 756 991 break; 757 992 case R300_RB3D_COLOROFFSET0: 758 993 case R300_RB3D_COLOROFFSET1: ··· 942 1215 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; 943 1216 track->textures[i].tex_coord_type = tmp; 944 1217 switch ((ib_chunk->kdata[idx] & 0x1F)) { 945 - case 0: 946 - case 2: 947 - case 5: 948 - case 18: 949 - case 20: 950 - case 21: 1218 + case R300_TX_FORMAT_X8: 1219 + case R300_TX_FORMAT_Y4X4: 1220 + case R300_TX_FORMAT_Z3Y3X2: 951 1221 track->textures[i].cpp = 1; 952 1222 break; 953 - case 1: 954 - case 3: 955 - case 6: 956 - case 7: 957 - case 10: 958 - case 11: 959 - case 19: 960 - case 22: 961 - case 24: 1223 + case R300_TX_FORMAT_X16: 1224 + case R300_TX_FORMAT_Y8X8: 1225 + case R300_TX_FORMAT_Z5Y6X5: 1226 + case R300_TX_FORMAT_Z6Y5X5: 1227 + case R300_TX_FORMAT_W4Z4Y4X4: 1228 + case R300_TX_FORMAT_W1Z5Y5X5: 1229 + case R300_TX_FORMAT_DXT1: 1230 + case R300_TX_FORMAT_D3DMFT_CxV8U8: 1231 + case R300_TX_FORMAT_B8G8_B8G8: 1232 + case R300_TX_FORMAT_G8R8_G8B8: 962 1233 track->textures[i].cpp = 2; 963 1234 break; 964 - case 4: 965 - case 8: 966 - case 9: 967 - case 12: 968 - case 13: 969 - case 23: 970 - case 25: 971 - case 27: 972 - case 30: 1235 + case R300_TX_FORMAT_Y16X16: 1236 + case R300_TX_FORMAT_Z11Y11X10: 1237 + case R300_TX_FORMAT_Z10Y11X11: 1238 + case R300_TX_FORMAT_W8Z8Y8X8: 1239 + case R300_TX_FORMAT_W2Z10Y10X10: 1240 + case 0x17: 1241 + case R300_TX_FORMAT_FL_I32: 1242 + case 0x1e: 1243 + case R300_TX_FORMAT_DXT3: 1244 + case R300_TX_FORMAT_DXT5: 973 1245 track->textures[i].cpp = 4; 974 1246 break; 975 - case 14: 976 - case 26: 977 - case 28: 1247 + case R300_TX_FORMAT_W16Z16Y16X16: 1248 + case R300_TX_FORMAT_FL_R16G16B16A16: 1249 + case R300_TX_FORMAT_FL_I32A32: 978 1250 track->textures[i].cpp = 8; 979 1251 break; 980 - case 29: 1252 + case R300_TX_FORMAT_FL_R32G32B32A32: 981 1253 track->textures[i].cpp = 16; 982 1254 break; 983 1255 default: ··· 1004 1278 case 0x443C: 1005 1279 /* TX_FILTER0_[0-15] */ 1006 1280 i = (reg - 0x4400) >> 2; 1007 - tmp = ib_chunk->kdata[idx] & 0x7;; 1281 + tmp = ib_chunk->kdata[idx] & 0x7; 1008 1282 if (tmp == 2 || tmp == 4 || tmp == 6) { 1009 1283 track->textures[i].roundup_w = false; 1010 1284 } 1011 - tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;; 1285 + tmp = (ib_chunk->kdata[idx] >> 3) & 0x7; 1012 1286 if (tmp == 2 || tmp == 4 || tmp == 6) { 1013 1287 track->textures[i].roundup_h = false; 1014 1288 } ··· 1096 1370 struct radeon_cs_packet *pkt) 1097 1371 { 1098 1372 struct radeon_cs_chunk *ib_chunk; 1373 + 1099 1374 struct radeon_cs_reloc *reloc; 1100 - struct r300_cs_track *track; 1375 + struct r100_cs_track *track; 1101 1376 volatile uint32_t *ib; 1102 1377 unsigned idx; 1103 1378 unsigned i, c; ··· 1107 1380 ib = p->ib->ptr; 1108 1381 ib_chunk = &p->chunks[p->chunk_ib_idx]; 1109 1382 idx = pkt->idx + 1; 1110 - track = (struct r300_cs_track*)p->track; 1383 + track = (struct r100_cs_track *)p->track; 1111 1384 switch(pkt->opcode) { 1112 1385 case PACKET3_3D_LOAD_VBPNTR: 1113 1386 c = ib_chunk->kdata[idx++] & 0x1F; ··· 1174 1447 } 1175 1448 track->vap_vf_cntl = ib_chunk->kdata[idx+1]; 1176 1449 track->immd_dwords = pkt->count - 1; 1177 - r = r300_cs_track_check(p->rdev, track); 1450 + r = r100_cs_track_check(p->rdev, track); 1178 1451 if (r) { 1179 1452 return r; 1180 1453 } ··· 1189 1462 } 1190 1463 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1191 1464 track->immd_dwords = pkt->count; 1192 - r = r300_cs_track_check(p->rdev, track); 1465 + r = r100_cs_track_check(p->rdev, track); 1193 1466 if (r) { 1194 1467 return r; 1195 1468 } 1196 1469 break; 1197 1470 case PACKET3_3D_DRAW_VBUF: 1198 1471 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1199 - r = r300_cs_track_check(p->rdev, track); 1472 + r = r100_cs_track_check(p->rdev, track); 1200 1473 if (r) { 1201 1474 return r; 1202 1475 } 1203 1476 break; 1204 1477 case PACKET3_3D_DRAW_VBUF_2: 1205 1478 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1206 - r = r300_cs_track_check(p->rdev, track); 1479 + r = r100_cs_track_check(p->rdev, track); 1207 1480 if (r) { 1208 1481 return r; 1209 1482 } 1210 1483 break; 1211 1484 case PACKET3_3D_DRAW_INDX: 1212 1485 track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; 1213 - r = r300_cs_track_check(p->rdev, track); 1486 + r = r100_cs_track_check(p->rdev, track); 1214 1487 if (r) { 1215 1488 return r; 1216 1489 } 1217 1490 break; 1218 1491 case PACKET3_3D_DRAW_INDX_2: 1219 1492 track->vap_vf_cntl = ib_chunk->kdata[idx]; 1220 - r = r300_cs_track_check(p->rdev, track); 1493 + r = r100_cs_track_check(p->rdev, track); 1221 1494 if (r) { 1222 1495 return r; 1223 1496 } ··· 1234 1507 int r300_cs_parse(struct radeon_cs_parser *p) 1235 1508 { 1236 1509 struct radeon_cs_packet pkt; 1237 - struct r300_cs_track track; 1510 + struct r100_cs_track track; 1238 1511 int r; 1239 1512 1240 - r300_cs_track_clear(&track); 1513 + r100_cs_track_clear(p->rdev, &track); 1241 1514 p->track = &track; 1242 1515 do { 1243 1516 r = r100_cs_packet_parse(p, &pkt, p->idx);
+6
drivers/gpu/drm/radeon/radeon.h
··· 604 604 void (*bandwidth_update)(struct radeon_device *rdev); 605 605 }; 606 606 607 + struct r100_asic { 608 + const unsigned *reg_safe_bm; 609 + unsigned reg_safe_bm_size; 610 + }; 611 + 607 612 union radeon_asic_config { 608 613 struct r300_asic r300; 614 + struct r100_asic r100; 609 615 }; 610 616 611 617
+1
drivers/gpu/drm/radeon/radeon_asic.h
··· 42 42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 43 43 */ 44 44 int r100_init(struct radeon_device *rdev); 45 + int r200_init(struct radeon_device *rdev); 45 46 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 46 47 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 47 48 void r100_errata(struct radeon_device *rdev);
+56 -1
drivers/gpu/drm/radeon/radeon_reg.h
··· 1945 1945 # define RADEON_TXFORMAT_DXT1 (12 << 0) 1946 1946 # define RADEON_TXFORMAT_DXT23 (14 << 0) 1947 1947 # define RADEON_TXFORMAT_DXT45 (15 << 0) 1948 + # define RADEON_TXFORMAT_SHADOW16 (16 << 0) 1949 + # define RADEON_TXFORMAT_SHADOW32 (17 << 0) 1950 + # define RADEON_TXFORMAT_DUDV88 (18 << 0) 1951 + # define RADEON_TXFORMAT_LDUDV655 (19 << 0) 1952 + # define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) 1948 1953 # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) 1949 1954 # define RADEON_TXFORMAT_FORMAT_SHIFT 0 1950 1955 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) ··· 2208 2203 # define RADEON_ROP_ENABLE (1 << 6) 2209 2204 # define RADEON_STENCIL_ENABLE (1 << 7) 2210 2205 # define RADEON_Z_ENABLE (1 << 8) 2211 - # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 2206 + # define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9) 2212 2207 # define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 2213 2208 2214 2209 # define RADEON_COLOR_FORMAT_ARGB1555 3 ··· 2778 2773 # define R200_TXFORMAT_DXT1 (12 << 0) 2779 2774 # define R200_TXFORMAT_DXT23 (14 << 0) 2780 2775 # define R200_TXFORMAT_DXT45 (15 << 0) 2776 + # define R200_TXFORMAT_DVDU88 (18 << 0) 2777 + # define R200_TXFORMAT_LDVDU655 (19 << 0) 2778 + # define R200_TXFORMAT_LDVDU8888 (20 << 0) 2779 + # define R200_TXFORMAT_GR1616 (21 << 0) 2781 2780 # define R200_TXFORMAT_ABGR8888 (22 << 0) 2781 + # define R200_TXFORMAT_BGR111110 (23 << 0) 2782 2782 # define R200_TXFORMAT_FORMAT_MASK (31 << 0) 2783 2783 # define R200_TXFORMAT_FORMAT_SHIFT 0 2784 2784 # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) ··· 2828 2818 #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ 2829 2819 #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ 2830 2820 2821 + #define R200_PP_CUBIC_FACES_0 0x2c18 2822 + #define R200_PP_CUBIC_FACES_1 0x2c38 2823 + #define R200_PP_CUBIC_FACES_2 0x2c58 2824 + #define R200_PP_CUBIC_FACES_3 0x2c78 2825 + #define R200_PP_CUBIC_FACES_4 0x2c98 2826 + #define R200_PP_CUBIC_FACES_5 0x2cb8 2827 + 2831 2828 #define R200_PP_TXOFFSET_0 0x2d00 2832 2829 # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) 2833 2830 # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) ··· 2846 2829 # define R200_TXO_MICRO_TILE (1 << 3) 2847 2830 # define R200_TXO_OFFSET_MASK 0xffffffe0 2848 2831 # define R200_TXO_OFFSET_SHIFT 5 2832 + #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 2833 + #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 2834 + #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 2835 + #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 2836 + #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 2837 + 2849 2838 #define R200_PP_TXOFFSET_1 0x2d18 2839 + #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 2840 + #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 2841 + #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 2842 + #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 2843 + #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 2844 + 2850 2845 #define R200_PP_TXOFFSET_2 0x2d30 2846 + #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 2847 + #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 2848 + #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 2849 + #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 2850 + #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 2851 + 2851 2852 #define R200_PP_TXOFFSET_3 0x2d48 2853 + #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 2854 + #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 2855 + #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 2856 + #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 2857 + #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 2852 2858 #define R200_PP_TXOFFSET_4 0x2d60 2859 + #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 2860 + #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 2861 + #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 2862 + #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 2863 + #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 2853 2864 #define R200_PP_TXOFFSET_5 0x2d78 2865 + #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 2866 + #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 2867 + #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 2868 + #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 2869 + #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 2854 2870 2855 2871 #define R200_PP_TFACTOR_0 0x2ee0 2856 2872 #define R200_PP_TFACTOR_1 0x2ee4 ··· 3225 3175 # define R200_FORCE_INORDER_PROC (1<<31) 3226 3176 #define R200_PP_CNTL_X 0x2cc4 3227 3177 #define R200_PP_TXMULTI_CTL_0 0x2c1c 3178 + #define R200_PP_TXMULTI_CTL_1 0x2c3c 3179 + #define R200_PP_TXMULTI_CTL_2 0x2c5c 3180 + #define R200_PP_TXMULTI_CTL_3 0x2c7c 3181 + #define R200_PP_TXMULTI_CTL_4 0x2c9c 3182 + #define R200_PP_TXMULTI_CTL_5 0x2cbc 3228 3183 #define R200_SE_VTX_STATE_CNTL 0x2180 3229 3184 # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) 3230 3185
+105
drivers/gpu/drm/radeon/reg_srcs/r100
··· 1 + r100 0x3294 2 + 0x1434 SRC_Y_X 3 + 0x1438 DST_Y_X 4 + 0x143C DST_HEIGHT_WIDTH 5 + 0x146C DP_GUI_MASTER_CNTL 6 + 0x1474 BRUSH_Y_X 7 + 0x1478 DP_BRUSH_BKGD_CLR 8 + 0x147C DP_BRUSH_FRGD_CLR 9 + 0x1480 BRUSH_DATA0 10 + 0x1484 BRUSH_DATA1 11 + 0x1598 DST_WIDTH_HEIGHT 12 + 0x15C0 CLR_CMP_CNTL 13 + 0x15C4 CLR_CMP_CLR_SRC 14 + 0x15C8 CLR_CMP_CLR_DST 15 + 0x15CC CLR_CMP_MSK 16 + 0x15D8 DP_SRC_FRGD_CLR 17 + 0x15DC DP_SRC_BKGD_CLR 18 + 0x1600 DST_LINE_START 19 + 0x1604 DST_LINE_END 20 + 0x1608 DST_LINE_PATCOUNT 21 + 0x16C0 DP_CNTL 22 + 0x16CC DP_WRITE_MSK 23 + 0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR 24 + 0x16E8 DEFAULT_SC_BOTTOM_RIGHT 25 + 0x16EC SC_TOP_LEFT 26 + 0x16F0 SC_BOTTOM_RIGHT 27 + 0x16F4 SRC_SC_BOTTOM_RIGHT 28 + 0x1714 DSTCACHE_CTLSTAT 29 + 0x1720 WAIT_UNTIL 30 + 0x172C RBBM_GUICNTL 31 + 0x1810 FOG_3D_TABLE_START 32 + 0x1814 FOG_3D_TABLE_END 33 + 0x1a14 FOG_TABLE_INDEX 34 + 0x1a18 FOG_TABLE_DATA 35 + 0x1c14 PP_MISC 36 + 0x1c18 PP_FOG_COLOR 37 + 0x1c1c RE_SOLID_COLOR 38 + 0x1c20 RB3D_BLENDCNTL 39 + 0x1c4c SE_CNTL 40 + 0x1c50 SE_COORD_FMT 41 + 0x1c60 PP_TXCBLEND_0 42 + 0x1c64 PP_TXABLEND_0 43 + 0x1c68 PP_TFACTOR_0 44 + 0x1c78 PP_TXCBLEND_1 45 + 0x1c7c PP_TXABLEND_1 46 + 0x1c80 PP_TFACTOR_1 47 + 0x1c90 PP_TXCBLEND_2 48 + 0x1c94 PP_TXABLEND_2 49 + 0x1c98 PP_TFACTOR_2 50 + 0x1cc8 RE_STIPPLE_ADDR 51 + 0x1ccc RE_STIPPLE_DATA 52 + 0x1cd0 RE_LINE_PATTERN 53 + 0x1cd4 RE_LINE_STATE 54 + 0x1d40 PP_BORDER_COLOR0 55 + 0x1d44 PP_BORDER_COLOR1 56 + 0x1d48 PP_BORDER_COLOR2 57 + 0x1d7c RB3D_STENCILREFMASK 58 + 0x1d80 RB3D_ROPCNTL 59 + 0x1d84 RB3D_PLANEMASK 60 + 0x1d98 VAP_VPORT_XSCALE 61 + 0x1d9C VAP_VPORT_XOFFSET 62 + 0x1da0 VAP_VPORT_YSCALE 63 + 0x1da4 VAP_VPORT_YOFFSET 64 + 0x1da8 VAP_VPORT_ZSCALE 65 + 0x1dac VAP_VPORT_ZOFFSET 66 + 0x1db0 SE_ZBIAS_FACTOR 67 + 0x1db4 SE_ZBIAS_CONSTANT 68 + 0x1db8 SE_LINE_WIDTH 69 + 0x2140 SE_CNTL_STATUS 70 + 0x2200 SE_TCL_VECTOR_INDX_REG 71 + 0x2204 SE_TCL_VECTOR_DATA_REG 72 + 0x2208 SE_TCL_SCALAR_INDX_REG 73 + 0x220c SE_TCL_SCALAR_DATA_REG 74 + 0x2210 SE_TCL_MATERIAL_EMISSIVE_RED 75 + 0x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN 76 + 0x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE 77 + 0x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA 78 + 0x2220 SE_TCL_MATERIAL_AMBIENT_RED 79 + 0x2224 SE_TCL_MATERIAL_AMBIENT_GREEN 80 + 0x2228 SE_TCL_MATERIAL_AMBIENT_BLUE 81 + 0x222c SE_TCL_MATERIAL_AMBIENT_ALPHA 82 + 0x2230 SE_TCL_MATERIAL_DIFFUSE_RED 83 + 0x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN 84 + 0x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE 85 + 0x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA 86 + 0x2240 SE_TCL_MATERIAL_SPECULAR_RED 87 + 0x2244 SE_TCL_MATERIAL_SPECULAR_GREEN 88 + 0x2248 SE_TCL_MATERIAL_SPECULAR_BLUE 89 + 0x224c SE_TCL_MATERIAL_SPECULAR_ALPHA 90 + 0x2250 SE_TCL_SHININESS 91 + 0x2254 SE_TCL_OUTPUT_VTX_FMT 92 + 0x2258 SE_TCL_OUTPUT_VTX_SEL 93 + 0x225c SE_TCL_MATRIX_SELECT_0 94 + 0x2260 SE_TCL_MATRIX_SELECT_1 95 + 0x2264 SE_TCL_UCP_VERT_BLEND_CNTL 96 + 0x2268 SE_TCL_TEXTURE_PROC_CTL 97 + 0x226c SE_TCL_LIGHT_MODEL_CTL 98 + 0x2270 SE_TCL_PER_LIGHT_CTL_0 99 + 0x2274 SE_TCL_PER_LIGHT_CTL_1 100 + 0x2278 SE_TCL_PER_LIGHT_CTL_2 101 + 0x227c SE_TCL_PER_LIGHT_CTL_3 102 + 0x2284 SE_TCL_STATE_FLUSH 103 + 0x26c0 RE_TOP_LEFT 104 + 0x26c4 RE_MISC 105 + 0x3290 RB3D_ZPASS_DATA
+184
drivers/gpu/drm/radeon/reg_srcs/r200
··· 1 + r200 0x3294 2 + 0x1434 SRC_Y_X 3 + 0x1438 DST_Y_X 4 + 0x143C DST_HEIGHT_WIDTH 5 + 0x146C DP_GUI_MASTER_CNTL 6 + 0x1474 BRUSH_Y_X 7 + 0x1478 DP_BRUSH_BKGD_CLR 8 + 0x147C DP_BRUSH_FRGD_CLR 9 + 0x1480 BRUSH_DATA0 10 + 0x1484 BRUSH_DATA1 11 + 0x1598 DST_WIDTH_HEIGHT 12 + 0x15C0 CLR_CMP_CNTL 13 + 0x15C4 CLR_CMP_CLR_SRC 14 + 0x15C8 CLR_CMP_CLR_DST 15 + 0x15CC CLR_CMP_MSK 16 + 0x15D8 DP_SRC_FRGD_CLR 17 + 0x15DC DP_SRC_BKGD_CLR 18 + 0x1600 DST_LINE_START 19 + 0x1604 DST_LINE_END 20 + 0x1608 DST_LINE_PATCOUNT 21 + 0x16C0 DP_CNTL 22 + 0x16CC DP_WRITE_MSK 23 + 0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR 24 + 0x16E8 DEFAULT_SC_BOTTOM_RIGHT 25 + 0x16EC SC_TOP_LEFT 26 + 0x16F0 SC_BOTTOM_RIGHT 27 + 0x16F4 SRC_SC_BOTTOM_RIGHT 28 + 0x1714 DSTCACHE_CTLSTAT 29 + 0x1720 WAIT_UNTIL 30 + 0x172C RBBM_GUICNTL 31 + 0x1c14 PP_MISC 32 + 0x1c18 PP_FOG_COLOR 33 + 0x1c1c RE_SOLID_COLOR 34 + 0x1c20 RB3D_BLENDCNTL 35 + 0x1c4c SE_CNTL 36 + 0x1c50 RE_CNTL 37 + 0x1cc8 RE_STIPPLE_ADDR 38 + 0x1ccc RE_STIPPLE_DATA 39 + 0x1cd0 RE_LINE_PATTERN 40 + 0x1cd4 RE_LINE_STATE 41 + 0x1cd8 RE_SCISSOR_TL_0 42 + 0x1cdc RE_SCISSOR_BR_0 43 + 0x1ce0 RE_SCISSOR_TL_1 44 + 0x1ce4 RE_SCISSOR_BR_1 45 + 0x1ce8 RE_SCISSOR_TL_2 46 + 0x1cec RE_SCISSOR_BR_2 47 + 0x1d60 RB3D_DEPTHXY_OFFSET 48 + 0x1d7c RB3D_STENCILREFMASK 49 + 0x1d80 RB3D_ROPCNTL 50 + 0x1d84 RB3D_PLANEMASK 51 + 0x1d98 VAP_VPORT_XSCALE 52 + 0x1d9c VAP_VPORT_XOFFSET 53 + 0x1da0 VAP_VPORT_YSCALE 54 + 0x1da4 VAP_VPORT_YOFFSET 55 + 0x1da8 VAP_VPORT_ZSCALE 56 + 0x1dac VAP_VPORT_ZOFFSET 57 + 0x1db0 SE_ZBIAS_FACTOR 58 + 0x1db4 SE_ZBIAS_CONSTANT 59 + 0x1db8 SE_LINE_WIDTH 60 + 0x2080 SE_VAP_CNTL 61 + 0x2090 SE_TCL_OUTPUT_VTX_FMT_0 62 + 0x2094 SE_TCL_OUTPUT_VTX_FMT_1 63 + 0x20b0 SE_VTE_CNTL 64 + 0x2140 SE_CNTL_STATUS 65 + 0x2180 SE_VTX_STATE_CNTL 66 + 0x2200 SE_TCL_VECTOR_INDX_REG 67 + 0x2204 SE_TCL_VECTOR_DATA_REG 68 + 0x2208 SE_TCL_SCALAR_INDX_REG 69 + 0x220c SE_TCL_SCALAR_DATA_REG 70 + 0x2230 SE_TCL_MATRIX_SEL_0 71 + 0x2234 SE_TCL_MATRIX_SEL_1 72 + 0x2238 SE_TCL_MATRIX_SEL_2 73 + 0x223c SE_TCL_MATRIX_SEL_3 74 + 0x2240 SE_TCL_MATRIX_SEL_4 75 + 0x2250 SE_TCL_OUTPUT_VTX_COMP_SEL 76 + 0x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0 77 + 0x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1 78 + 0x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2 79 + 0x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3 80 + 0x2268 SE_TCL_LIGHT_MODEL_CTL_0 81 + 0x226c SE_TCL_LIGHT_MODEL_CTL_1 82 + 0x2270 SE_TCL_PER_LIGHT_CTL_0 83 + 0x2274 SE_TCL_PER_LIGHT_CTL_1 84 + 0x2278 SE_TCL_PER_LIGHT_CTL_2 85 + 0x227c SE_TCL_PER_LIGHT_CTL_3 86 + 0x2284 VAP_PVS_STATE_FLUSH_REG 87 + 0x22a8 SE_TCL_TEX_PROC_CTL_2 88 + 0x22ac SE_TCL_TEX_PROC_CTL_3 89 + 0x22b0 SE_TCL_TEX_PROC_CTL_0 90 + 0x22b4 SE_TCL_TEX_PROC_CTL_1 91 + 0x22b8 SE_TCL_TEX_CYL_WRAP_CTL 92 + 0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL 93 + 0x22c4 SE_TCL_POINT_SPRITE_CNTL 94 + 0x2648 RE_POINTSIZE 95 + 0x26c0 RE_TOP_LEFT 96 + 0x26c4 RE_MISC 97 + 0x26f0 RE_AUX_SCISSOR_CNTL 98 + 0x2c14 PP_BORDER_COLOR_0 99 + 0x2c34 PP_BORDER_COLOR_1 100 + 0x2c54 PP_BORDER_COLOR_2 101 + 0x2c74 PP_BORDER_COLOR_3 102 + 0x2c94 PP_BORDER_COLOR_4 103 + 0x2cb4 PP_BORDER_COLOR_5 104 + 0x2cc4 PP_CNTL_X 105 + 0x2cf8 PP_TRI_PERF 106 + 0x2cfc PP_PERF_CNTL 107 + 0x2d9c PP_TAM_DEBUG3 108 + 0x2ee0 PP_TFACTOR_0 109 + 0x2ee4 PP_TFACTOR_1 110 + 0x2ee8 PP_TFACTOR_2 111 + 0x2eec PP_TFACTOR_3 112 + 0x2ef0 PP_TFACTOR_4 113 + 0x2ef4 PP_TFACTOR_5 114 + 0x2ef8 PP_TFACTOR_6 115 + 0x2efc PP_TFACTOR_7 116 + 0x2f00 PP_TXCBLEND_0 117 + 0x2f04 PP_TXCBLEND2_0 118 + 0x2f08 PP_TXABLEND_0 119 + 0x2f0c PP_TXABLEND2_0 120 + 0x2f10 PP_TXCBLEND_1 121 + 0x2f14 PP_TXCBLEND2_1 122 + 0x2f18 PP_TXABLEND_1 123 + 0x2f1c PP_TXABLEND2_1 124 + 0x2f20 PP_TXCBLEND_2 125 + 0x2f24 PP_TXCBLEND2_2 126 + 0x2f28 PP_TXABLEND_2 127 + 0x2f2c PP_TXABLEND2_2 128 + 0x2f30 PP_TXCBLEND_3 129 + 0x2f34 PP_TXCBLEND2_3 130 + 0x2f38 PP_TXABLEND_3 131 + 0x2f3c PP_TXABLEND2_3 132 + 0x2f40 PP_TXCBLEND_4 133 + 0x2f44 PP_TXCBLEND2_4 134 + 0x2f48 PP_TXABLEND_4 135 + 0x2f4c PP_TXABLEND2_4 136 + 0x2f50 PP_TXCBLEND_5 137 + 0x2f54 PP_TXCBLEND2_5 138 + 0x2f58 PP_TXABLEND_5 139 + 0x2f5c PP_TXABLEND2_5 140 + 0x2f60 PP_TXCBLEND_6 141 + 0x2f64 PP_TXCBLEND2_6 142 + 0x2f68 PP_TXABLEND_6 143 + 0x2f6c PP_TXABLEND2_6 144 + 0x2f70 PP_TXCBLEND_7 145 + 0x2f74 PP_TXCBLEND2_7 146 + 0x2f78 PP_TXABLEND_7 147 + 0x2f7c PP_TXABLEND2_7 148 + 0x2f80 PP_TXCBLEND_8 149 + 0x2f84 PP_TXCBLEND2_8 150 + 0x2f88 PP_TXABLEND_8 151 + 0x2f8c PP_TXABLEND2_8 152 + 0x2f90 PP_TXCBLEND_9 153 + 0x2f94 PP_TXCBLEND2_9 154 + 0x2f98 PP_TXABLEND_9 155 + 0x2f9c PP_TXABLEND2_9 156 + 0x2fa0 PP_TXCBLEND_10 157 + 0x2fa4 PP_TXCBLEND2_10 158 + 0x2fa8 PP_TXABLEND_10 159 + 0x2fac PP_TXABLEND2_10 160 + 0x2fb0 PP_TXCBLEND_11 161 + 0x2fb4 PP_TXCBLEND2_11 162 + 0x2fb8 PP_TXABLEND_11 163 + 0x2fbc PP_TXABLEND2_11 164 + 0x2fc0 PP_TXCBLEND_12 165 + 0x2fc4 PP_TXCBLEND2_12 166 + 0x2fc8 PP_TXABLEND_12 167 + 0x2fcc PP_TXABLEND2_12 168 + 0x2fd0 PP_TXCBLEND_13 169 + 0x2fd4 PP_TXCBLEND2_13 170 + 0x2fd8 PP_TXABLEND_13 171 + 0x2fdc PP_TXABLEND2_13 172 + 0x2fe0 PP_TXCBLEND_14 173 + 0x2fe4 PP_TXCBLEND2_14 174 + 0x2fe8 PP_TXABLEND_14 175 + 0x2fec PP_TXABLEND2_14 176 + 0x2ff0 PP_TXCBLEND_15 177 + 0x2ff4 PP_TXCBLEND2_15 178 + 0x2ff8 PP_TXABLEND_15 179 + 0x2ffc PP_TXABLEND2_15 180 + 0x3218 RB3D_BLENCOLOR 181 + 0x321c RB3D_ABLENDCNTL 182 + 0x3220 RB3D_CBLENDCNTL 183 + 0x3290 RB3D_ZPASS_DATA 184 +
+30
drivers/gpu/drm/radeon/reg_srcs/rn50
··· 1 + rn50 0x3294 2 + 0x1434 SRC_Y_X 3 + 0x1438 DST_Y_X 4 + 0x143C DST_HEIGHT_WIDTH 5 + 0x146C DP_GUI_MASTER_CNTL 6 + 0x1474 BRUSH_Y_X 7 + 0x1478 DP_BRUSH_BKGD_CLR 8 + 0x147C DP_BRUSH_FRGD_CLR 9 + 0x1480 BRUSH_DATA0 10 + 0x1484 BRUSH_DATA1 11 + 0x1598 DST_WIDTH_HEIGHT 12 + 0x15C0 CLR_CMP_CNTL 13 + 0x15C4 CLR_CMP_CLR_SRC 14 + 0x15C8 CLR_CMP_CLR_DST 15 + 0x15CC CLR_CMP_MSK 16 + 0x15D8 DP_SRC_FRGD_CLR 17 + 0x15DC DP_SRC_BKGD_CLR 18 + 0x1600 DST_LINE_START 19 + 0x1604 DST_LINE_END 20 + 0x1608 DST_LINE_PATCOUNT 21 + 0x16C0 DP_CNTL 22 + 0x16CC DP_WRITE_MSK 23 + 0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR 24 + 0x16E8 DEFAULT_SC_BOTTOM_RIGHT 25 + 0x16EC SC_TOP_LEFT 26 + 0x16F0 SC_BOTTOM_RIGHT 27 + 0x16F4 SRC_SC_BOTTOM_RIGHT 28 + 0x1714 DSTCACHE_CTLSTAT 29 + 0x1720 WAIT_UNTIL 30 + 0x172C RBBM_GUICNTL