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dt-bindings: interrupt-controller: Convert brcm,bcm2835-armctrl-ic to DT schema
Convert the Broadcom BCM2835 ARMCTRL interrupt controller binding to
schema format. It's a straight-forward conversion of the typical
interrupt controller.
Link: https://lore.kernel.org/r/20250505144618.1287539-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
+162
-131
-131
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
-131
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
···
1
-
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
2
-
3
-
The BCM2835 contains a custom top-level interrupt controller, which supports
4
-
72 interrupt sources using a 2-level register scheme. The interrupt
5
-
controller, or the HW block containing it, is referred to occasionally
6
-
as "armctrl" in the SoC documentation, hence naming of this binding.
7
-
8
-
The BCM2836 contains the same interrupt controller with the same
9
-
interrupts, but the per-CPU interrupt controller is the root, and an
10
-
interrupt there indicates that the ARMCTRL has an interrupt to handle.
11
-
12
-
Required properties:
13
-
14
-
- compatible : should be "brcm,bcm2835-armctrl-ic" or
15
-
"brcm,bcm2836-armctrl-ic"
16
-
- reg : Specifies base physical address and size of the registers.
17
-
- interrupt-controller : Identifies the node as an interrupt controller
18
-
- #interrupt-cells : Specifies the number of cells needed to encode an
19
-
interrupt source. The value shall be 2.
20
-
21
-
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
22
-
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
23
-
1/2" register.
24
-
25
-
The 2nd cell contains the interrupt number within the bank. Valid values
26
-
are 0..7 for bank 0, and 0..31 for bank 1.
27
-
28
-
Additional required properties for brcm,bcm2836-armctrl-ic:
29
-
- interrupts : Specifies the interrupt on the parent for this interrupt
30
-
controller to handle.
31
-
32
-
The interrupt sources are as follows:
33
-
34
-
Bank 0:
35
-
0: ARM_TIMER
36
-
1: ARM_MAILBOX
37
-
2: ARM_DOORBELL_0
38
-
3: ARM_DOORBELL_1
39
-
4: VPU0_HALTED
40
-
5: VPU1_HALTED
41
-
6: ILLEGAL_TYPE0
42
-
7: ILLEGAL_TYPE1
43
-
44
-
Bank 1:
45
-
0: TIMER0
46
-
1: TIMER1
47
-
2: TIMER2
48
-
3: TIMER3
49
-
4: CODEC0
50
-
5: CODEC1
51
-
6: CODEC2
52
-
7: VC_JPEG
53
-
8: ISP
54
-
9: VC_USB
55
-
10: VC_3D
56
-
11: TRANSPOSER
57
-
12: MULTICORESYNC0
58
-
13: MULTICORESYNC1
59
-
14: MULTICORESYNC2
60
-
15: MULTICORESYNC3
61
-
16: DMA0
62
-
17: DMA1
63
-
18: VC_DMA2
64
-
19: VC_DMA3
65
-
20: DMA4
66
-
21: DMA5
67
-
22: DMA6
68
-
23: DMA7
69
-
24: DMA8
70
-
25: DMA9
71
-
26: DMA10
72
-
27: DMA11-14 - shared interrupt for DMA 11 to 14
73
-
28: DMAALL - triggers on all dma interrupts (including channel 15)
74
-
29: AUX
75
-
30: ARM
76
-
31: VPUDMA
77
-
78
-
Bank 2:
79
-
0: HOSTPORT
80
-
1: VIDEOSCALER
81
-
2: CCP2TX
82
-
3: SDC
83
-
4: DSI0
84
-
5: AVE
85
-
6: CAM0
86
-
7: CAM1
87
-
8: HDMI0
88
-
9: HDMI1
89
-
10: PIXELVALVE1
90
-
11: I2CSPISLV
91
-
12: DSI1
92
-
13: PWA0
93
-
14: PWA1
94
-
15: CPR
95
-
16: SMI
96
-
17: GPIO0
97
-
18: GPIO1
98
-
19: GPIO2
99
-
20: GPIO3
100
-
21: VC_I2C
101
-
22: VC_SPI
102
-
23: VC_I2SPCM
103
-
24: VC_SDIO
104
-
25: VC_UART
105
-
26: SLIMBUS
106
-
27: VEC
107
-
28: CPG
108
-
29: RNG
109
-
30: VC_ARASANSDIO
110
-
31: AVSPMON
111
-
112
-
Example:
113
-
114
-
/* BCM2835, first level */
115
-
intc: interrupt-controller {
116
-
compatible = "brcm,bcm2835-armctrl-ic";
117
-
reg = <0x7e00b200 0x200>;
118
-
interrupt-controller;
119
-
#interrupt-cells = <2>;
120
-
};
121
-
122
-
/* BCM2836, second level */
123
-
intc: interrupt-controller {
124
-
compatible = "brcm,bcm2836-armctrl-ic";
125
-
reg = <0x7e00b200 0x200>;
126
-
interrupt-controller;
127
-
#interrupt-cells = <2>;
128
-
129
-
interrupt-parent = <&local_intc>;
130
-
interrupts = <8>;
131
-
};
+162
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml
+162
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml
···
1
+
%YAML 1.2
2
+
---
3
+
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml#
4
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
5
+
6
+
title: BCM2835 ARMCTRL Interrupt Controller
7
+
8
+
maintainers:
9
+
- Florian Fainelli <florian.fainelli@broadcom.com>
10
+
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
11
+
12
+
description: >
13
+
The BCM2835 contains a custom top-level interrupt controller, which supports
14
+
72 interrupt sources using a 2-level register scheme. The interrupt
15
+
controller, or the HW block containing it, is referred to occasionally as
16
+
"armctrl" in the SoC documentation, hence naming of this binding.
17
+
18
+
The BCM2836 contains the same interrupt controller with the same interrupts,
19
+
but the per-CPU interrupt controller is the root, and an interrupt there
20
+
indicates that the ARMCTRL has an interrupt to handle.
21
+
22
+
The interrupt sources are as follows:
23
+
24
+
Bank 0:
25
+
0: ARM_TIMER
26
+
1: ARM_MAILBOX
27
+
2: ARM_DOORBELL_0
28
+
3: ARM_DOORBELL_1
29
+
4: VPU0_HALTED
30
+
5: VPU1_HALTED
31
+
6: ILLEGAL_TYPE0
32
+
7: ILLEGAL_TYPE1
33
+
34
+
Bank 1:
35
+
0: TIMER0
36
+
1: TIMER1
37
+
2: TIMER2
38
+
3: TIMER3
39
+
4: CODEC0
40
+
5: CODEC1
41
+
6: CODEC2
42
+
7: VC_JPEG
43
+
8: ISP
44
+
9: VC_USB
45
+
10: VC_3D
46
+
11: TRANSPOSER
47
+
12: MULTICORESYNC0
48
+
13: MULTICORESYNC1
49
+
14: MULTICORESYNC2
50
+
15: MULTICORESYNC3
51
+
16: DMA0
52
+
17: DMA1
53
+
18: VC_DMA2
54
+
19: VC_DMA3
55
+
20: DMA4
56
+
21: DMA5
57
+
22: DMA6
58
+
23: DMA7
59
+
24: DMA8
60
+
25: DMA9
61
+
26: DMA10
62
+
27: DMA11-14 - shared interrupt for DMA 11 to 14
63
+
28: DMAALL - triggers on all dma interrupts (including channel 15)
64
+
29: AUX
65
+
30: ARM
66
+
31: VPUDMA
67
+
68
+
Bank 2:
69
+
0: HOSTPORT
70
+
1: VIDEOSCALER
71
+
2: CCP2TX
72
+
3: SDC
73
+
4: DSI0
74
+
5: AVE
75
+
6: CAM0
76
+
7: CAM1
77
+
8: HDMI0
78
+
9: HDMI1
79
+
10: PIXELVALVE1
80
+
11: I2CSPISLV
81
+
12: DSI1
82
+
13: PWA0
83
+
14: PWA1
84
+
15: CPR
85
+
16: SMI
86
+
17: GPIO0
87
+
18: GPIO1
88
+
19: GPIO2
89
+
20: GPIO3
90
+
21: VC_I2C
91
+
22: VC_SPI
92
+
23: VC_I2SPCM
93
+
24: VC_SDIO
94
+
25: VC_UART
95
+
26: SLIMBUS
96
+
27: VEC
97
+
28: CPG
98
+
29: RNG
99
+
30: VC_ARASANSDIO
100
+
31: AVSPMON
101
+
102
+
properties:
103
+
compatible:
104
+
enum:
105
+
- brcm,bcm2835-armctrl-ic
106
+
- brcm,bcm2836-armctrl-ic
107
+
108
+
reg:
109
+
maxItems: 1
110
+
111
+
interrupt-controller: true
112
+
113
+
'#interrupt-cells':
114
+
const: 2
115
+
description: >
116
+
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
117
+
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
118
+
1/2" register.
119
+
120
+
The 2nd cell contains the interrupt number within the bank. Valid values
121
+
are 0..7 for bank 0, and 0..31 for bank 1.
122
+
123
+
interrupts:
124
+
maxItems: 1
125
+
126
+
required:
127
+
- compatible
128
+
- reg
129
+
- interrupt-controller
130
+
- '#interrupt-cells'
131
+
132
+
allOf:
133
+
- if:
134
+
properties:
135
+
compatible:
136
+
contains:
137
+
const: brcm,bcm2836-armctrl-ic
138
+
then:
139
+
required:
140
+
- interrupts
141
+
else:
142
+
properties:
143
+
interrupts: false
144
+
145
+
additionalProperties: false
146
+
147
+
examples:
148
+
- |
149
+
interrupt-controller@7e00b200 {
150
+
compatible = "brcm,bcm2835-armctrl-ic";
151
+
reg = <0x7e00b200 0x200>;
152
+
interrupt-controller;
153
+
#interrupt-cells = <2>;
154
+
};
155
+
- |
156
+
interrupt-controller@7e00b200 {
157
+
compatible = "brcm,bcm2836-armctrl-ic";
158
+
reg = <0x7e00b200 0x200>;
159
+
interrupt-controller;
160
+
#interrupt-cells = <2>;
161
+
interrupts = <8>;
162
+
};