tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

powerpc/fsl: Use new clockgen binding

The driver retains compatibility with old device trees, but we don't
want the old nodes lying around to be copied, or used as a reference
(some of the mux options are incorrect), or even just being clutter.

Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
[scottwood: removed sysclk node added by Andy]
Signed-off-by: Scott Wood <oss@buserror.net>

Scott Wood 54877957 0deae39c

+50 -409
+2 -2
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
··· 70 70 cpu0: PowerPC,e6500@0 { 71 71 device_type = "cpu"; 72 72 reg = <0 1>; 73 - clocks = <&mux0>; 73 + clocks = <&clockgen 1 0>; 74 74 next-level-cache = <&L2_1>; 75 75 fsl,portid-mapping = <0x80000000>; 76 76 }; 77 77 cpu1: PowerPC,e6500@2 { 78 78 device_type = "cpu"; 79 79 reg = <2 3>; 80 - clocks = <&mux0>; 80 + clocks = <&clockgen 1 0>; 81 81 next-level-cache = <&L2_1>; 82 82 fsl,portid-mapping = <0x80000000>; 83 83 };
+4 -4
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
··· 75 75 cpu0: PowerPC,e6500@0 { 76 76 device_type = "cpu"; 77 77 reg = <0 1>; 78 - clocks = <&mux0>; 78 + clocks = <&clockgen 1 0>; 79 79 next-level-cache = <&L2_1>; 80 80 fsl,portid-mapping = <0x80000000>; 81 81 }; 82 82 cpu1: PowerPC,e6500@2 { 83 83 device_type = "cpu"; 84 84 reg = <2 3>; 85 - clocks = <&mux0>; 85 + clocks = <&clockgen 1 0>; 86 86 next-level-cache = <&L2_1>; 87 87 fsl,portid-mapping = <0x80000000>; 88 88 }; 89 89 cpu2: PowerPC,e6500@4 { 90 90 device_type = "cpu"; 91 91 reg = <4 5>; 92 - clocks = <&mux0>; 92 + clocks = <&clockgen 1 0>; 93 93 next-level-cache = <&L2_1>; 94 94 fsl,portid-mapping = <0x80000000>; 95 95 }; 96 96 cpu3: PowerPC,e6500@6 { 97 97 device_type = "cpu"; 98 98 reg = <6 7>; 99 - clocks = <&mux0>; 99 + clocks = <&clockgen 1 0>; 100 100 next-level-cache = <&L2_1>; 101 101 fsl,portid-mapping = <0x80000000>; 102 102 };
-15
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
··· 398 398 }; 399 399 400 400 /include/ "qoriq-clockgen2.dtsi" 401 - clockgen: global-utilities@e1000 { 402 - compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0"; 403 - reg = <0xe1000 0x1000>; 404 - 405 - mux0: mux0@0 { 406 - #clock-cells = <0>; 407 - reg = <0x0 0x4>; 408 - compatible = "fsl,qoriq-core-mux-2.0"; 409 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 410 - <&pll1 0>, <&pll1 1>, <&pll1 2>; 411 - clock-names = "pll0", "pll0-div2", "pll0-div4", 412 - "pll1", "pll1-div2", "pll1-div4"; 413 - clock-output-names = "cmux0"; 414 - }; 415 - }; 416 401 417 402 rcpm: global-utilities@e2000 { 418 403 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
-18
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
··· 327 327 /include/ "qoriq-clockgen1.dtsi" 328 328 global-utilities@e1000 { 329 329 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; 330 - 331 - mux2: mux2@40 { 332 - #clock-cells = <0>; 333 - reg = <0x40 0x4>; 334 - compatible = "fsl,qoriq-core-mux-1.0"; 335 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 336 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 337 - clock-output-names = "cmux2"; 338 - }; 339 - 340 - mux3: mux3@60 { 341 - #clock-cells = <0>; 342 - reg = <0x60 0x4>; 343 - compatible = "fsl,qoriq-core-mux-1.0"; 344 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 345 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 346 - clock-output-names = "cmux3"; 347 - }; 348 330 }; 349 331 350 332 rcpm: global-utilities@e2000 {
+4 -4
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
··· 89 89 cpu0: PowerPC,e500mc@0 { 90 90 device_type = "cpu"; 91 91 reg = <0>; 92 - clocks = <&mux0>; 92 + clocks = <&clockgen 1 0>; 93 93 next-level-cache = <&L2_0>; 94 94 fsl,portid-mapping = <0x80000000>; 95 95 L2_0: l2-cache { ··· 99 99 cpu1: PowerPC,e500mc@1 { 100 100 device_type = "cpu"; 101 101 reg = <1>; 102 - clocks = <&mux1>; 102 + clocks = <&clockgen 1 1>; 103 103 next-level-cache = <&L2_1>; 104 104 fsl,portid-mapping = <0x40000000>; 105 105 L2_1: l2-cache { ··· 109 109 cpu2: PowerPC,e500mc@2 { 110 110 device_type = "cpu"; 111 111 reg = <2>; 112 - clocks = <&mux2>; 112 + clocks = <&clockgen 1 2>; 113 113 next-level-cache = <&L2_2>; 114 114 fsl,portid-mapping = <0x20000000>; 115 115 L2_2: l2-cache { ··· 119 119 cpu3: PowerPC,e500mc@3 { 120 120 device_type = "cpu"; 121 121 reg = <3>; 122 - clocks = <&mux3>; 122 + clocks = <&clockgen 1 3>; 123 123 next-level-cache = <&L2_3>; 124 124 fsl,portid-mapping = <0x10000000>; 125 125 L2_3: l2-cache {
-18
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
··· 354 354 /include/ "qoriq-clockgen1.dtsi" 355 355 global-utilities@e1000 { 356 356 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; 357 - 358 - mux2: mux2@40 { 359 - #clock-cells = <0>; 360 - reg = <0x40 0x4>; 361 - compatible = "fsl,qoriq-core-mux-1.0"; 362 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 363 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 364 - clock-output-names = "cmux2"; 365 - }; 366 - 367 - mux3: mux3@60 { 368 - #clock-cells = <0>; 369 - reg = <0x60 0x4>; 370 - compatible = "fsl,qoriq-core-mux-1.0"; 371 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 372 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 373 - clock-output-names = "cmux3"; 374 - }; 375 357 }; 376 358 377 359 rcpm: global-utilities@e2000 {
+4 -4
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
··· 90 90 cpu0: PowerPC,e500mc@0 { 91 91 device_type = "cpu"; 92 92 reg = <0>; 93 - clocks = <&mux0>; 93 + clocks = <&clockgen 1 0>; 94 94 next-level-cache = <&L2_0>; 95 95 fsl,portid-mapping = <0x80000000>; 96 96 L2_0: l2-cache { ··· 100 100 cpu1: PowerPC,e500mc@1 { 101 101 device_type = "cpu"; 102 102 reg = <1>; 103 - clocks = <&mux1>; 103 + clocks = <&clockgen 1 1>; 104 104 next-level-cache = <&L2_1>; 105 105 fsl,portid-mapping = <0x40000000>; 106 106 L2_1: l2-cache { ··· 110 110 cpu2: PowerPC,e500mc@2 { 111 111 device_type = "cpu"; 112 112 reg = <2>; 113 - clocks = <&mux2>; 113 + clocks = <&clockgen 1 2>; 114 114 next-level-cache = <&L2_2>; 115 115 fsl,portid-mapping = <0x20000000>; 116 116 L2_2: l2-cache { ··· 120 120 cpu3: PowerPC,e500mc@3 { 121 121 device_type = "cpu"; 122 122 reg = <3>; 123 - clocks = <&mux3>; 123 + clocks = <&clockgen 1 3>; 124 124 next-level-cache = <&L2_3>; 125 125 fsl,portid-mapping = <0x10000000>; 126 126 L2_3: l2-cache {
-70
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
··· 374 374 /include/ "qoriq-clockgen1.dtsi" 375 375 global-utilities@e1000 { 376 376 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; 377 - 378 - pll2: pll2@840 { 379 - #clock-cells = <1>; 380 - reg = <0x840 0x4>; 381 - compatible = "fsl,qoriq-core-pll-1.0"; 382 - clocks = <&sysclk>; 383 - clock-output-names = "pll2", "pll2-div2"; 384 - }; 385 - 386 - pll3: pll3@860 { 387 - #clock-cells = <1>; 388 - reg = <0x860 0x4>; 389 - compatible = "fsl,qoriq-core-pll-1.0"; 390 - clocks = <&sysclk>; 391 - clock-output-names = "pll3", "pll3-div2"; 392 - }; 393 - 394 - mux2: mux2@40 { 395 - #clock-cells = <0>; 396 - reg = <0x40 0x4>; 397 - compatible = "fsl,qoriq-core-mux-1.0"; 398 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 399 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 400 - clock-output-names = "cmux2"; 401 - }; 402 - 403 - mux3: mux3@60 { 404 - #clock-cells = <0>; 405 - reg = <0x60 0x4>; 406 - compatible = "fsl,qoriq-core-mux-1.0"; 407 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 408 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 409 - clock-output-names = "cmux3"; 410 - }; 411 - 412 - mux4: mux4@80 { 413 - #clock-cells = <0>; 414 - reg = <0x80 0x4>; 415 - compatible = "fsl,qoriq-core-mux-1.0"; 416 - clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 417 - clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 418 - clock-output-names = "cmux4"; 419 - }; 420 - 421 - mux5: mux5@a0 { 422 - #clock-cells = <0>; 423 - reg = <0xa0 0x4>; 424 - compatible = "fsl,qoriq-core-mux-1.0"; 425 - clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 426 - clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 427 - clock-output-names = "cmux5"; 428 - }; 429 - 430 - mux6: mux6@c0 { 431 - #clock-cells = <0>; 432 - reg = <0xc0 0x4>; 433 - compatible = "fsl,qoriq-core-mux-1.0"; 434 - clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 435 - clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 436 - clock-output-names = "cmux6"; 437 - }; 438 - 439 - mux7: mux7@e0 { 440 - #clock-cells = <0>; 441 - reg = <0xe0 0x4>; 442 - compatible = "fsl,qoriq-core-mux-1.0"; 443 - clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>; 444 - clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2"; 445 - clock-output-names = "cmux7"; 446 - }; 447 377 }; 448 378 449 379 rcpm: global-utilities@e2000 {
+8 -8
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
··· 94 94 cpu0: PowerPC,e500mc@0 { 95 95 device_type = "cpu"; 96 96 reg = <0>; 97 - clocks = <&mux0>; 97 + clocks = <&clockgen 1 0>; 98 98 next-level-cache = <&L2_0>; 99 99 fsl,portid-mapping = <0x80000000>; 100 100 L2_0: l2-cache { ··· 104 104 cpu1: PowerPC,e500mc@1 { 105 105 device_type = "cpu"; 106 106 reg = <1>; 107 - clocks = <&mux1>; 107 + clocks = <&clockgen 1 1>; 108 108 next-level-cache = <&L2_1>; 109 109 fsl,portid-mapping = <0x40000000>; 110 110 L2_1: l2-cache { ··· 114 114 cpu2: PowerPC,e500mc@2 { 115 115 device_type = "cpu"; 116 116 reg = <2>; 117 - clocks = <&mux2>; 117 + clocks = <&clockgen 1 2>; 118 118 next-level-cache = <&L2_2>; 119 119 fsl,portid-mapping = <0x20000000>; 120 120 L2_2: l2-cache { ··· 124 124 cpu3: PowerPC,e500mc@3 { 125 125 device_type = "cpu"; 126 126 reg = <3>; 127 - clocks = <&mux3>; 127 + clocks = <&clockgen 1 3>; 128 128 next-level-cache = <&L2_3>; 129 129 fsl,portid-mapping = <0x10000000>; 130 130 L2_3: l2-cache { ··· 134 134 cpu4: PowerPC,e500mc@4 { 135 135 device_type = "cpu"; 136 136 reg = <4>; 137 - clocks = <&mux4>; 137 + clocks = <&clockgen 1 4>; 138 138 next-level-cache = <&L2_4>; 139 139 fsl,portid-mapping = <0x08000000>; 140 140 L2_4: l2-cache { ··· 144 144 cpu5: PowerPC,e500mc@5 { 145 145 device_type = "cpu"; 146 146 reg = <5>; 147 - clocks = <&mux5>; 147 + clocks = <&clockgen 1 5>; 148 148 next-level-cache = <&L2_5>; 149 149 fsl,portid-mapping = <0x04000000>; 150 150 L2_5: l2-cache { ··· 154 154 cpu6: PowerPC,e500mc@6 { 155 155 device_type = "cpu"; 156 156 reg = <6>; 157 - clocks = <&mux6>; 157 + clocks = <&clockgen 1 6>; 158 158 next-level-cache = <&L2_6>; 159 159 fsl,portid-mapping = <0x02000000>; 160 160 L2_6: l2-cache { ··· 164 164 cpu7: PowerPC,e500mc@7 { 165 165 device_type = "cpu"; 166 166 reg = <7>; 167 - clocks = <&mux7>; 167 + clocks = <&clockgen 1 7>; 168 168 next-level-cache = <&L2_7>; 169 169 fsl,portid-mapping = <0x01000000>; 170 170 L2_7: l2-cache {
+2 -2
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
··· 96 96 cpu0: PowerPC,e5500@0 { 97 97 device_type = "cpu"; 98 98 reg = <0>; 99 - clocks = <&mux0>; 99 + clocks = <&clockgen 1 0>; 100 100 next-level-cache = <&L2_0>; 101 101 fsl,portid-mapping = <0x80000000>; 102 102 L2_0: l2-cache { ··· 106 106 cpu1: PowerPC,e5500@1 { 107 107 device_type = "cpu"; 108 108 reg = <1>; 109 - clocks = <&mux1>; 109 + clocks = <&clockgen 1 1>; 110 110 next-level-cache = <&L2_1>; 111 111 fsl,portid-mapping = <0x40000000>; 112 112 L2_1: l2-cache {
-18
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
··· 319 319 /include/ "qoriq-clockgen1.dtsi" 320 320 global-utilities@e1000 { 321 321 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; 322 - 323 - mux2: mux2@40 { 324 - #clock-cells = <0>; 325 - reg = <0x40 0x4>; 326 - compatible = "fsl,qoriq-core-mux-1.0"; 327 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 328 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 329 - clock-output-names = "cmux2"; 330 - }; 331 - 332 - mux3: mux3@60 { 333 - #clock-cells = <0>; 334 - reg = <0x60 0x4>; 335 - compatible = "fsl,qoriq-core-mux-1.0"; 336 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 337 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 338 - clock-output-names = "cmux3"; 339 - }; 340 322 }; 341 323 342 324 rcpm: global-utilities@e2000 {
+4 -4
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
··· 102 102 cpu0: PowerPC,e5500@0 { 103 103 device_type = "cpu"; 104 104 reg = <0>; 105 - clocks = <&mux0>; 105 + clocks = <&clockgen 1 0>; 106 106 next-level-cache = <&L2_0>; 107 107 fsl,portid-mapping = <0x80000000>; 108 108 L2_0: l2-cache { ··· 112 112 cpu1: PowerPC,e5500@1 { 113 113 device_type = "cpu"; 114 114 reg = <1>; 115 - clocks = <&mux1>; 115 + clocks = <&clockgen 1 1>; 116 116 next-level-cache = <&L2_1>; 117 117 fsl,portid-mapping = <0x40000000>; 118 118 L2_1: l2-cache { ··· 122 122 cpu2: PowerPC,e5500@2 { 123 123 device_type = "cpu"; 124 124 reg = <2>; 125 - clocks = <&mux2>; 125 + clocks = <&clockgen 1 2>; 126 126 next-level-cache = <&L2_2>; 127 127 fsl,portid-mapping = <0x20000000>; 128 128 L2_2: l2-cache { ··· 132 132 cpu3: PowerPC,e5500@3 { 133 133 device_type = "cpu"; 134 134 reg = <3>; 135 - clocks = <&mux3>; 135 + clocks = <&clockgen 1 3>; 136 136 next-level-cache = <&L2_3>; 137 137 fsl,portid-mapping = <0x10000000>; 138 138 L2_3: l2-cache {
-47
arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
··· 34 34 35 35 clockgen: global-utilities@e1000 { 36 36 compatible = "fsl,qoriq-clockgen-1.0"; 37 - ranges = <0x0 0xe1000 0x1000>; 38 37 reg = <0xe1000 0x1000>; 39 - clock-frequency = <0>; 40 - #address-cells = <1>; 41 - #size-cells = <1>; 42 38 #clock-cells = <2>; 43 - 44 - sysclk: sysclk { 45 - #clock-cells = <0>; 46 - compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock"; 47 - clock-output-names = "sysclk"; 48 - }; 49 - pll0: pll0@800 { 50 - #clock-cells = <1>; 51 - reg = <0x800 0x4>; 52 - compatible = "fsl,qoriq-core-pll-1.0"; 53 - clocks = <&sysclk>; 54 - clock-output-names = "pll0", "pll0-div2"; 55 - }; 56 - pll1: pll1@820 { 57 - #clock-cells = <1>; 58 - reg = <0x820 0x4>; 59 - compatible = "fsl,qoriq-core-pll-1.0"; 60 - clocks = <&sysclk>; 61 - clock-output-names = "pll1", "pll1-div2"; 62 - }; 63 - mux0: mux0@0 { 64 - #clock-cells = <0>; 65 - reg = <0x0 0x4>; 66 - compatible = "fsl,qoriq-core-mux-1.0"; 67 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 68 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 69 - clock-output-names = "cmux0"; 70 - }; 71 - mux1: mux1@20 { 72 - #clock-cells = <0>; 73 - reg = <0x20 0x4>; 74 - compatible = "fsl,qoriq-core-mux-1.0"; 75 - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 76 - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 77 - clock-output-names = "cmux1"; 78 - }; 79 - platform_pll: platform-pll@c00 { 80 - #clock-cells = <1>; 81 - reg = <0xc00 0x4>; 82 - compatible = "fsl,qoriq-platform-pll-1.0"; 83 - clocks = <&sysclk>; 84 - clock-output-names = "platform-pll", "platform-pll-div2"; 85 - }; 86 39 };
-30
arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
··· 34 34 35 35 clockgen: global-utilities@e1000 { 36 36 compatible = "fsl,qoriq-clockgen-2.0"; 37 - ranges = <0x0 0xe1000 0x1000>; 38 37 reg = <0xe1000 0x1000>; 39 - #address-cells = <1>; 40 - #size-cells = <1>; 41 38 #clock-cells = <2>; 42 - 43 - sysclk: sysclk { 44 - #clock-cells = <0>; 45 - compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock"; 46 - clock-output-names = "sysclk"; 47 - }; 48 - pll0: pll0@800 { 49 - #clock-cells = <1>; 50 - reg = <0x800 0x4>; 51 - compatible = "fsl,qoriq-core-pll-2.0"; 52 - clocks = <&sysclk>; 53 - clock-output-names = "pll0", "pll0-div2", "pll0-div4"; 54 - }; 55 - pll1: pll1@820 { 56 - #clock-cells = <1>; 57 - reg = <0x820 0x4>; 58 - compatible = "fsl,qoriq-core-pll-2.0"; 59 - clocks = <&sysclk>; 60 - clock-output-names = "pll1", "pll1-div2", "pll1-div4"; 61 - }; 62 - platform_pll: platform-pll@c00 { 63 - #clock-cells = <1>; 64 - reg = <0xc00 0x4>; 65 - compatible = "fsl,qoriq-platform-pll-2.0"; 66 - clocks = <&sysclk>; 67 - clock-output-names = "platform-pll", "platform-pll-div2"; 68 - }; 69 39 };
-16
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
··· 345 345 /include/ "qoriq-clockgen2.dtsi" 346 346 global-utilities@e1000 { 347 347 compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0"; 348 - mux0: mux0@0 { 349 - #clock-cells = <0>; 350 - reg = <0x0 4>; 351 - compatible = "fsl,core-mux-clock"; 352 - clocks = <&pll0 0>, <&pll0 1>; 353 - clock-names = "pll0_0", "pll0_1"; 354 - clock-output-names = "cmux0"; 355 - }; 356 - mux1: mux1@20 { 357 - #clock-cells = <0>; 358 - reg = <0x20 4>; 359 - compatible = "fsl,core-mux-clock"; 360 - clocks = <&pll0 0>, <&pll0 1>; 361 - clock-names = "pll0_0", "pll0_1"; 362 - clock-output-names = "cmux1"; 363 - }; 364 348 }; 365 349 366 350 rcpm: global-utilities@e2000 {
+2 -2
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
··· 74 74 cpu0: PowerPC,e5500@0 { 75 75 device_type = "cpu"; 76 76 reg = <0>; 77 - clocks = <&mux0>; 77 + clocks = <&clockgen 1 0>; 78 78 next-level-cache = <&L2_1>; 79 79 #cooling-cells = <2>; 80 80 L2_1: l2-cache { ··· 84 84 cpu1: PowerPC,e5500@1 { 85 85 device_type = "cpu"; 86 86 reg = <1>; 87 - clocks = <&mux1>; 87 + clocks = <&clockgen 1 1>; 88 88 next-level-cache = <&L2_2>; 89 89 #cooling-cells = <2>; 90 90 L2_2: l2-cache {
-44
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
··· 425 425 /include/ "qoriq-clockgen2.dtsi" 426 426 global-utilities@e1000 { 427 427 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; 428 - 429 - mux0: mux0@0 { 430 - #clock-cells = <0>; 431 - reg = <0x0 4>; 432 - compatible = "fsl,qoriq-core-mux-2.0"; 433 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 434 - <&pll1 0>, <&pll1 1>, <&pll1 2>; 435 - clock-names = "pll0", "pll0-div2", "pll1-div4", 436 - "pll1", "pll1-div2", "pll1-div4"; 437 - clock-output-names = "cmux0"; 438 - }; 439 - 440 - mux1: mux1@20 { 441 - #clock-cells = <0>; 442 - reg = <0x20 4>; 443 - compatible = "fsl,qoriq-core-mux-2.0"; 444 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 445 - <&pll1 0>, <&pll1 1>, <&pll1 2>; 446 - clock-names = "pll0", "pll0-div2", "pll1-div4", 447 - "pll1", "pll1-div2", "pll1-div4"; 448 - clock-output-names = "cmux1"; 449 - }; 450 - 451 - mux2: mux2@40 { 452 - #clock-cells = <0>; 453 - reg = <0x40 4>; 454 - compatible = "fsl,qoriq-core-mux-2.0"; 455 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 456 - <&pll1 0>, <&pll1 1>, <&pll1 2>; 457 - clock-names = "pll0", "pll0-div2", "pll1-div4", 458 - "pll1", "pll1-div2", "pll1-div4"; 459 - clock-output-names = "cmux2"; 460 - }; 461 - 462 - mux3: mux3@60 { 463 - #clock-cells = <0>; 464 - reg = <0x60 4>; 465 - compatible = "fsl,qoriq-core-mux-2.0"; 466 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 467 - <&pll1 0>, <&pll1 1>, <&pll1 2>; 468 - clock-names = "pll0_0", "pll0_1", "pll0_2", 469 - "pll1_0", "pll1_1", "pll1_2"; 470 - clock-output-names = "cmux3"; 471 - }; 472 428 }; 473 429 474 430 rcpm: global-utilities@e2000 {
+4 -4
arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
··· 74 74 cpu0: PowerPC,e5500@0 { 75 75 device_type = "cpu"; 76 76 reg = <0>; 77 - clocks = <&mux0>; 77 + clocks = <&clockgen 1 0>; 78 78 next-level-cache = <&L2_1>; 79 79 #cooling-cells = <2>; 80 80 L2_1: l2-cache { ··· 84 84 cpu1: PowerPC,e5500@1 { 85 85 device_type = "cpu"; 86 86 reg = <1>; 87 - clocks = <&mux1>; 87 + clocks = <&clockgen 1 1>; 88 88 next-level-cache = <&L2_2>; 89 89 #cooling-cells = <2>; 90 90 L2_2: l2-cache { ··· 94 94 cpu2: PowerPC,e5500@2 { 95 95 device_type = "cpu"; 96 96 reg = <2>; 97 - clocks = <&mux2>; 97 + clocks = <&clockgen 1 2>; 98 98 next-level-cache = <&L2_3>; 99 99 #cooling-cells = <2>; 100 100 L2_3: l2-cache { ··· 104 104 cpu3: PowerPC,e5500@3 { 105 105 device_type = "cpu"; 106 106 reg = <3>; 107 - clocks = <&mux3>; 107 + clocks = <&clockgen 1 3>; 108 108 next-level-cache = <&L2_4>; 109 109 #cooling-cells = <2>; 110 110 L2_4: l2-cache {
-22
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
··· 535 535 /include/ "qoriq-clockgen2.dtsi" 536 536 global-utilities@e1000 { 537 537 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0"; 538 - 539 - mux0: mux0@0 { 540 - #clock-cells = <0>; 541 - reg = <0x0 4>; 542 - compatible = "fsl,qoriq-core-mux-2.0"; 543 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 544 - <&pll1 0>, <&pll1 1>, <&pll1 2>; 545 - clock-names = "pll0", "pll0-div2", "pll0-div4", 546 - "pll1", "pll1-div2", "pll1-div4"; 547 - clock-output-names = "cmux0"; 548 - }; 549 - 550 - mux1: mux1@20 { 551 - #clock-cells = <0>; 552 - reg = <0x20 4>; 553 - compatible = "fsl,qoriq-core-mux-2.0"; 554 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 555 - <&pll1 0>, <&pll1 1>, <&pll1 2>; 556 - clock-names = "pll0", "pll0-div2", "pll0-div4", 557 - "pll1", "pll1-div2", "pll1-div4"; 558 - clock-output-names = "cmux1"; 559 - }; 560 538 }; 561 539 562 540 rcpm: global-utilities@e2000 {
+4 -4
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
··· 81 81 cpu0: PowerPC,e6500@0 { 82 82 device_type = "cpu"; 83 83 reg = <0 1>; 84 - clocks = <&mux0>; 84 + clocks = <&clockgen 1 0>; 85 85 next-level-cache = <&L2_1>; 86 86 fsl,portid-mapping = <0x80000000>; 87 87 }; 88 88 cpu1: PowerPC,e6500@2 { 89 89 device_type = "cpu"; 90 90 reg = <2 3>; 91 - clocks = <&mux0>; 91 + clocks = <&clockgen 1 0>; 92 92 next-level-cache = <&L2_1>; 93 93 fsl,portid-mapping = <0x80000000>; 94 94 }; 95 95 cpu2: PowerPC,e6500@4 { 96 96 device_type = "cpu"; 97 97 reg = <4 5>; 98 - clocks = <&mux0>; 98 + clocks = <&clockgen 1 0>; 99 99 next-level-cache = <&L2_1>; 100 100 fsl,portid-mapping = <0x80000000>; 101 101 }; 102 102 cpu3: PowerPC,e6500@6 { 103 103 device_type = "cpu"; 104 104 reg = <6 7>; 105 - clocks = <&mux0>; 105 + clocks = <&clockgen 1 0>; 106 106 next-level-cache = <&L2_1>; 107 107 fsl,portid-mapping = <0x80000000>; 108 108 };
-61
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
··· 950 950 /include/ "qoriq-clockgen2.dtsi" 951 951 global-utilities@e1000 { 952 952 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; 953 - 954 - pll2: pll2@840 { 955 - #clock-cells = <1>; 956 - reg = <0x840 0x4>; 957 - compatible = "fsl,qoriq-core-pll-2.0"; 958 - clocks = <&sysclk>; 959 - clock-output-names = "pll2", "pll2-div2", "pll2-div4"; 960 - }; 961 - 962 - pll3: pll3@860 { 963 - #clock-cells = <1>; 964 - reg = <0x860 0x4>; 965 - compatible = "fsl,qoriq-core-pll-2.0"; 966 - clocks = <&sysclk>; 967 - clock-output-names = "pll3", "pll3-div2", "pll3-div4"; 968 - }; 969 - 970 - pll4: pll4@880 { 971 - #clock-cells = <1>; 972 - reg = <0x880 0x4>; 973 - compatible = "fsl,qoriq-core-pll-2.0"; 974 - clocks = <&sysclk>; 975 - clock-output-names = "pll4", "pll4-div2", "pll4-div4"; 976 - }; 977 - 978 - mux0: mux0@0 { 979 - #clock-cells = <0>; 980 - reg = <0x0 0x4>; 981 - compatible = "fsl,qoriq-core-mux-2.0"; 982 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 983 - <&pll1 0>, <&pll1 1>, <&pll1 2>, 984 - <&pll2 0>, <&pll2 1>, <&pll2 2>; 985 - clock-names = "pll0", "pll0-div2", "pll0-div4", 986 - "pll1", "pll1-div2", "pll1-div4", 987 - "pll2", "pll2-div2", "pll2-div4"; 988 - clock-output-names = "cmux0"; 989 - }; 990 - 991 - mux1: mux1@20 { 992 - #clock-cells = <0>; 993 - reg = <0x20 0x4>; 994 - compatible = "fsl,qoriq-core-mux-2.0"; 995 - clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, 996 - <&pll1 0>, <&pll1 1>, <&pll1 2>, 997 - <&pll2 0>, <&pll2 1>, <&pll2 2>; 998 - clock-names = "pll0", "pll0-div2", "pll0-div4", 999 - "pll1", "pll1-div2", "pll1-div4", 1000 - "pll2", "pll2-div2", "pll2-div4"; 1001 - clock-output-names = "cmux1"; 1002 - }; 1003 - 1004 - mux2: mux2@40 { 1005 - #clock-cells = <0>; 1006 - reg = <0x40 0x4>; 1007 - compatible = "fsl,qoriq-core-mux-2.0"; 1008 - clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, 1009 - <&pll4 0>, <&pll4 1>, <&pll4 2>; 1010 - clock-names = "pll3", "pll3-div2", "pll3-div4", 1011 - "pll4", "pll4-div2", "pll4-div4"; 1012 - clock-output-names = "cmux2"; 1013 - }; 1014 953 }; 1015 954 1016 955 rcpm: global-utilities@e2000 {
+12 -12
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
··· 90 90 cpu0: PowerPC,e6500@0 { 91 91 device_type = "cpu"; 92 92 reg = <0 1>; 93 - clocks = <&mux0>; 93 + clocks = <&clockgen 1 0>; 94 94 next-level-cache = <&L2_1>; 95 95 fsl,portid-mapping = <0x80000000>; 96 96 }; 97 97 cpu1: PowerPC,e6500@2 { 98 98 device_type = "cpu"; 99 99 reg = <2 3>; 100 - clocks = <&mux0>; 100 + clocks = <&clockgen 1 0>; 101 101 next-level-cache = <&L2_1>; 102 102 fsl,portid-mapping = <0x80000000>; 103 103 }; 104 104 cpu2: PowerPC,e6500@4 { 105 105 device_type = "cpu"; 106 106 reg = <4 5>; 107 - clocks = <&mux0>; 107 + clocks = <&clockgen 1 0>; 108 108 next-level-cache = <&L2_1>; 109 109 fsl,portid-mapping = <0x80000000>; 110 110 }; 111 111 cpu3: PowerPC,e6500@6 { 112 112 device_type = "cpu"; 113 113 reg = <6 7>; 114 - clocks = <&mux0>; 114 + clocks = <&clockgen 1 0>; 115 115 next-level-cache = <&L2_1>; 116 116 fsl,portid-mapping = <0x80000000>; 117 117 }; 118 118 cpu4: PowerPC,e6500@8 { 119 119 device_type = "cpu"; 120 120 reg = <8 9>; 121 - clocks = <&mux1>; 121 + clocks = <&clockgen 1 1>; 122 122 next-level-cache = <&L2_2>; 123 123 fsl,portid-mapping = <0x40000000>; 124 124 }; 125 125 cpu5: PowerPC,e6500@10 { 126 126 device_type = "cpu"; 127 127 reg = <10 11>; 128 - clocks = <&mux1>; 128 + clocks = <&clockgen 1 1>; 129 129 next-level-cache = <&L2_2>; 130 130 fsl,portid-mapping = <0x40000000>; 131 131 }; 132 132 cpu6: PowerPC,e6500@12 { 133 133 device_type = "cpu"; 134 134 reg = <12 13>; 135 - clocks = <&mux1>; 135 + clocks = <&clockgen 1 1>; 136 136 next-level-cache = <&L2_2>; 137 137 fsl,portid-mapping = <0x40000000>; 138 138 }; 139 139 cpu7: PowerPC,e6500@14 { 140 140 device_type = "cpu"; 141 141 reg = <14 15>; 142 - clocks = <&mux1>; 142 + clocks = <&clockgen 1 1>; 143 143 next-level-cache = <&L2_2>; 144 144 fsl,portid-mapping = <0x40000000>; 145 145 }; 146 146 cpu8: PowerPC,e6500@16 { 147 147 device_type = "cpu"; 148 148 reg = <16 17>; 149 - clocks = <&mux2>; 149 + clocks = <&clockgen 1 2>; 150 150 next-level-cache = <&L2_3>; 151 151 fsl,portid-mapping = <0x20000000>; 152 152 }; 153 153 cpu9: PowerPC,e6500@18 { 154 154 device_type = "cpu"; 155 155 reg = <18 19>; 156 - clocks = <&mux2>; 156 + clocks = <&clockgen 1 2>; 157 157 next-level-cache = <&L2_3>; 158 158 fsl,portid-mapping = <0x20000000>; 159 159 }; 160 160 cpu10: PowerPC,e6500@20 { 161 161 device_type = "cpu"; 162 162 reg = <20 21>; 163 - clocks = <&mux2>; 163 + clocks = <&clockgen 1 2>; 164 164 next-level-cache = <&L2_3>; 165 165 fsl,portid-mapping = <0x20000000>; 166 166 }; 167 167 cpu11: PowerPC,e6500@22 { 168 168 device_type = "cpu"; 169 169 reg = <22 23>; 170 - clocks = <&mux2>; 170 + clocks = <&clockgen 1 2>; 171 171 next-level-cache = <&L2_3>; 172 172 fsl,portid-mapping = <0x20000000>; 173 173 };