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kernel
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linux
interconnect: qcom: sm8250: convert to dynamic IDs
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-rework-icc-v3-6-0575304c9624@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Georgi Djakov
543f5fcb
4de68f33
+361
-543
+361
-375
drivers/interconnect/qcom/sm8250.c
+361
-375
drivers/interconnect/qcom/sm8250.c
···
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#include "bcm-voter.h"
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#include "icc-rpmh.h"
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#include "sm8250.h"
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static struct qcom_icc_node qhm_a1noc_cfg;
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static struct qcom_icc_node qhm_qspi;
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static struct qcom_icc_node qhm_qup1;
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static struct qcom_icc_node qhm_qup2;
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static struct qcom_icc_node qhm_tsif;
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static struct qcom_icc_node xm_pcie3_modem;
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static struct qcom_icc_node xm_sdc4;
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static struct qcom_icc_node xm_ufs_mem;
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static struct qcom_icc_node xm_usb3_0;
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static struct qcom_icc_node xm_usb3_1;
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static struct qcom_icc_node qhm_a2noc_cfg;
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static struct qcom_icc_node qhm_qdss_bam;
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static struct qcom_icc_node qhm_qup0;
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static struct qcom_icc_node qnm_cnoc;
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static struct qcom_icc_node qxm_crypto;
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static struct qcom_icc_node qxm_ipa;
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static struct qcom_icc_node xm_pcie3_0;
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static struct qcom_icc_node xm_pcie3_1;
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static struct qcom_icc_node xm_qdss_etr;
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static struct qcom_icc_node xm_sdc2;
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static struct qcom_icc_node xm_ufs_card;
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static struct qcom_icc_node qnm_npu;
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static struct qcom_icc_node qnm_snoc;
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static struct qcom_icc_node xm_qdss_dap;
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static struct qcom_icc_node qhm_cnoc_dc_noc;
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static struct qcom_icc_node alm_gpu_tcu;
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static struct qcom_icc_node alm_sys_tcu;
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static struct qcom_icc_node chm_apps;
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static struct qcom_icc_node qhm_gemnoc_cfg;
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static struct qcom_icc_node qnm_cmpnoc;
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static struct qcom_icc_node qnm_gpu;
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static struct qcom_icc_node qnm_mnoc_hf;
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static struct qcom_icc_node qnm_mnoc_sf;
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static struct qcom_icc_node qnm_pcie;
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static struct qcom_icc_node qnm_snoc_gc;
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static struct qcom_icc_node qnm_snoc_sf;
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static struct qcom_icc_node llcc_mc;
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static struct qcom_icc_node qhm_mnoc_cfg;
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static struct qcom_icc_node qnm_camnoc_hf;
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static struct qcom_icc_node qnm_camnoc_icp;
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static struct qcom_icc_node qnm_camnoc_sf;
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static struct qcom_icc_node qnm_video0;
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static struct qcom_icc_node qnm_video1;
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static struct qcom_icc_node qnm_video_cvp;
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static struct qcom_icc_node qxm_mdp0;
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static struct qcom_icc_node qxm_mdp1;
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static struct qcom_icc_node qxm_rot;
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static struct qcom_icc_node amm_npu_sys;
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static struct qcom_icc_node amm_npu_sys_cdp_w;
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static struct qcom_icc_node qhm_cfg;
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static struct qcom_icc_node qhm_snoc_cfg;
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static struct qcom_icc_node qnm_aggre1_noc;
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static struct qcom_icc_node qnm_aggre2_noc;
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static struct qcom_icc_node qnm_gemnoc;
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static struct qcom_icc_node qnm_gemnoc_pcie;
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static struct qcom_icc_node qxm_pimem;
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static struct qcom_icc_node xm_gic;
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static struct qcom_icc_node qns_a1noc_snoc;
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static struct qcom_icc_node qns_pcie_modem_mem_noc;
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static struct qcom_icc_node srvc_aggre1_noc;
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static struct qcom_icc_node qns_a2noc_snoc;
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static struct qcom_icc_node qns_pcie_mem_noc;
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static struct qcom_icc_node srvc_aggre2_noc;
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static struct qcom_icc_node qns_cdsp_mem_noc;
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static struct qcom_icc_node qhs_a1_noc_cfg;
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static struct qcom_icc_node qhs_a2_noc_cfg;
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static struct qcom_icc_node qhs_ahb2phy0;
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static struct qcom_icc_node qhs_ahb2phy1;
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static struct qcom_icc_node qhs_aoss;
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static struct qcom_icc_node qhs_camera_cfg;
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static struct qcom_icc_node qhs_clk_ctl;
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static struct qcom_icc_node qhs_compute_dsp;
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static struct qcom_icc_node qhs_cpr_cx;
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static struct qcom_icc_node qhs_cpr_mmcx;
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static struct qcom_icc_node qhs_cpr_mx;
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static struct qcom_icc_node qhs_crypto0_cfg;
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static struct qcom_icc_node qhs_cx_rdpm;
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static struct qcom_icc_node qhs_dcc_cfg;
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static struct qcom_icc_node qhs_ddrss_cfg;
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static struct qcom_icc_node qhs_display_cfg;
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static struct qcom_icc_node qhs_gpuss_cfg;
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static struct qcom_icc_node qhs_imem_cfg;
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static struct qcom_icc_node qhs_ipa;
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static struct qcom_icc_node qhs_ipc_router;
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static struct qcom_icc_node qhs_lpass_cfg;
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static struct qcom_icc_node qhs_mnoc_cfg;
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static struct qcom_icc_node qhs_npu_cfg;
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static struct qcom_icc_node qhs_pcie0_cfg;
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static struct qcom_icc_node qhs_pcie1_cfg;
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static struct qcom_icc_node qhs_pcie_modem_cfg;
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static struct qcom_icc_node qhs_pdm;
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static struct qcom_icc_node qhs_pimem_cfg;
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static struct qcom_icc_node qhs_prng;
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static struct qcom_icc_node qhs_qdss_cfg;
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static struct qcom_icc_node qhs_qspi;
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static struct qcom_icc_node qhs_qup0;
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static struct qcom_icc_node qhs_qup1;
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static struct qcom_icc_node qhs_qup2;
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static struct qcom_icc_node qhs_sdc2;
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static struct qcom_icc_node qhs_sdc4;
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static struct qcom_icc_node qhs_snoc_cfg;
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static struct qcom_icc_node qhs_tcsr;
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static struct qcom_icc_node qhs_tlmm0;
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static struct qcom_icc_node qhs_tlmm1;
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static struct qcom_icc_node qhs_tlmm2;
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static struct qcom_icc_node qhs_tsif;
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static struct qcom_icc_node qhs_ufs_card_cfg;
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static struct qcom_icc_node qhs_ufs_mem_cfg;
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static struct qcom_icc_node qhs_usb3_0;
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static struct qcom_icc_node qhs_usb3_1;
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static struct qcom_icc_node qhs_venus_cfg;
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static struct qcom_icc_node qhs_vsense_ctrl_cfg;
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static struct qcom_icc_node qns_cnoc_a2noc;
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static struct qcom_icc_node srvc_cnoc;
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static struct qcom_icc_node qhs_llcc;
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static struct qcom_icc_node qhs_memnoc;
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static struct qcom_icc_node qns_gem_noc_snoc;
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static struct qcom_icc_node qns_llcc;
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static struct qcom_icc_node qns_sys_pcie;
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static struct qcom_icc_node srvc_even_gemnoc;
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static struct qcom_icc_node srvc_odd_gemnoc;
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static struct qcom_icc_node srvc_sys_gemnoc;
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static struct qcom_icc_node ebi;
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static struct qcom_icc_node qns_mem_noc_hf;
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static struct qcom_icc_node qns_mem_noc_sf;
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static struct qcom_icc_node srvc_mnoc;
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static struct qcom_icc_node qhs_cal_dp0;
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static struct qcom_icc_node qhs_cal_dp1;
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static struct qcom_icc_node qhs_cp;
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static struct qcom_icc_node qhs_dma_bwmon;
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static struct qcom_icc_node qhs_dpm;
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static struct qcom_icc_node qhs_isense;
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static struct qcom_icc_node qhs_llm;
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static struct qcom_icc_node qhs_tcm;
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static struct qcom_icc_node qns_npu_sys;
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static struct qcom_icc_node srvc_noc;
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static struct qcom_icc_node qhs_apss;
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static struct qcom_icc_node qns_cnoc;
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static struct qcom_icc_node qns_gemnoc_gc;
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static struct qcom_icc_node qns_gemnoc_sf;
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static struct qcom_icc_node qxs_imem;
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static struct qcom_icc_node qxs_pimem;
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static struct qcom_icc_node srvc_snoc;
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static struct qcom_icc_node xs_pcie_0;
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static struct qcom_icc_node xs_pcie_1;
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static struct qcom_icc_node xs_pcie_modem;
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static struct qcom_icc_node xs_qdss_stm;
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static struct qcom_icc_node xs_sys_tcu_cfg;
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static struct qcom_icc_node qup0_core_master;
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static struct qcom_icc_node qup1_core_master;
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static struct qcom_icc_node qup2_core_master;
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static struct qcom_icc_node qup0_core_slave;
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static struct qcom_icc_node qup1_core_slave;
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static struct qcom_icc_node qup2_core_slave;
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static struct qcom_icc_node qhm_a1noc_cfg = {
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.name = "qhm_a1noc_cfg",
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.id = SM8250_MASTER_A1NOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_SLAVE_SERVICE_A1NOC },
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.link_nodes = { &srvc_aggre1_noc },
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};
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static struct qcom_icc_node qhm_qspi = {
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.name = "qhm_qspi",
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.id = SM8250_MASTER_QSPI_0,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_qup1 = {
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.name = "qhm_qup1",
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.id = SM8250_MASTER_QUP_1,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_qup2 = {
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.name = "qhm_qup2",
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.id = SM8250_MASTER_QUP_2,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_tsif = {
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.name = "qhm_tsif",
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.id = SM8250_MASTER_TSIF,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_pcie3_modem = {
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.name = "xm_pcie3_modem",
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.id = SM8250_MASTER_PCIE_2,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 },
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.link_nodes = { &qns_pcie_modem_mem_noc },
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};
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static struct qcom_icc_node xm_sdc4 = {
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.name = "xm_sdc4",
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.id = SM8250_MASTER_SDCC_4,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_ufs_mem = {
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.name = "xm_ufs_mem",
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.id = SM8250_MASTER_UFS_MEM,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_usb3_0 = {
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.name = "xm_usb3_0",
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.id = SM8250_MASTER_USB3,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_usb3_1 = {
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.name = "xm_usb3_1",
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.id = SM8250_MASTER_USB3_1,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A1NOC_SNOC_SLV },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_a2noc_cfg = {
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.name = "qhm_a2noc_cfg",
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.id = SM8250_MASTER_A2NOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_SLAVE_SERVICE_A2NOC },
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.link_nodes = { &srvc_aggre2_noc },
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};
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static struct qcom_icc_node qhm_qdss_bam = {
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.name = "qhm_qdss_bam",
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.id = SM8250_MASTER_QDSS_BAM,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qhm_qup0 = {
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.name = "qhm_qup0",
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.id = SM8250_MASTER_QUP_0,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qnm_cnoc = {
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.name = "qnm_cnoc",
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.id = SM8250_MASTER_CNOC_A2NOC,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qxm_crypto = {
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.name = "qxm_crypto",
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.id = SM8250_MASTER_CRYPTO_CORE_0,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qxm_ipa = {
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.name = "qxm_ipa",
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.id = SM8250_MASTER_IPA,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node xm_pcie3_0 = {
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.name = "xm_pcie3_0",
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.id = SM8250_MASTER_PCIE,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
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.link_nodes = { &qns_pcie_mem_noc },
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};
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static struct qcom_icc_node xm_pcie3_1 = {
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.name = "xm_pcie3_1",
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.id = SM8250_MASTER_PCIE_1,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
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.link_nodes = { &qns_pcie_mem_noc },
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};
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static struct qcom_icc_node xm_qdss_etr = {
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.name = "xm_qdss_etr",
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.id = SM8250_MASTER_QDSS_ETR,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node xm_sdc2 = {
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.name = "xm_sdc2",
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.id = SM8250_MASTER_SDCC_2,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node xm_ufs_card = {
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.name = "xm_ufs_card",
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.id = SM8250_MASTER_UFS_CARD,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SM8250_A2NOC_SNOC_SLV },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qnm_npu = {
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.name = "qnm_npu",
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.id = SM8250_MASTER_NPU,
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.channels = 2,
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.buswidth = 32,
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.num_links = 1,
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.links = { SM8250_SLAVE_CDSP_MEM_NOC },
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.link_nodes = { &qns_cdsp_mem_noc },
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};
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217
349
static struct qcom_icc_node qnm_snoc = {
218
350
.name = "qnm_snoc",
219
-
.id = SM8250_SNOC_CNOC_MAS,
220
351
.channels = 1,
221
352
.buswidth = 8,
222
353
.num_links = 49,
223
-
.links = { SM8250_SLAVE_CDSP_CFG,
224
-
SM8250_SLAVE_CAMERA_CFG,
225
-
SM8250_SLAVE_TLMM_SOUTH,
226
-
SM8250_SLAVE_TLMM_NORTH,
227
-
SM8250_SLAVE_SDCC_4,
228
-
SM8250_SLAVE_TLMM_WEST,
229
-
SM8250_SLAVE_SDCC_2,
230
-
SM8250_SLAVE_CNOC_MNOC_CFG,
231
-
SM8250_SLAVE_UFS_MEM_CFG,
232
-
SM8250_SLAVE_SNOC_CFG,
233
-
SM8250_SLAVE_PDM,
234
-
SM8250_SLAVE_CX_RDPM,
235
-
SM8250_SLAVE_PCIE_1_CFG,
236
-
SM8250_SLAVE_A2NOC_CFG,
237
-
SM8250_SLAVE_QDSS_CFG,
238
-
SM8250_SLAVE_DISPLAY_CFG,
239
-
SM8250_SLAVE_PCIE_2_CFG,
240
-
SM8250_SLAVE_TCSR,
241
-
SM8250_SLAVE_DCC_CFG,
242
-
SM8250_SLAVE_CNOC_DDRSS,
243
-
SM8250_SLAVE_IPC_ROUTER_CFG,
244
-
SM8250_SLAVE_PCIE_0_CFG,
245
-
SM8250_SLAVE_RBCPR_MMCX_CFG,
246
-
SM8250_SLAVE_NPU_CFG,
247
-
SM8250_SLAVE_AHB2PHY_SOUTH,
248
-
SM8250_SLAVE_AHB2PHY_NORTH,
249
-
SM8250_SLAVE_GRAPHICS_3D_CFG,
250
-
SM8250_SLAVE_VENUS_CFG,
251
-
SM8250_SLAVE_TSIF,
252
-
SM8250_SLAVE_IPA_CFG,
253
-
SM8250_SLAVE_IMEM_CFG,
254
-
SM8250_SLAVE_USB3,
255
-
SM8250_SLAVE_SERVICE_CNOC,
256
-
SM8250_SLAVE_UFS_CARD_CFG,
257
-
SM8250_SLAVE_USB3_1,
258
-
SM8250_SLAVE_LPASS,
259
-
SM8250_SLAVE_RBCPR_CX_CFG,
260
-
SM8250_SLAVE_A1NOC_CFG,
261
-
SM8250_SLAVE_AOSS,
262
-
SM8250_SLAVE_PRNG,
263
-
SM8250_SLAVE_VSENSE_CTRL_CFG,
264
-
SM8250_SLAVE_QSPI_0,
265
-
SM8250_SLAVE_CRYPTO_0_CFG,
266
-
SM8250_SLAVE_PIMEM_CFG,
267
-
SM8250_SLAVE_RBCPR_MX_CFG,
268
-
SM8250_SLAVE_QUP_0,
269
-
SM8250_SLAVE_QUP_1,
270
-
SM8250_SLAVE_QUP_2,
271
-
SM8250_SLAVE_CLK_CTL
272
-
},
354
+
.link_nodes = { &qhs_compute_dsp,
355
+
&qhs_camera_cfg,
356
+
&qhs_tlmm1,
357
+
&qhs_tlmm0,
358
+
&qhs_sdc4,
359
+
&qhs_tlmm2,
360
+
&qhs_sdc2,
361
+
&qhs_mnoc_cfg,
362
+
&qhs_ufs_mem_cfg,
363
+
&qhs_snoc_cfg,
364
+
&qhs_pdm,
365
+
&qhs_cx_rdpm,
366
+
&qhs_pcie1_cfg,
367
+
&qhs_a2_noc_cfg,
368
+
&qhs_qdss_cfg,
369
+
&qhs_display_cfg,
370
+
&qhs_pcie_modem_cfg,
371
+
&qhs_tcsr,
372
+
&qhs_dcc_cfg,
373
+
&qhs_ddrss_cfg,
374
+
&qhs_ipc_router,
375
+
&qhs_pcie0_cfg,
376
+
&qhs_cpr_mmcx,
377
+
&qhs_npu_cfg,
378
+
&qhs_ahb2phy0,
379
+
&qhs_ahb2phy1,
380
+
&qhs_gpuss_cfg,
381
+
&qhs_venus_cfg,
382
+
&qhs_tsif,
383
+
&qhs_ipa,
384
+
&qhs_imem_cfg,
385
+
&qhs_usb3_0,
386
+
&srvc_cnoc,
387
+
&qhs_ufs_card_cfg,
388
+
&qhs_usb3_1,
389
+
&qhs_lpass_cfg,
390
+
&qhs_cpr_cx,
391
+
&qhs_a1_noc_cfg,
392
+
&qhs_aoss,
393
+
&qhs_prng,
394
+
&qhs_vsense_ctrl_cfg,
395
+
&qhs_qspi,
396
+
&qhs_crypto0_cfg,
397
+
&qhs_pimem_cfg,
398
+
&qhs_cpr_mx,
399
+
&qhs_qup0,
400
+
&qhs_qup1,
401
+
&qhs_qup2,
402
+
&qhs_clk_ctl },
273
403
};
274
404
275
405
static struct qcom_icc_node xm_qdss_dap = {
276
406
.name = "xm_qdss_dap",
277
-
.id = SM8250_MASTER_QDSS_DAP,
278
407
.channels = 1,
279
408
.buswidth = 8,
280
409
.num_links = 50,
281
-
.links = { SM8250_SLAVE_CDSP_CFG,
282
-
SM8250_SLAVE_CAMERA_CFG,
283
-
SM8250_SLAVE_TLMM_SOUTH,
284
-
SM8250_SLAVE_TLMM_NORTH,
285
-
SM8250_SLAVE_SDCC_4,
286
-
SM8250_SLAVE_TLMM_WEST,
287
-
SM8250_SLAVE_SDCC_2,
288
-
SM8250_SLAVE_CNOC_MNOC_CFG,
289
-
SM8250_SLAVE_UFS_MEM_CFG,
290
-
SM8250_SLAVE_SNOC_CFG,
291
-
SM8250_SLAVE_PDM,
292
-
SM8250_SLAVE_CX_RDPM,
293
-
SM8250_SLAVE_PCIE_1_CFG,
294
-
SM8250_SLAVE_A2NOC_CFG,
295
-
SM8250_SLAVE_QDSS_CFG,
296
-
SM8250_SLAVE_DISPLAY_CFG,
297
-
SM8250_SLAVE_PCIE_2_CFG,
298
-
SM8250_SLAVE_TCSR,
299
-
SM8250_SLAVE_DCC_CFG,
300
-
SM8250_SLAVE_CNOC_DDRSS,
301
-
SM8250_SLAVE_IPC_ROUTER_CFG,
302
-
SM8250_SLAVE_CNOC_A2NOC,
303
-
SM8250_SLAVE_PCIE_0_CFG,
304
-
SM8250_SLAVE_RBCPR_MMCX_CFG,
305
-
SM8250_SLAVE_NPU_CFG,
306
-
SM8250_SLAVE_AHB2PHY_SOUTH,
307
-
SM8250_SLAVE_AHB2PHY_NORTH,
308
-
SM8250_SLAVE_GRAPHICS_3D_CFG,
309
-
SM8250_SLAVE_VENUS_CFG,
310
-
SM8250_SLAVE_TSIF,
311
-
SM8250_SLAVE_IPA_CFG,
312
-
SM8250_SLAVE_IMEM_CFG,
313
-
SM8250_SLAVE_USB3,
314
-
SM8250_SLAVE_SERVICE_CNOC,
315
-
SM8250_SLAVE_UFS_CARD_CFG,
316
-
SM8250_SLAVE_USB3_1,
317
-
SM8250_SLAVE_LPASS,
318
-
SM8250_SLAVE_RBCPR_CX_CFG,
319
-
SM8250_SLAVE_A1NOC_CFG,
320
-
SM8250_SLAVE_AOSS,
321
-
SM8250_SLAVE_PRNG,
322
-
SM8250_SLAVE_VSENSE_CTRL_CFG,
323
-
SM8250_SLAVE_QSPI_0,
324
-
SM8250_SLAVE_CRYPTO_0_CFG,
325
-
SM8250_SLAVE_PIMEM_CFG,
326
-
SM8250_SLAVE_RBCPR_MX_CFG,
327
-
SM8250_SLAVE_QUP_0,
328
-
SM8250_SLAVE_QUP_1,
329
-
SM8250_SLAVE_QUP_2,
330
-
SM8250_SLAVE_CLK_CTL
331
-
},
410
+
.link_nodes = { &qhs_compute_dsp,
411
+
&qhs_camera_cfg,
412
+
&qhs_tlmm1,
413
+
&qhs_tlmm0,
414
+
&qhs_sdc4,
415
+
&qhs_tlmm2,
416
+
&qhs_sdc2,
417
+
&qhs_mnoc_cfg,
418
+
&qhs_ufs_mem_cfg,
419
+
&qhs_snoc_cfg,
420
+
&qhs_pdm,
421
+
&qhs_cx_rdpm,
422
+
&qhs_pcie1_cfg,
423
+
&qhs_a2_noc_cfg,
424
+
&qhs_qdss_cfg,
425
+
&qhs_display_cfg,
426
+
&qhs_pcie_modem_cfg,
427
+
&qhs_tcsr,
428
+
&qhs_dcc_cfg,
429
+
&qhs_ddrss_cfg,
430
+
&qhs_ipc_router,
431
+
&qns_cnoc_a2noc,
432
+
&qhs_pcie0_cfg,
433
+
&qhs_cpr_mmcx,
434
+
&qhs_npu_cfg,
435
+
&qhs_ahb2phy0,
436
+
&qhs_ahb2phy1,
437
+
&qhs_gpuss_cfg,
438
+
&qhs_venus_cfg,
439
+
&qhs_tsif,
440
+
&qhs_ipa,
441
+
&qhs_imem_cfg,
442
+
&qhs_usb3_0,
443
+
&srvc_cnoc,
444
+
&qhs_ufs_card_cfg,
445
+
&qhs_usb3_1,
446
+
&qhs_lpass_cfg,
447
+
&qhs_cpr_cx,
448
+
&qhs_a1_noc_cfg,
449
+
&qhs_aoss,
450
+
&qhs_prng,
451
+
&qhs_vsense_ctrl_cfg,
452
+
&qhs_qspi,
453
+
&qhs_crypto0_cfg,
454
+
&qhs_pimem_cfg,
455
+
&qhs_cpr_mx,
456
+
&qhs_qup0,
457
+
&qhs_qup1,
458
+
&qhs_qup2,
459
+
&qhs_clk_ctl },
332
460
};
333
461
334
462
static struct qcom_icc_node qhm_cnoc_dc_noc = {
335
463
.name = "qhm_cnoc_dc_noc",
336
-
.id = SM8250_MASTER_CNOC_DC_NOC,
337
464
.channels = 1,
338
465
.buswidth = 4,
339
466
.num_links = 2,
340
-
.links = { SM8250_SLAVE_GEM_NOC_CFG,
341
-
SM8250_SLAVE_LLCC_CFG
342
-
},
467
+
.link_nodes = { &qhs_memnoc,
468
+
&qhs_llcc },
343
469
};
344
470
345
471
static struct qcom_icc_node alm_gpu_tcu = {
346
472
.name = "alm_gpu_tcu",
347
-
.id = SM8250_MASTER_GPU_TCU,
348
473
.channels = 1,
349
474
.buswidth = 8,
350
475
.num_links = 2,
351
-
.links = { SM8250_SLAVE_LLCC,
352
-
SM8250_SLAVE_GEM_NOC_SNOC
353
-
},
476
+
.link_nodes = { &qns_llcc,
477
+
&qns_gem_noc_snoc },
354
478
};
355
479
356
480
static struct qcom_icc_node alm_sys_tcu = {
357
481
.name = "alm_sys_tcu",
358
-
.id = SM8250_MASTER_SYS_TCU,
359
482
.channels = 1,
360
483
.buswidth = 8,
361
484
.num_links = 2,
362
-
.links = { SM8250_SLAVE_LLCC,
363
-
SM8250_SLAVE_GEM_NOC_SNOC
364
-
},
485
+
.link_nodes = { &qns_llcc,
486
+
&qns_gem_noc_snoc },
365
487
};
366
488
367
489
static struct qcom_icc_node chm_apps = {
368
490
.name = "chm_apps",
369
-
.id = SM8250_MASTER_AMPSS_M0,
370
491
.channels = 2,
371
492
.buswidth = 32,
372
493
.num_links = 3,
373
-
.links = { SM8250_SLAVE_LLCC,
374
-
SM8250_SLAVE_GEM_NOC_SNOC,
375
-
SM8250_SLAVE_MEM_NOC_PCIE_SNOC
376
-
},
494
+
.link_nodes = { &qns_llcc,
495
+
&qns_gem_noc_snoc,
496
+
&qns_sys_pcie },
377
497
};
378
498
379
499
static struct qcom_icc_node qhm_gemnoc_cfg = {
380
500
.name = "qhm_gemnoc_cfg",
381
-
.id = SM8250_MASTER_GEM_NOC_CFG,
382
501
.channels = 1,
383
502
.buswidth = 4,
384
503
.num_links = 3,
385
-
.links = { SM8250_SLAVE_SERVICE_GEM_NOC_2,
386
-
SM8250_SLAVE_SERVICE_GEM_NOC_1,
387
-
SM8250_SLAVE_SERVICE_GEM_NOC
388
-
},
504
+
.link_nodes = { &srvc_odd_gemnoc,
505
+
&srvc_even_gemnoc,
506
+
&srvc_sys_gemnoc },
389
507
};
390
508
391
509
static struct qcom_icc_node qnm_cmpnoc = {
392
510
.name = "qnm_cmpnoc",
393
-
.id = SM8250_MASTER_COMPUTE_NOC,
394
511
.channels = 2,
395
512
.buswidth = 32,
396
513
.num_links = 2,
397
-
.links = { SM8250_SLAVE_LLCC,
398
-
SM8250_SLAVE_GEM_NOC_SNOC
399
-
},
514
+
.link_nodes = { &qns_llcc,
515
+
&qns_gem_noc_snoc },
400
516
};
401
517
402
518
static struct qcom_icc_node qnm_gpu = {
403
519
.name = "qnm_gpu",
404
-
.id = SM8250_MASTER_GRAPHICS_3D,
405
520
.channels = 2,
406
521
.buswidth = 32,
407
522
.num_links = 2,
408
-
.links = { SM8250_SLAVE_LLCC,
409
-
SM8250_SLAVE_GEM_NOC_SNOC },
523
+
.link_nodes = { &qns_llcc,
524
+
&qns_gem_noc_snoc },
410
525
};
411
526
412
527
static struct qcom_icc_node qnm_mnoc_hf = {
413
528
.name = "qnm_mnoc_hf",
414
-
.id = SM8250_MASTER_MNOC_HF_MEM_NOC,
415
529
.channels = 2,
416
530
.buswidth = 32,
417
531
.num_links = 1,
418
-
.links = { SM8250_SLAVE_LLCC },
532
+
.link_nodes = { &qns_llcc },
419
533
};
420
534
421
535
static struct qcom_icc_node qnm_mnoc_sf = {
422
536
.name = "qnm_mnoc_sf",
423
-
.id = SM8250_MASTER_MNOC_SF_MEM_NOC,
424
537
.channels = 2,
425
538
.buswidth = 32,
426
539
.num_links = 2,
427
-
.links = { SM8250_SLAVE_LLCC,
428
-
SM8250_SLAVE_GEM_NOC_SNOC
429
-
},
540
+
.link_nodes = { &qns_llcc,
541
+
&qns_gem_noc_snoc },
430
542
};
431
543
432
544
static struct qcom_icc_node qnm_pcie = {
433
545
.name = "qnm_pcie",
434
-
.id = SM8250_MASTER_ANOC_PCIE_GEM_NOC,
435
546
.channels = 1,
436
547
.buswidth = 16,
437
548
.num_links = 2,
438
-
.links = { SM8250_SLAVE_LLCC,
439
-
SM8250_SLAVE_GEM_NOC_SNOC
440
-
},
549
+
.link_nodes = { &qns_llcc,
550
+
&qns_gem_noc_snoc },
441
551
};
442
552
443
553
static struct qcom_icc_node qnm_snoc_gc = {
444
554
.name = "qnm_snoc_gc",
445
-
.id = SM8250_MASTER_SNOC_GC_MEM_NOC,
446
555
.channels = 1,
447
556
.buswidth = 8,
448
557
.num_links = 1,
449
-
.links = { SM8250_SLAVE_LLCC },
558
+
.link_nodes = { &qns_llcc },
450
559
};
451
560
452
561
static struct qcom_icc_node qnm_snoc_sf = {
453
562
.name = "qnm_snoc_sf",
454
-
.id = SM8250_MASTER_SNOC_SF_MEM_NOC,
455
563
.channels = 1,
456
564
.buswidth = 16,
457
565
.num_links = 3,
458
-
.links = { SM8250_SLAVE_LLCC,
459
-
SM8250_SLAVE_GEM_NOC_SNOC,
460
-
SM8250_SLAVE_MEM_NOC_PCIE_SNOC
461
-
},
566
+
.link_nodes = { &qns_llcc,
567
+
&qns_gem_noc_snoc,
568
+
&qns_sys_pcie },
462
569
};
463
570
464
571
static struct qcom_icc_node llcc_mc = {
465
572
.name = "llcc_mc",
466
-
.id = SM8250_MASTER_LLCC,
467
573
.channels = 4,
468
574
.buswidth = 4,
469
575
.num_links = 1,
470
-
.links = { SM8250_SLAVE_EBI_CH0 },
576
+
.link_nodes = { &ebi },
471
577
};
472
578
473
579
static struct qcom_icc_node qhm_mnoc_cfg = {
474
580
.name = "qhm_mnoc_cfg",
475
-
.id = SM8250_MASTER_CNOC_MNOC_CFG,
476
581
.channels = 1,
477
582
.buswidth = 4,
478
583
.num_links = 1,
479
-
.links = { SM8250_SLAVE_SERVICE_MNOC },
584
+
.link_nodes = { &srvc_mnoc },
480
585
};
481
586
482
587
static struct qcom_icc_node qnm_camnoc_hf = {
483
588
.name = "qnm_camnoc_hf",
484
-
.id = SM8250_MASTER_CAMNOC_HF,
485
589
.channels = 2,
486
590
.buswidth = 32,
487
591
.num_links = 1,
488
-
.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
592
+
.link_nodes = { &qns_mem_noc_hf },
489
593
};
490
594
491
595
static struct qcom_icc_node qnm_camnoc_icp = {
492
596
.name = "qnm_camnoc_icp",
493
-
.id = SM8250_MASTER_CAMNOC_ICP,
494
597
.channels = 1,
495
598
.buswidth = 8,
496
599
.num_links = 1,
497
-
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
600
+
.link_nodes = { &qns_mem_noc_sf },
498
601
};
499
602
500
603
static struct qcom_icc_node qnm_camnoc_sf = {
501
604
.name = "qnm_camnoc_sf",
502
-
.id = SM8250_MASTER_CAMNOC_SF,
503
605
.channels = 2,
504
606
.buswidth = 32,
505
607
.num_links = 1,
506
-
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
608
+
.link_nodes = { &qns_mem_noc_sf },
507
609
};
508
610
509
611
static struct qcom_icc_node qnm_video0 = {
510
612
.name = "qnm_video0",
511
-
.id = SM8250_MASTER_VIDEO_P0,
512
613
.channels = 1,
513
614
.buswidth = 32,
514
615
.num_links = 1,
515
-
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
616
+
.link_nodes = { &qns_mem_noc_sf },
516
617
};
517
618
518
619
static struct qcom_icc_node qnm_video1 = {
519
620
.name = "qnm_video1",
520
-
.id = SM8250_MASTER_VIDEO_P1,
521
621
.channels = 1,
522
622
.buswidth = 32,
523
623
.num_links = 1,
524
-
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
624
+
.link_nodes = { &qns_mem_noc_sf },
525
625
};
526
626
527
627
static struct qcom_icc_node qnm_video_cvp = {
528
628
.name = "qnm_video_cvp",
529
-
.id = SM8250_MASTER_VIDEO_PROC,
530
629
.channels = 1,
531
630
.buswidth = 32,
532
631
.num_links = 1,
533
-
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
632
+
.link_nodes = { &qns_mem_noc_sf },
534
633
};
535
634
536
635
static struct qcom_icc_node qxm_mdp0 = {
537
636
.name = "qxm_mdp0",
538
-
.id = SM8250_MASTER_MDP_PORT0,
539
637
.channels = 1,
540
638
.buswidth = 32,
541
639
.num_links = 1,
542
-
.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
640
+
.link_nodes = { &qns_mem_noc_hf },
543
641
};
544
642
545
643
static struct qcom_icc_node qxm_mdp1 = {
546
644
.name = "qxm_mdp1",
547
-
.id = SM8250_MASTER_MDP_PORT1,
548
645
.channels = 1,
549
646
.buswidth = 32,
550
647
.num_links = 1,
551
-
.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
648
+
.link_nodes = { &qns_mem_noc_hf },
552
649
};
553
650
554
651
static struct qcom_icc_node qxm_rot = {
555
652
.name = "qxm_rot",
556
-
.id = SM8250_MASTER_ROTATOR,
557
653
.channels = 1,
558
654
.buswidth = 32,
559
655
.num_links = 1,
560
-
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
656
+
.link_nodes = { &qns_mem_noc_sf },
561
657
};
562
658
563
659
static struct qcom_icc_node amm_npu_sys = {
564
660
.name = "amm_npu_sys",
565
-
.id = SM8250_MASTER_NPU_SYS,
566
661
.channels = 4,
567
662
.buswidth = 32,
568
663
.num_links = 1,
569
-
.links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
664
+
.link_nodes = { &qns_npu_sys },
570
665
};
571
666
572
667
static struct qcom_icc_node amm_npu_sys_cdp_w = {
573
668
.name = "amm_npu_sys_cdp_w",
574
-
.id = SM8250_MASTER_NPU_CDP,
575
669
.channels = 2,
576
670
.buswidth = 16,
577
671
.num_links = 1,
578
-
.links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
672
+
.link_nodes = { &qns_npu_sys },
579
673
};
580
674
581
675
static struct qcom_icc_node qhm_cfg = {
582
676
.name = "qhm_cfg",
583
-
.id = SM8250_MASTER_NPU_NOC_CFG,
584
677
.channels = 1,
585
678
.buswidth = 4,
586
679
.num_links = 9,
587
-
.links = { SM8250_SLAVE_SERVICE_NPU_NOC,
588
-
SM8250_SLAVE_ISENSE_CFG,
589
-
SM8250_SLAVE_NPU_LLM_CFG,
590
-
SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
591
-
SM8250_SLAVE_NPU_CP,
592
-
SM8250_SLAVE_NPU_TCM,
593
-
SM8250_SLAVE_NPU_CAL_DP0,
594
-
SM8250_SLAVE_NPU_CAL_DP1,
595
-
SM8250_SLAVE_NPU_DPM
596
-
},
680
+
.link_nodes = { &srvc_noc,
681
+
&qhs_isense,
682
+
&qhs_llm,
683
+
&qhs_dma_bwmon,
684
+
&qhs_cp,
685
+
&qhs_tcm,
686
+
&qhs_cal_dp0,
687
+
&qhs_cal_dp1,
688
+
&qhs_dpm },
597
689
};
598
690
599
691
static struct qcom_icc_node qhm_snoc_cfg = {
600
692
.name = "qhm_snoc_cfg",
601
-
.id = SM8250_MASTER_SNOC_CFG,
602
693
.channels = 1,
603
694
.buswidth = 4,
604
695
.num_links = 1,
605
-
.links = { SM8250_SLAVE_SERVICE_SNOC },
696
+
.link_nodes = { &srvc_snoc },
606
697
};
607
698
608
699
static struct qcom_icc_node qnm_aggre1_noc = {
609
700
.name = "qnm_aggre1_noc",
610
-
.id = SM8250_A1NOC_SNOC_MAS,
611
701
.channels = 1,
612
702
.buswidth = 16,
613
703
.num_links = 1,
614
-
.links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
704
+
.link_nodes = { &qns_gemnoc_sf },
615
705
};
616
706
617
707
static struct qcom_icc_node qnm_aggre2_noc = {
618
708
.name = "qnm_aggre2_noc",
619
-
.id = SM8250_A2NOC_SNOC_MAS,
620
709
.channels = 1,
621
710
.buswidth = 16,
622
711
.num_links = 1,
623
-
.links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
712
+
.link_nodes = { &qns_gemnoc_sf },
624
713
};
625
714
626
715
static struct qcom_icc_node qnm_gemnoc = {
627
716
.name = "qnm_gemnoc",
628
-
.id = SM8250_MASTER_GEM_NOC_SNOC,
629
717
.channels = 1,
630
718
.buswidth = 16,
631
719
.num_links = 6,
632
-
.links = { SM8250_SLAVE_PIMEM,
633
-
SM8250_SLAVE_OCIMEM,
634
-
SM8250_SLAVE_APPSS,
635
-
SM8250_SNOC_CNOC_SLV,
636
-
SM8250_SLAVE_TCU,
637
-
SM8250_SLAVE_QDSS_STM
638
-
},
720
+
.link_nodes = { &qxs_pimem,
721
+
&qxs_imem,
722
+
&qhs_apss,
723
+
&qns_cnoc,
724
+
&xs_sys_tcu_cfg,
725
+
&xs_qdss_stm },
639
726
};
640
727
641
728
static struct qcom_icc_node qnm_gemnoc_pcie = {
642
729
.name = "qnm_gemnoc_pcie",
643
-
.id = SM8250_MASTER_GEM_NOC_PCIE_SNOC,
644
730
.channels = 1,
645
731
.buswidth = 8,
646
732
.num_links = 3,
647
-
.links = { SM8250_SLAVE_PCIE_2,
648
-
SM8250_SLAVE_PCIE_0,
649
-
SM8250_SLAVE_PCIE_1
650
-
},
733
+
.link_nodes = { &xs_pcie_modem,
734
+
&xs_pcie_0,
735
+
&xs_pcie_1 },
651
736
};
652
737
653
738
static struct qcom_icc_node qxm_pimem = {
654
739
.name = "qxm_pimem",
655
-
.id = SM8250_MASTER_PIMEM,
656
740
.channels = 1,
657
741
.buswidth = 8,
658
742
.num_links = 1,
659
-
.links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
743
+
.link_nodes = { &qns_gemnoc_gc },
660
744
};
661
745
662
746
static struct qcom_icc_node xm_gic = {
663
747
.name = "xm_gic",
664
-
.id = SM8250_MASTER_GIC,
665
748
.channels = 1,
666
749
.buswidth = 8,
667
750
.num_links = 1,
668
-
.links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
751
+
.link_nodes = { &qns_gemnoc_gc },
669
752
};
670
753
671
754
static struct qcom_icc_node qns_a1noc_snoc = {
672
755
.name = "qns_a1noc_snoc",
673
-
.id = SM8250_A1NOC_SNOC_SLV,
674
756
.channels = 1,
675
757
.buswidth = 16,
676
758
.num_links = 1,
677
-
.links = { SM8250_A1NOC_SNOC_MAS },
759
+
.link_nodes = { &qnm_aggre1_noc },
678
760
};
679
761
680
762
static struct qcom_icc_node qns_pcie_modem_mem_noc = {
681
763
.name = "qns_pcie_modem_mem_noc",
682
-
.id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1,
683
764
.channels = 1,
684
765
.buswidth = 16,
685
766
.num_links = 1,
686
-
.links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
767
+
.link_nodes = { &qnm_pcie },
687
768
};
688
769
689
770
static struct qcom_icc_node srvc_aggre1_noc = {
690
771
.name = "srvc_aggre1_noc",
691
-
.id = SM8250_SLAVE_SERVICE_A1NOC,
692
772
.channels = 1,
693
773
.buswidth = 4,
694
774
};
695
775
696
776
static struct qcom_icc_node qns_a2noc_snoc = {
697
777
.name = "qns_a2noc_snoc",
698
-
.id = SM8250_A2NOC_SNOC_SLV,
699
778
.channels = 1,
700
779
.buswidth = 16,
701
780
.num_links = 1,
702
-
.links = { SM8250_A2NOC_SNOC_MAS },
781
+
.link_nodes = { &qnm_aggre2_noc },
703
782
};
704
783
705
784
static struct qcom_icc_node qns_pcie_mem_noc = {
706
785
.name = "qns_pcie_mem_noc",
707
-
.id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC,
708
786
.channels = 1,
709
787
.buswidth = 16,
710
788
.num_links = 1,
711
-
.links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
789
+
.link_nodes = { &qnm_pcie },
712
790
};
713
791
714
792
static struct qcom_icc_node srvc_aggre2_noc = {
715
793
.name = "srvc_aggre2_noc",
716
-
.id = SM8250_SLAVE_SERVICE_A2NOC,
717
794
.channels = 1,
718
795
.buswidth = 4,
719
796
};
720
797
721
798
static struct qcom_icc_node qns_cdsp_mem_noc = {
722
799
.name = "qns_cdsp_mem_noc",
723
-
.id = SM8250_SLAVE_CDSP_MEM_NOC,
724
800
.channels = 2,
725
801
.buswidth = 32,
726
802
.num_links = 1,
727
-
.links = { SM8250_MASTER_COMPUTE_NOC },
803
+
.link_nodes = { &qnm_cmpnoc },
728
804
};
729
805
730
806
static struct qcom_icc_node qhs_a1_noc_cfg = {
731
807
.name = "qhs_a1_noc_cfg",
732
-
.id = SM8250_SLAVE_A1NOC_CFG,
733
808
.channels = 1,
734
809
.buswidth = 4,
735
810
.num_links = 1,
736
-
.links = { SM8250_MASTER_A1NOC_CFG },
811
+
.link_nodes = { &qhm_a1noc_cfg },
737
812
};
738
813
739
814
static struct qcom_icc_node qhs_a2_noc_cfg = {
740
815
.name = "qhs_a2_noc_cfg",
741
-
.id = SM8250_SLAVE_A2NOC_CFG,
742
816
.channels = 1,
743
817
.buswidth = 4,
744
818
.num_links = 1,
745
-
.links = { SM8250_MASTER_A2NOC_CFG },
819
+
.link_nodes = { &qhm_a2noc_cfg },
746
820
};
747
821
748
822
static struct qcom_icc_node qhs_ahb2phy0 = {
749
823
.name = "qhs_ahb2phy0",
750
-
.id = SM8250_SLAVE_AHB2PHY_SOUTH,
751
824
.channels = 1,
752
825
.buswidth = 4,
753
826
};
754
827
755
828
static struct qcom_icc_node qhs_ahb2phy1 = {
756
829
.name = "qhs_ahb2phy1",
757
-
.id = SM8250_SLAVE_AHB2PHY_NORTH,
758
830
.channels = 1,
759
831
.buswidth = 4,
760
832
};
761
833
762
834
static struct qcom_icc_node qhs_aoss = {
763
835
.name = "qhs_aoss",
764
-
.id = SM8250_SLAVE_AOSS,
765
836
.channels = 1,
766
837
.buswidth = 4,
767
838
};
768
839
769
840
static struct qcom_icc_node qhs_camera_cfg = {
770
841
.name = "qhs_camera_cfg",
771
-
.id = SM8250_SLAVE_CAMERA_CFG,
772
842
.channels = 1,
773
843
.buswidth = 4,
774
844
};
775
845
776
846
static struct qcom_icc_node qhs_clk_ctl = {
777
847
.name = "qhs_clk_ctl",
778
-
.id = SM8250_SLAVE_CLK_CTL,
779
848
.channels = 1,
780
849
.buswidth = 4,
781
850
};
782
851
783
852
static struct qcom_icc_node qhs_compute_dsp = {
784
853
.name = "qhs_compute_dsp",
785
-
.id = SM8250_SLAVE_CDSP_CFG,
786
854
.channels = 1,
787
855
.buswidth = 4,
788
856
};
789
857
790
858
static struct qcom_icc_node qhs_cpr_cx = {
791
859
.name = "qhs_cpr_cx",
792
-
.id = SM8250_SLAVE_RBCPR_CX_CFG,
793
860
.channels = 1,
794
861
.buswidth = 4,
795
862
};
796
863
797
864
static struct qcom_icc_node qhs_cpr_mmcx = {
798
865
.name = "qhs_cpr_mmcx",
799
-
.id = SM8250_SLAVE_RBCPR_MMCX_CFG,
800
866
.channels = 1,
801
867
.buswidth = 4,
802
868
};
803
869
804
870
static struct qcom_icc_node qhs_cpr_mx = {
805
871
.name = "qhs_cpr_mx",
806
-
.id = SM8250_SLAVE_RBCPR_MX_CFG,
807
872
.channels = 1,
808
873
.buswidth = 4,
809
874
};
810
875
811
876
static struct qcom_icc_node qhs_crypto0_cfg = {
812
877
.name = "qhs_crypto0_cfg",
813
-
.id = SM8250_SLAVE_CRYPTO_0_CFG,
814
878
.channels = 1,
815
879
.buswidth = 4,
816
880
};
817
881
818
882
static struct qcom_icc_node qhs_cx_rdpm = {
819
883
.name = "qhs_cx_rdpm",
820
-
.id = SM8250_SLAVE_CX_RDPM,
821
884
.channels = 1,
822
885
.buswidth = 4,
823
886
};
824
887
825
888
static struct qcom_icc_node qhs_dcc_cfg = {
826
889
.name = "qhs_dcc_cfg",
827
-
.id = SM8250_SLAVE_DCC_CFG,
828
890
.channels = 1,
829
891
.buswidth = 4,
830
892
};
831
893
832
894
static struct qcom_icc_node qhs_ddrss_cfg = {
833
895
.name = "qhs_ddrss_cfg",
834
-
.id = SM8250_SLAVE_CNOC_DDRSS,
835
896
.channels = 1,
836
897
.buswidth = 4,
837
898
.num_links = 1,
838
-
.links = { SM8250_MASTER_CNOC_DC_NOC },
899
+
.link_nodes = { &qhm_cnoc_dc_noc },
839
900
};
840
901
841
902
static struct qcom_icc_node qhs_display_cfg = {
842
903
.name = "qhs_display_cfg",
843
-
.id = SM8250_SLAVE_DISPLAY_CFG,
844
904
.channels = 1,
845
905
.buswidth = 4,
846
906
};
847
907
848
908
static struct qcom_icc_node qhs_gpuss_cfg = {
849
909
.name = "qhs_gpuss_cfg",
850
-
.id = SM8250_SLAVE_GRAPHICS_3D_CFG,
851
910
.channels = 1,
852
911
.buswidth = 8,
853
912
};
854
913
855
914
static struct qcom_icc_node qhs_imem_cfg = {
856
915
.name = "qhs_imem_cfg",
857
-
.id = SM8250_SLAVE_IMEM_CFG,
858
916
.channels = 1,
859
917
.buswidth = 4,
860
918
};
861
919
862
920
static struct qcom_icc_node qhs_ipa = {
863
921
.name = "qhs_ipa",
864
-
.id = SM8250_SLAVE_IPA_CFG,
865
922
.channels = 1,
866
923
.buswidth = 4,
867
924
};
868
925
869
926
static struct qcom_icc_node qhs_ipc_router = {
870
927
.name = "qhs_ipc_router",
871
-
.id = SM8250_SLAVE_IPC_ROUTER_CFG,
872
928
.channels = 1,
873
929
.buswidth = 4,
874
930
};
875
931
876
932
static struct qcom_icc_node qhs_lpass_cfg = {
877
933
.name = "qhs_lpass_cfg",
878
-
.id = SM8250_SLAVE_LPASS,
879
934
.channels = 1,
880
935
.buswidth = 4,
881
936
};
882
937
883
938
static struct qcom_icc_node qhs_mnoc_cfg = {
884
939
.name = "qhs_mnoc_cfg",
885
-
.id = SM8250_SLAVE_CNOC_MNOC_CFG,
886
940
.channels = 1,
887
941
.buswidth = 4,
888
942
.num_links = 1,
889
-
.links = { SM8250_MASTER_CNOC_MNOC_CFG },
943
+
.link_nodes = { &qhm_mnoc_cfg },
890
944
};
891
945
892
946
static struct qcom_icc_node qhs_npu_cfg = {
893
947
.name = "qhs_npu_cfg",
894
-
.id = SM8250_SLAVE_NPU_CFG,
895
948
.channels = 1,
896
949
.buswidth = 4,
897
950
.num_links = 1,
898
-
.links = { SM8250_MASTER_NPU_NOC_CFG },
951
+
.link_nodes = { &qhm_cfg },
899
952
};
900
953
901
954
static struct qcom_icc_node qhs_pcie0_cfg = {
902
955
.name = "qhs_pcie0_cfg",
903
-
.id = SM8250_SLAVE_PCIE_0_CFG,
904
956
.channels = 1,
905
957
.buswidth = 4,
906
958
};
907
959
908
960
static struct qcom_icc_node qhs_pcie1_cfg = {
909
961
.name = "qhs_pcie1_cfg",
910
-
.id = SM8250_SLAVE_PCIE_1_CFG,
911
962
.channels = 1,
912
963
.buswidth = 4,
913
964
};
914
965
915
966
static struct qcom_icc_node qhs_pcie_modem_cfg = {
916
967
.name = "qhs_pcie_modem_cfg",
917
-
.id = SM8250_SLAVE_PCIE_2_CFG,
918
968
.channels = 1,
919
969
.buswidth = 4,
920
970
};
921
971
922
972
static struct qcom_icc_node qhs_pdm = {
923
973
.name = "qhs_pdm",
924
-
.id = SM8250_SLAVE_PDM,
925
974
.channels = 1,
926
975
.buswidth = 4,
927
976
};
928
977
929
978
static struct qcom_icc_node qhs_pimem_cfg = {
930
979
.name = "qhs_pimem_cfg",
931
-
.id = SM8250_SLAVE_PIMEM_CFG,
932
980
.channels = 1,
933
981
.buswidth = 4,
934
982
};
935
983
936
984
static struct qcom_icc_node qhs_prng = {
937
985
.name = "qhs_prng",
938
-
.id = SM8250_SLAVE_PRNG,
939
986
.channels = 1,
940
987
.buswidth = 4,
941
988
};
942
989
943
990
static struct qcom_icc_node qhs_qdss_cfg = {
944
991
.name = "qhs_qdss_cfg",
945
-
.id = SM8250_SLAVE_QDSS_CFG,
946
992
.channels = 1,
947
993
.buswidth = 4,
948
994
};
949
995
950
996
static struct qcom_icc_node qhs_qspi = {
951
997
.name = "qhs_qspi",
952
-
.id = SM8250_SLAVE_QSPI_0,
953
998
.channels = 1,
954
999
.buswidth = 4,
955
1000
};
956
1001
957
1002
static struct qcom_icc_node qhs_qup0 = {
958
1003
.name = "qhs_qup0",
959
-
.id = SM8250_SLAVE_QUP_0,
960
1004
.channels = 1,
961
1005
.buswidth = 4,
962
1006
};
963
1007
964
1008
static struct qcom_icc_node qhs_qup1 = {
965
1009
.name = "qhs_qup1",
966
-
.id = SM8250_SLAVE_QUP_1,
967
1010
.channels = 1,
968
1011
.buswidth = 4,
969
1012
};
970
1013
971
1014
static struct qcom_icc_node qhs_qup2 = {
972
1015
.name = "qhs_qup2",
973
-
.id = SM8250_SLAVE_QUP_2,
974
1016
.channels = 1,
975
1017
.buswidth = 4,
976
1018
};
977
1019
978
1020
static struct qcom_icc_node qhs_sdc2 = {
979
1021
.name = "qhs_sdc2",
980
-
.id = SM8250_SLAVE_SDCC_2,
981
1022
.channels = 1,
982
1023
.buswidth = 4,
983
1024
};
984
1025
985
1026
static struct qcom_icc_node qhs_sdc4 = {
986
1027
.name = "qhs_sdc4",
987
-
.id = SM8250_SLAVE_SDCC_4,
988
1028
.channels = 1,
989
1029
.buswidth = 4,
990
1030
};
991
1031
992
1032
static struct qcom_icc_node qhs_snoc_cfg = {
993
1033
.name = "qhs_snoc_cfg",
994
-
.id = SM8250_SLAVE_SNOC_CFG,
995
1034
.channels = 1,
996
1035
.buswidth = 4,
997
1036
.num_links = 1,
998
-
.links = { SM8250_MASTER_SNOC_CFG },
1037
+
.link_nodes = { &qhm_snoc_cfg },
999
1038
};
1000
1039
1001
1040
static struct qcom_icc_node qhs_tcsr = {
1002
1041
.name = "qhs_tcsr",
1003
-
.id = SM8250_SLAVE_TCSR,
1004
1042
.channels = 1,
1005
1043
.buswidth = 4,
1006
1044
};
1007
1045
1008
1046
static struct qcom_icc_node qhs_tlmm0 = {
1009
1047
.name = "qhs_tlmm0",
1010
-
.id = SM8250_SLAVE_TLMM_NORTH,
1011
1048
.channels = 1,
1012
1049
.buswidth = 4,
1013
1050
};
1014
1051
1015
1052
static struct qcom_icc_node qhs_tlmm1 = {
1016
1053
.name = "qhs_tlmm1",
1017
-
.id = SM8250_SLAVE_TLMM_SOUTH,
1018
1054
.channels = 1,
1019
1055
.buswidth = 4,
1020
1056
};
1021
1057
1022
1058
static struct qcom_icc_node qhs_tlmm2 = {
1023
1059
.name = "qhs_tlmm2",
1024
-
.id = SM8250_SLAVE_TLMM_WEST,
1025
1060
.channels = 1,
1026
1061
.buswidth = 4,
1027
1062
};
1028
1063
1029
1064
static struct qcom_icc_node qhs_tsif = {
1030
1065
.name = "qhs_tsif",
1031
-
.id = SM8250_SLAVE_TSIF,
1032
1066
.channels = 1,
1033
1067
.buswidth = 4,
1034
1068
};
1035
1069
1036
1070
static struct qcom_icc_node qhs_ufs_card_cfg = {
1037
1071
.name = "qhs_ufs_card_cfg",
1038
-
.id = SM8250_SLAVE_UFS_CARD_CFG,
1039
1072
.channels = 1,
1040
1073
.buswidth = 4,
1041
1074
};
1042
1075
1043
1076
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1044
1077
.name = "qhs_ufs_mem_cfg",
1045
-
.id = SM8250_SLAVE_UFS_MEM_CFG,
1046
1078
.channels = 1,
1047
1079
.buswidth = 4,
1048
1080
};
1049
1081
1050
1082
static struct qcom_icc_node qhs_usb3_0 = {
1051
1083
.name = "qhs_usb3_0",
1052
-
.id = SM8250_SLAVE_USB3,
1053
1084
.channels = 1,
1054
1085
.buswidth = 4,
1055
1086
};
1056
1087
1057
1088
static struct qcom_icc_node qhs_usb3_1 = {
1058
1089
.name = "qhs_usb3_1",
1059
-
.id = SM8250_SLAVE_USB3_1,
1060
1090
.channels = 1,
1061
1091
.buswidth = 4,
1062
1092
};
1063
1093
1064
1094
static struct qcom_icc_node qhs_venus_cfg = {
1065
1095
.name = "qhs_venus_cfg",
1066
-
.id = SM8250_SLAVE_VENUS_CFG,
1067
1096
.channels = 1,
1068
1097
.buswidth = 4,
1069
1098
};
1070
1099
1071
1100
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1072
1101
.name = "qhs_vsense_ctrl_cfg",
1073
-
.id = SM8250_SLAVE_VSENSE_CTRL_CFG,
1074
1102
.channels = 1,
1075
1103
.buswidth = 4,
1076
1104
};
1077
1105
1078
1106
static struct qcom_icc_node qns_cnoc_a2noc = {
1079
1107
.name = "qns_cnoc_a2noc",
1080
-
.id = SM8250_SLAVE_CNOC_A2NOC,
1081
1108
.channels = 1,
1082
1109
.buswidth = 8,
1083
1110
.num_links = 1,
1084
-
.links = { SM8250_MASTER_CNOC_A2NOC },
1111
+
.link_nodes = { &qnm_cnoc },
1085
1112
};
1086
1113
1087
1114
static struct qcom_icc_node srvc_cnoc = {
1088
1115
.name = "srvc_cnoc",
1089
-
.id = SM8250_SLAVE_SERVICE_CNOC,
1090
1116
.channels = 1,
1091
1117
.buswidth = 4,
1092
1118
};
1093
1119
1094
1120
static struct qcom_icc_node qhs_llcc = {
1095
1121
.name = "qhs_llcc",
1096
-
.id = SM8250_SLAVE_LLCC_CFG,
1097
1122
.channels = 1,
1098
1123
.buswidth = 4,
1099
1124
};
1100
1125
1101
1126
static struct qcom_icc_node qhs_memnoc = {
1102
1127
.name = "qhs_memnoc",
1103
-
.id = SM8250_SLAVE_GEM_NOC_CFG,
1104
1128
.channels = 1,
1105
1129
.buswidth = 4,
1106
1130
.num_links = 1,
1107
-
.links = { SM8250_MASTER_GEM_NOC_CFG },
1131
+
.link_nodes = { &qhm_gemnoc_cfg },
1108
1132
};
1109
1133
1110
1134
static struct qcom_icc_node qns_gem_noc_snoc = {
1111
1135
.name = "qns_gem_noc_snoc",
1112
-
.id = SM8250_SLAVE_GEM_NOC_SNOC,
1113
1136
.channels = 1,
1114
1137
.buswidth = 16,
1115
1138
.num_links = 1,
1116
-
.links = { SM8250_MASTER_GEM_NOC_SNOC },
1139
+
.link_nodes = { &qnm_gemnoc },
1117
1140
};
1118
1141
1119
1142
static struct qcom_icc_node qns_llcc = {
1120
1143
.name = "qns_llcc",
1121
-
.id = SM8250_SLAVE_LLCC,
1122
1144
.channels = 4,
1123
1145
.buswidth = 16,
1124
1146
.num_links = 1,
1125
-
.links = { SM8250_MASTER_LLCC },
1147
+
.link_nodes = { &llcc_mc },
1126
1148
};
1127
1149
1128
1150
static struct qcom_icc_node qns_sys_pcie = {
1129
1151
.name = "qns_sys_pcie",
1130
-
.id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC,
1131
1152
.channels = 1,
1132
1153
.buswidth = 8,
1133
1154
.num_links = 1,
1134
-
.links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC },
1155
+
.link_nodes = { &qnm_gemnoc_pcie },
1135
1156
};
1136
1157
1137
1158
static struct qcom_icc_node srvc_even_gemnoc = {
1138
1159
.name = "srvc_even_gemnoc",
1139
-
.id = SM8250_SLAVE_SERVICE_GEM_NOC_1,
1140
1160
.channels = 1,
1141
1161
.buswidth = 4,
1142
1162
};
1143
1163
1144
1164
static struct qcom_icc_node srvc_odd_gemnoc = {
1145
1165
.name = "srvc_odd_gemnoc",
1146
-
.id = SM8250_SLAVE_SERVICE_GEM_NOC_2,
1147
1166
.channels = 1,
1148
1167
.buswidth = 4,
1149
1168
};
1150
1169
1151
1170
static struct qcom_icc_node srvc_sys_gemnoc = {
1152
1171
.name = "srvc_sys_gemnoc",
1153
-
.id = SM8250_SLAVE_SERVICE_GEM_NOC,
1154
1172
.channels = 1,
1155
1173
.buswidth = 4,
1156
1174
};
1157
1175
1158
1176
static struct qcom_icc_node ebi = {
1159
1177
.name = "ebi",
1160
-
.id = SM8250_SLAVE_EBI_CH0,
1161
1178
.channels = 4,
1162
1179
.buswidth = 4,
1163
1180
};
1164
1181
1165
1182
static struct qcom_icc_node qns_mem_noc_hf = {
1166
1183
.name = "qns_mem_noc_hf",
1167
-
.id = SM8250_SLAVE_MNOC_HF_MEM_NOC,
1168
1184
.channels = 2,
1169
1185
.buswidth = 32,
1170
1186
.num_links = 1,
1171
-
.links = { SM8250_MASTER_MNOC_HF_MEM_NOC },
1187
+
.link_nodes = { &qnm_mnoc_hf },
1172
1188
};
1173
1189
1174
1190
static struct qcom_icc_node qns_mem_noc_sf = {
1175
1191
.name = "qns_mem_noc_sf",
1176
-
.id = SM8250_SLAVE_MNOC_SF_MEM_NOC,
1177
1192
.channels = 2,
1178
1193
.buswidth = 32,
1179
1194
.num_links = 1,
1180
-
.links = { SM8250_MASTER_MNOC_SF_MEM_NOC },
1195
+
.link_nodes = { &qnm_mnoc_sf },
1181
1196
};
1182
1197
1183
1198
static struct qcom_icc_node srvc_mnoc = {
1184
1199
.name = "srvc_mnoc",
1185
-
.id = SM8250_SLAVE_SERVICE_MNOC,
1186
1200
.channels = 1,
1187
1201
.buswidth = 4,
1188
1202
};
1189
1203
1190
1204
static struct qcom_icc_node qhs_cal_dp0 = {
1191
1205
.name = "qhs_cal_dp0",
1192
-
.id = SM8250_SLAVE_NPU_CAL_DP0,
1193
1206
.channels = 1,
1194
1207
.buswidth = 4,
1195
1208
};
1196
1209
1197
1210
static struct qcom_icc_node qhs_cal_dp1 = {
1198
1211
.name = "qhs_cal_dp1",
1199
-
.id = SM8250_SLAVE_NPU_CAL_DP1,
1200
1212
.channels = 1,
1201
1213
.buswidth = 4,
1202
1214
};
1203
1215
1204
1216
static struct qcom_icc_node qhs_cp = {
1205
1217
.name = "qhs_cp",
1206
-
.id = SM8250_SLAVE_NPU_CP,
1207
1218
.channels = 1,
1208
1219
.buswidth = 4,
1209
1220
};
1210
1221
1211
1222
static struct qcom_icc_node qhs_dma_bwmon = {
1212
1223
.name = "qhs_dma_bwmon",
1213
-
.id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
1214
1224
.channels = 1,
1215
1225
.buswidth = 4,
1216
1226
};
1217
1227
1218
1228
static struct qcom_icc_node qhs_dpm = {
1219
1229
.name = "qhs_dpm",
1220
-
.id = SM8250_SLAVE_NPU_DPM,
1221
1230
.channels = 1,
1222
1231
.buswidth = 4,
1223
1232
};
1224
1233
1225
1234
static struct qcom_icc_node qhs_isense = {
1226
1235
.name = "qhs_isense",
1227
-
.id = SM8250_SLAVE_ISENSE_CFG,
1228
1236
.channels = 1,
1229
1237
.buswidth = 4,
1230
1238
};
1231
1239
1232
1240
static struct qcom_icc_node qhs_llm = {
1233
1241
.name = "qhs_llm",
1234
-
.id = SM8250_SLAVE_NPU_LLM_CFG,
1235
1242
.channels = 1,
1236
1243
.buswidth = 4,
1237
1244
};
1238
1245
1239
1246
static struct qcom_icc_node qhs_tcm = {
1240
1247
.name = "qhs_tcm",
1241
-
.id = SM8250_SLAVE_NPU_TCM,
1242
1248
.channels = 1,
1243
1249
.buswidth = 4,
1244
1250
};
1245
1251
1246
1252
static struct qcom_icc_node qns_npu_sys = {
1247
1253
.name = "qns_npu_sys",
1248
-
.id = SM8250_SLAVE_NPU_COMPUTE_NOC,
1249
1254
.channels = 2,
1250
1255
.buswidth = 32,
1251
1256
};
1252
1257
1253
1258
static struct qcom_icc_node srvc_noc = {
1254
1259
.name = "srvc_noc",
1255
-
.id = SM8250_SLAVE_SERVICE_NPU_NOC,
1256
1260
.channels = 1,
1257
1261
.buswidth = 4,
1258
1262
};
1259
1263
1260
1264
static struct qcom_icc_node qhs_apss = {
1261
1265
.name = "qhs_apss",
1262
-
.id = SM8250_SLAVE_APPSS,
1263
1266
.channels = 1,
1264
1267
.buswidth = 8,
1265
1268
};
1266
1269
1267
1270
static struct qcom_icc_node qns_cnoc = {
1268
1271
.name = "qns_cnoc",
1269
-
.id = SM8250_SNOC_CNOC_SLV,
1270
1272
.channels = 1,
1271
1273
.buswidth = 8,
1272
1274
.num_links = 1,
1273
-
.links = { SM8250_SNOC_CNOC_MAS },
1275
+
.link_nodes = { &qnm_snoc },
1274
1276
};
1275
1277
1276
1278
static struct qcom_icc_node qns_gemnoc_gc = {
1277
1279
.name = "qns_gemnoc_gc",
1278
-
.id = SM8250_SLAVE_SNOC_GEM_NOC_GC,
1279
1280
.channels = 1,
1280
1281
.buswidth = 8,
1281
1282
.num_links = 1,
1282
-
.links = { SM8250_MASTER_SNOC_GC_MEM_NOC },
1283
+
.link_nodes = { &qnm_snoc_gc },
1283
1284
};
1284
1285
1285
1286
static struct qcom_icc_node qns_gemnoc_sf = {
1286
1287
.name = "qns_gemnoc_sf",
1287
-
.id = SM8250_SLAVE_SNOC_GEM_NOC_SF,
1288
1288
.channels = 1,
1289
1289
.buswidth = 16,
1290
1290
.num_links = 1,
1291
-
.links = { SM8250_MASTER_SNOC_SF_MEM_NOC },
1291
+
.link_nodes = { &qnm_snoc_sf },
1292
1292
};
1293
1293
1294
1294
static struct qcom_icc_node qxs_imem = {
1295
1295
.name = "qxs_imem",
1296
-
.id = SM8250_SLAVE_OCIMEM,
1297
1296
.channels = 1,
1298
1297
.buswidth = 8,
1299
1298
};
1300
1299
1301
1300
static struct qcom_icc_node qxs_pimem = {
1302
1301
.name = "qxs_pimem",
1303
-
.id = SM8250_SLAVE_PIMEM,
1304
1302
.channels = 1,
1305
1303
.buswidth = 8,
1306
1304
};
1307
1305
1308
1306
static struct qcom_icc_node srvc_snoc = {
1309
1307
.name = "srvc_snoc",
1310
-
.id = SM8250_SLAVE_SERVICE_SNOC,
1311
1308
.channels = 1,
1312
1309
.buswidth = 4,
1313
1310
};
1314
1311
1315
1312
static struct qcom_icc_node xs_pcie_0 = {
1316
1313
.name = "xs_pcie_0",
1317
-
.id = SM8250_SLAVE_PCIE_0,
1318
1314
.channels = 1,
1319
1315
.buswidth = 8,
1320
1316
};
1321
1317
1322
1318
static struct qcom_icc_node xs_pcie_1 = {
1323
1319
.name = "xs_pcie_1",
1324
-
.id = SM8250_SLAVE_PCIE_1,
1325
1320
.channels = 1,
1326
1321
.buswidth = 8,
1327
1322
};
1328
1323
1329
1324
static struct qcom_icc_node xs_pcie_modem = {
1330
1325
.name = "xs_pcie_modem",
1331
-
.id = SM8250_SLAVE_PCIE_2,
1332
1326
.channels = 1,
1333
1327
.buswidth = 8,
1334
1328
};
1335
1329
1336
1330
static struct qcom_icc_node xs_qdss_stm = {
1337
1331
.name = "xs_qdss_stm",
1338
-
.id = SM8250_SLAVE_QDSS_STM,
1339
1332
.channels = 1,
1340
1333
.buswidth = 4,
1341
1334
};
1342
1335
1343
1336
static struct qcom_icc_node xs_sys_tcu_cfg = {
1344
1337
.name = "xs_sys_tcu_cfg",
1345
-
.id = SM8250_SLAVE_TCU,
1346
1338
.channels = 1,
1347
1339
.buswidth = 8,
1348
1340
};
1349
1341
1350
1342
static struct qcom_icc_node qup0_core_master = {
1351
1343
.name = "qup0_core_master",
1352
-
.id = SM8250_MASTER_QUP_CORE_0,
1353
1344
.channels = 1,
1354
1345
.buswidth = 4,
1355
1346
.num_links = 1,
1356
-
.links = { SM8250_SLAVE_QUP_CORE_0 },
1347
+
.link_nodes = { &qup0_core_slave },
1357
1348
};
1358
1349
1359
1350
static struct qcom_icc_node qup1_core_master = {
1360
1351
.name = "qup1_core_master",
1361
-
.id = SM8250_MASTER_QUP_CORE_1,
1362
1352
.channels = 1,
1363
1353
.buswidth = 4,
1364
1354
.num_links = 1,
1365
-
.links = { SM8250_SLAVE_QUP_CORE_1 },
1355
+
.link_nodes = { &qup1_core_slave },
1366
1356
};
1367
1357
1368
1358
static struct qcom_icc_node qup2_core_master = {
1369
1359
.name = "qup2_core_master",
1370
-
.id = SM8250_MASTER_QUP_CORE_2,
1371
1360
.channels = 1,
1372
1361
.buswidth = 4,
1373
1362
.num_links = 1,
1374
-
.links = { SM8250_SLAVE_QUP_CORE_2 },
1363
+
.link_nodes = { &qup2_core_slave },
1375
1364
};
1376
1365
1377
1366
static struct qcom_icc_node qup0_core_slave = {
1378
1367
.name = "qup0_core_slave",
1379
-
.id = SM8250_SLAVE_QUP_CORE_0,
1380
1368
.channels = 1,
1381
1369
.buswidth = 4,
1382
1370
};
1383
1371
1384
1372
static struct qcom_icc_node qup1_core_slave = {
1385
1373
.name = "qup1_core_slave",
1386
-
.id = SM8250_SLAVE_QUP_CORE_1,
1387
1374
.channels = 1,
1388
1375
.buswidth = 4,
1389
1376
};
1390
1377
1391
1378
static struct qcom_icc_node qup2_core_slave = {
1392
1379
.name = "qup2_core_slave",
1393
-
.id = SM8250_SLAVE_QUP_CORE_2,
1394
1380
.channels = 1,
1395
1381
.buswidth = 4,
1396
1382
};
-168
drivers/interconnect/qcom/sm8250.h
-168
drivers/interconnect/qcom/sm8250.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
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/*
3
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* Qualcomm #define SM8250 interconnect IDs
4
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*
5
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
6
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*/
7
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8
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H
9
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#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H
10
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11
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#define SM8250_A1NOC_SNOC_MAS 0
12
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#define SM8250_A1NOC_SNOC_SLV 1
13
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#define SM8250_A2NOC_SNOC_MAS 2
14
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#define SM8250_A2NOC_SNOC_SLV 3
15
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#define SM8250_MASTER_A1NOC_CFG 4
16
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#define SM8250_MASTER_A2NOC_CFG 5
17
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#define SM8250_MASTER_AMPSS_M0 6
18
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#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7
19
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#define SM8250_MASTER_CAMNOC_HF 8
20
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#define SM8250_MASTER_CAMNOC_ICP 9
21
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#define SM8250_MASTER_CAMNOC_SF 10
22
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#define SM8250_MASTER_CNOC_A2NOC 11
23
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#define SM8250_MASTER_CNOC_DC_NOC 12
24
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#define SM8250_MASTER_CNOC_MNOC_CFG 13
25
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#define SM8250_MASTER_COMPUTE_NOC 14
26
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#define SM8250_MASTER_CRYPTO_CORE_0 15
27
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#define SM8250_MASTER_GEM_NOC_CFG 16
28
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#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17
29
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#define SM8250_MASTER_GEM_NOC_SNOC 18
30
-
#define SM8250_MASTER_GIC 19
31
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#define SM8250_MASTER_GPU_TCU 20
32
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#define SM8250_MASTER_GRAPHICS_3D 21
33
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#define SM8250_MASTER_IPA 22
34
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/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */
35
-
#define SM8250_MASTER_LLCC 24
36
-
#define SM8250_MASTER_MDP_PORT0 25
37
-
#define SM8250_MASTER_MDP_PORT1 26
38
-
#define SM8250_MASTER_MNOC_HF_MEM_NOC 27
39
-
#define SM8250_MASTER_MNOC_SF_MEM_NOC 28
40
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#define SM8250_MASTER_NPU 29
41
-
#define SM8250_MASTER_NPU_CDP 30
42
-
#define SM8250_MASTER_NPU_NOC_CFG 31
43
-
#define SM8250_MASTER_NPU_SYS 32
44
-
#define SM8250_MASTER_PCIE 33
45
-
#define SM8250_MASTER_PCIE_1 34
46
-
#define SM8250_MASTER_PCIE_2 35
47
-
#define SM8250_MASTER_PIMEM 36
48
-
#define SM8250_MASTER_QDSS_BAM 37
49
-
#define SM8250_MASTER_QDSS_DAP 38
50
-
#define SM8250_MASTER_QDSS_ETR 39
51
-
#define SM8250_MASTER_QSPI_0 40
52
-
#define SM8250_MASTER_QUP_0 41
53
-
#define SM8250_MASTER_QUP_1 42
54
-
#define SM8250_MASTER_QUP_2 43
55
-
#define SM8250_MASTER_ROTATOR 44
56
-
#define SM8250_MASTER_SDCC_2 45
57
-
#define SM8250_MASTER_SDCC_4 46
58
-
#define SM8250_MASTER_SNOC_CFG 47
59
-
#define SM8250_MASTER_SNOC_GC_MEM_NOC 48
60
-
#define SM8250_MASTER_SNOC_SF_MEM_NOC 49
61
-
#define SM8250_MASTER_SYS_TCU 50
62
-
#define SM8250_MASTER_TSIF 51
63
-
#define SM8250_MASTER_UFS_CARD 52
64
-
#define SM8250_MASTER_UFS_MEM 53
65
-
#define SM8250_MASTER_USB3 54
66
-
#define SM8250_MASTER_USB3_1 55
67
-
#define SM8250_MASTER_VIDEO_P0 56
68
-
#define SM8250_MASTER_VIDEO_P1 57
69
-
#define SM8250_MASTER_VIDEO_PROC 58
70
-
#define SM8250_SLAVE_A1NOC_CFG 59
71
-
#define SM8250_SLAVE_A2NOC_CFG 60
72
-
#define SM8250_SLAVE_AHB2PHY_NORTH 61
73
-
#define SM8250_SLAVE_AHB2PHY_SOUTH 62
74
-
#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63
75
-
#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64
76
-
#define SM8250_SLAVE_AOSS 65
77
-
#define SM8250_SLAVE_APPSS 66
78
-
#define SM8250_SLAVE_CAMERA_CFG 67
79
-
#define SM8250_SLAVE_CDSP_CFG 68
80
-
#define SM8250_SLAVE_CDSP_MEM_NOC 69
81
-
#define SM8250_SLAVE_CLK_CTL 70
82
-
#define SM8250_SLAVE_CNOC_A2NOC 71
83
-
#define SM8250_SLAVE_CNOC_DDRSS 72
84
-
#define SM8250_SLAVE_CNOC_MNOC_CFG 73
85
-
#define SM8250_SLAVE_CRYPTO_0_CFG 74
86
-
#define SM8250_SLAVE_CX_RDPM 75
87
-
#define SM8250_SLAVE_DCC_CFG 76
88
-
#define SM8250_SLAVE_DISPLAY_CFG 77
89
-
#define SM8250_SLAVE_EBI_CH0 78
90
-
#define SM8250_SLAVE_GEM_NOC_CFG 79
91
-
#define SM8250_SLAVE_GEM_NOC_SNOC 80
92
-
#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
93
-
#define SM8250_SLAVE_IMEM_CFG 82
94
-
#define SM8250_SLAVE_IPA_CFG 83
95
-
/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
96
-
#define SM8250_SLAVE_IPC_ROUTER_CFG 85
97
-
#define SM8250_SLAVE_ISENSE_CFG 86
98
-
#define SM8250_SLAVE_LLCC 87
99
-
#define SM8250_SLAVE_LLCC_CFG 88
100
-
#define SM8250_SLAVE_LPASS 89
101
-
#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90
102
-
#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91
103
-
#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92
104
-
#define SM8250_SLAVE_NPU_CAL_DP0 93
105
-
#define SM8250_SLAVE_NPU_CAL_DP1 94
106
-
#define SM8250_SLAVE_NPU_CFG 95
107
-
#define SM8250_SLAVE_NPU_COMPUTE_NOC 96
108
-
#define SM8250_SLAVE_NPU_CP 97
109
-
#define SM8250_SLAVE_NPU_DPM 98
110
-
#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99
111
-
#define SM8250_SLAVE_NPU_LLM_CFG 100
112
-
#define SM8250_SLAVE_NPU_TCM 101
113
-
#define SM8250_SLAVE_OCIMEM 102
114
-
#define SM8250_SLAVE_PCIE_0 103
115
-
#define SM8250_SLAVE_PCIE_0_CFG 104
116
-
#define SM8250_SLAVE_PCIE_1 105
117
-
#define SM8250_SLAVE_PCIE_1_CFG 106
118
-
#define SM8250_SLAVE_PCIE_2 107
119
-
#define SM8250_SLAVE_PCIE_2_CFG 108
120
-
#define SM8250_SLAVE_PDM 109
121
-
#define SM8250_SLAVE_PIMEM 110
122
-
#define SM8250_SLAVE_PIMEM_CFG 111
123
-
#define SM8250_SLAVE_PRNG 112
124
-
#define SM8250_SLAVE_QDSS_CFG 113
125
-
#define SM8250_SLAVE_QDSS_STM 114
126
-
#define SM8250_SLAVE_QSPI_0 115
127
-
#define SM8250_SLAVE_QUP_0 116
128
-
#define SM8250_SLAVE_QUP_1 117
129
-
#define SM8250_SLAVE_QUP_2 118
130
-
#define SM8250_SLAVE_RBCPR_CX_CFG 119
131
-
#define SM8250_SLAVE_RBCPR_MMCX_CFG 120
132
-
#define SM8250_SLAVE_RBCPR_MX_CFG 121
133
-
#define SM8250_SLAVE_SDCC_2 122
134
-
#define SM8250_SLAVE_SDCC_4 123
135
-
#define SM8250_SLAVE_SERVICE_A1NOC 124
136
-
#define SM8250_SLAVE_SERVICE_A2NOC 125
137
-
#define SM8250_SLAVE_SERVICE_CNOC 126
138
-
#define SM8250_SLAVE_SERVICE_GEM_NOC 127
139
-
#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128
140
-
#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129
141
-
#define SM8250_SLAVE_SERVICE_MNOC 130
142
-
#define SM8250_SLAVE_SERVICE_NPU_NOC 131
143
-
#define SM8250_SLAVE_SERVICE_SNOC 132
144
-
#define SM8250_SLAVE_SNOC_CFG 133
145
-
#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134
146
-
#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135
147
-
#define SM8250_SLAVE_TCSR 136
148
-
#define SM8250_SLAVE_TCU 137
149
-
#define SM8250_SLAVE_TLMM_NORTH 138
150
-
#define SM8250_SLAVE_TLMM_SOUTH 139
151
-
#define SM8250_SLAVE_TLMM_WEST 140
152
-
#define SM8250_SLAVE_TSIF 141
153
-
#define SM8250_SLAVE_UFS_CARD_CFG 142
154
-
#define SM8250_SLAVE_UFS_MEM_CFG 143
155
-
#define SM8250_SLAVE_USB3 144
156
-
#define SM8250_SLAVE_USB3_1 145
157
-
#define SM8250_SLAVE_VENUS_CFG 146
158
-
#define SM8250_SLAVE_VSENSE_CTRL_CFG 147
159
-
#define SM8250_SNOC_CNOC_MAS 148
160
-
#define SM8250_SNOC_CNOC_SLV 149
161
-
#define SM8250_MASTER_QUP_CORE_0 150
162
-
#define SM8250_MASTER_QUP_CORE_1 151
163
-
#define SM8250_MASTER_QUP_CORE_2 152
164
-
#define SM8250_SLAVE_QUP_CORE_0 153
165
-
#define SM8250_SLAVE_QUP_CORE_1 154
166
-
#define SM8250_SLAVE_QUP_CORE_2 155
167
-
168
-
#endif