tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pmdomain: mediatek: Add support for MT8196 SCPSYS power domains
Add a new SPM bus protection block and add support for both the
direct control and HW Voter control SCPSYS power domains found
in the MT8196 and MT6991 SoCs.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
authored by
AngeloGioacchino Del Regno
and committed by
Ulf Hansson
5437b281
8e98bade
+404
-3
+386
drivers/pmdomain/mediatek/mt8196-pm-domains.h
+386
drivers/pmdomain/mediatek/mt8196-pm-domains.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2025 Collabora Ltd
4
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
5
+
*/
6
+
7
+
#ifndef __SOC_MEDIATEK_MT8196_PM_DOMAINS_H
8
+
#define __SOC_MEDIATEK_MT8196_PM_DOMAINS_H
9
+
10
+
#include "mtk-pm-domains.h"
11
+
#include <dt-bindings/power/mediatek,mt8196-power.h>
12
+
13
+
/*
14
+
* MT8196 and MT6991 power domain support
15
+
*/
16
+
17
+
/* INFRA TOP_AXI registers */
18
+
#define MT8196_TOP_AXI_PROT_EN_SET 0x4
19
+
#define MT8196_TOP_AXI_PROT_EN_CLR 0x8
20
+
#define MT8196_TOP_AXI_PROT_EN_STA 0xc
21
+
#define MT8196_TOP_AXI_PROT_EN_SLEEP0_MD BIT(29)
22
+
23
+
#define MT8196_TOP_AXI_PROT_EN_1_SET 0x24
24
+
#define MT8196_TOP_AXI_PROT_EN_1_CLR 0x28
25
+
#define MT8196_TOP_AXI_PROT_EN_1_STA 0x2c
26
+
#define MT8196_TOP_AXI_PROT_EN_1_SLEEP1_MD BIT(0)
27
+
28
+
/* SPM BUS_PROTECT registers */
29
+
#define MT8196_SPM_BUS_PROTECT_CON_SET 0xdc
30
+
#define MT8196_SPM_BUS_PROTECT_CON_CLR 0xe0
31
+
#define MT8196_SPM_BUS_PROTECT_RDY 0x208
32
+
#define MT8196_SPM_PROT_EN_BUS_CONN BIT(1)
33
+
#define MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0 BIT(6)
34
+
#define MT8196_SPM_PROT_EN_BUS_SSUSB_P0 BIT(7)
35
+
#define MT8196_SPM_PROT_EN_BUS_SSUSB_P1 BIT(8)
36
+
#define MT8196_SPM_PROT_EN_BUS_SSUSB_P23 BIT(9)
37
+
#define MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2 BIT(10)
38
+
#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0 BIT(13)
39
+
#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1 BIT(14)
40
+
#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2 BIT(15)
41
+
#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0 BIT(16)
42
+
#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1 BIT(17)
43
+
#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2 BIT(18)
44
+
#define MT8196_SPM_PROT_EN_BUS_AUDIO BIT(19)
45
+
#define MT8196_SPM_PROT_EN_BUS_ADSP_TOP BIT(21)
46
+
#define MT8196_SPM_PROT_EN_BUS_ADSP_INFRA BIT(22)
47
+
#define MT8196_SPM_PROT_EN_BUS_ADSP_AO BIT(23)
48
+
#define MT8196_SPM_PROT_EN_BUS_MM_PROC BIT(24)
49
+
50
+
/* PWR_CON registers */
51
+
#define MT8196_PWR_ACK BIT(30)
52
+
#define MT8196_PWR_ACK_2ND BIT(31)
53
+
54
+
static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8196[] = {
55
+
BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SPM
56
+
};
57
+
58
+
static const struct scpsys_domain_data scpsys_domain_data_mt8196[] = {
59
+
[MT8196_POWER_DOMAIN_MD] = {
60
+
.name = "md",
61
+
.sta_mask = MT8196_PWR_ACK,
62
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
63
+
.ctl_offs = 0xe00,
64
+
.pwr_sta_offs = 0xe00,
65
+
.pwr_sta2nd_offs = 0xe00,
66
+
.ext_buck_iso_offs = 0xefc,
67
+
.ext_buck_iso_mask = GENMASK(1, 0),
68
+
.bp_cfg = {
69
+
BUS_PROT_WR_IGN(INFRA, MT8196_TOP_AXI_PROT_EN_SLEEP0_MD,
70
+
MT8196_TOP_AXI_PROT_EN_SET,
71
+
MT8196_TOP_AXI_PROT_EN_CLR,
72
+
MT8196_TOP_AXI_PROT_EN_STA),
73
+
BUS_PROT_WR_IGN(INFRA, MT8196_TOP_AXI_PROT_EN_1_SLEEP1_MD,
74
+
MT8196_TOP_AXI_PROT_EN_1_SET,
75
+
MT8196_TOP_AXI_PROT_EN_1_CLR,
76
+
MT8196_TOP_AXI_PROT_EN_1_STA),
77
+
},
78
+
.caps = MTK_SCPD_MODEM_PWRSEQ | MTK_SCPD_EXT_BUCK_ISO |
79
+
MTK_SCPD_SKIP_RESET_B | MTK_SCPD_KEEP_DEFAULT_OFF,
80
+
},
81
+
[MT8196_POWER_DOMAIN_CONN] = {
82
+
.name = "conn",
83
+
.sta_mask = MT8196_PWR_ACK,
84
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
85
+
.ctl_offs = 0xe04,
86
+
.pwr_sta_offs = 0xe04,
87
+
.pwr_sta2nd_offs = 0xe04,
88
+
.bp_cfg = {
89
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_CONN,
90
+
MT8196_SPM_BUS_PROTECT_CON_SET,
91
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
92
+
MT8196_SPM_BUS_PROTECT_RDY),
93
+
},
94
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
95
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
96
+
},
97
+
[MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0] = {
98
+
.name = "ssusb-dp-phy-p0",
99
+
.sta_mask = MT8196_PWR_ACK,
100
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
101
+
.ctl_offs = 0xe18,
102
+
.pwr_sta_offs = 0xe18,
103
+
.pwr_sta2nd_offs = 0xe18,
104
+
.bp_cfg = {
105
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0,
106
+
MT8196_SPM_BUS_PROTECT_CON_SET,
107
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
108
+
MT8196_SPM_BUS_PROTECT_RDY),
109
+
},
110
+
.caps = MTK_SCPD_ALWAYS_ON,
111
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
112
+
},
113
+
[MT8196_POWER_DOMAIN_SSUSB_P0] = {
114
+
.name = "ssusb-p0",
115
+
.sta_mask = MT8196_PWR_ACK,
116
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
117
+
.ctl_offs = 0xe1c,
118
+
.pwr_sta_offs = 0xe1c,
119
+
.pwr_sta2nd_offs = 0xe1c,
120
+
.sram_pdn_bits = BIT(8),
121
+
.sram_pdn_ack_bits = BIT(12),
122
+
.bp_cfg = {
123
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_P0,
124
+
MT8196_SPM_BUS_PROTECT_CON_SET,
125
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
126
+
MT8196_SPM_BUS_PROTECT_RDY),
127
+
},
128
+
.caps = MTK_SCPD_ALWAYS_ON,
129
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
130
+
},
131
+
[MT8196_POWER_DOMAIN_SSUSB_P1] = {
132
+
.name = "ssusb-p1",
133
+
.sta_mask = MT8196_PWR_ACK,
134
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
135
+
.ctl_offs = 0xe20,
136
+
.pwr_sta_offs = 0xe20,
137
+
.pwr_sta2nd_offs = 0xe20,
138
+
.sram_pdn_bits = BIT(8),
139
+
.sram_pdn_ack_bits = BIT(12),
140
+
.bp_cfg = {
141
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_P1,
142
+
MT8196_SPM_BUS_PROTECT_CON_SET,
143
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
144
+
MT8196_SPM_BUS_PROTECT_RDY),
145
+
},
146
+
.caps = MTK_SCPD_ALWAYS_ON,
147
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
148
+
},
149
+
[MT8196_POWER_DOMAIN_SSUSB_P23] = {
150
+
.name = "ssusb-p23",
151
+
.sta_mask = MT8196_PWR_ACK,
152
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
153
+
.ctl_offs = 0xe24,
154
+
.pwr_sta_offs = 0xe24,
155
+
.pwr_sta2nd_offs = 0xe24,
156
+
.bp_cfg = {
157
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_P23,
158
+
MT8196_SPM_BUS_PROTECT_CON_SET,
159
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
160
+
MT8196_SPM_BUS_PROTECT_RDY),
161
+
},
162
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
163
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
164
+
},
165
+
[MT8196_POWER_DOMAIN_SSUSB_PHY_P2] = {
166
+
.name = "ssusb-phy-p2",
167
+
.sta_mask = MT8196_PWR_ACK,
168
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
169
+
.ctl_offs = 0xe28,
170
+
.pwr_sta_offs = 0xe28,
171
+
.pwr_sta2nd_offs = 0xe28,
172
+
.sram_pdn_bits = BIT(8),
173
+
.sram_pdn_ack_bits = BIT(12),
174
+
.bp_cfg = {
175
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2,
176
+
MT8196_SPM_BUS_PROTECT_CON_SET,
177
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
178
+
MT8196_SPM_BUS_PROTECT_RDY),
179
+
},
180
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
181
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
182
+
},
183
+
[MT8196_POWER_DOMAIN_PEXTP_MAC0] = {
184
+
.name = "pextp-mac0",
185
+
.sta_mask = MT8196_PWR_ACK,
186
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
187
+
.ctl_offs = 0xe34,
188
+
.pwr_sta_offs = 0xe34,
189
+
.pwr_sta2nd_offs = 0xe34,
190
+
.sram_pdn_bits = BIT(8),
191
+
.sram_pdn_ack_bits = BIT(12),
192
+
.bp_cfg = {
193
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0,
194
+
MT8196_SPM_BUS_PROTECT_CON_SET,
195
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
196
+
MT8196_SPM_BUS_PROTECT_RDY),
197
+
},
198
+
.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
199
+
},
200
+
[MT8196_POWER_DOMAIN_PEXTP_MAC1] = {
201
+
.name = "pextp-mac1",
202
+
.sta_mask = MT8196_PWR_ACK,
203
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
204
+
.ctl_offs = 0xe38,
205
+
.pwr_sta_offs = 0xe38,
206
+
.pwr_sta2nd_offs = 0xe38,
207
+
.sram_pdn_bits = BIT(8),
208
+
.sram_pdn_ack_bits = BIT(12),
209
+
.bp_cfg = {
210
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1,
211
+
MT8196_SPM_BUS_PROTECT_CON_SET,
212
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
213
+
MT8196_SPM_BUS_PROTECT_RDY),
214
+
},
215
+
.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
216
+
},
217
+
[MT8196_POWER_DOMAIN_PEXTP_MAC2] = {
218
+
.name = "pextp-mac2",
219
+
.sta_mask = MT8196_PWR_ACK,
220
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
221
+
.ctl_offs = 0xe3c,
222
+
.pwr_sta_offs = 0xe3c,
223
+
.pwr_sta2nd_offs = 0xe3c,
224
+
.sram_pdn_bits = BIT(8),
225
+
.sram_pdn_ack_bits = BIT(12),
226
+
.bp_cfg = {
227
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2,
228
+
MT8196_SPM_BUS_PROTECT_CON_SET,
229
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
230
+
MT8196_SPM_BUS_PROTECT_RDY),
231
+
},
232
+
.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
233
+
},
234
+
[MT8196_POWER_DOMAIN_PEXTP_PHY0] = {
235
+
.name = "pextp-phy0",
236
+
.sta_mask = MT8196_PWR_ACK,
237
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
238
+
.ctl_offs = 0xe40,
239
+
.pwr_sta_offs = 0xe40,
240
+
.pwr_sta2nd_offs = 0xe40,
241
+
.bp_cfg = {
242
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0,
243
+
MT8196_SPM_BUS_PROTECT_CON_SET,
244
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
245
+
MT8196_SPM_BUS_PROTECT_RDY),
246
+
},
247
+
.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
248
+
},
249
+
[MT8196_POWER_DOMAIN_PEXTP_PHY1] = {
250
+
.name = "pextp-phy1",
251
+
.sta_mask = MT8196_PWR_ACK,
252
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
253
+
.ctl_offs = 0xe44,
254
+
.pwr_sta_offs = 0xe44,
255
+
.pwr_sta2nd_offs = 0xe44,
256
+
.bp_cfg = {
257
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1,
258
+
MT8196_SPM_BUS_PROTECT_CON_SET,
259
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
260
+
MT8196_SPM_BUS_PROTECT_RDY),
261
+
},
262
+
.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
263
+
},
264
+
[MT8196_POWER_DOMAIN_PEXTP_PHY2] = {
265
+
.name = "pextp-phy2",
266
+
.sta_mask = MT8196_PWR_ACK,
267
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
268
+
.ctl_offs = 0xe48,
269
+
.pwr_sta_offs = 0xe48,
270
+
.pwr_sta2nd_offs = 0xe48,
271
+
.bp_cfg = {
272
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2,
273
+
MT8196_SPM_BUS_PROTECT_CON_SET,
274
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
275
+
MT8196_SPM_BUS_PROTECT_RDY),
276
+
},
277
+
.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
278
+
},
279
+
[MT8196_POWER_DOMAIN_AUDIO] = {
280
+
.name = "audio",
281
+
.sta_mask = MT8196_PWR_ACK,
282
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
283
+
.ctl_offs = 0xe4c,
284
+
.pwr_sta_offs = 0xe4c,
285
+
.pwr_sta2nd_offs = 0xe4c,
286
+
.sram_pdn_bits = BIT(8),
287
+
.sram_pdn_ack_bits = BIT(12),
288
+
.bp_cfg = {
289
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_AUDIO,
290
+
MT8196_SPM_BUS_PROTECT_CON_SET,
291
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
292
+
MT8196_SPM_BUS_PROTECT_RDY),
293
+
},
294
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
295
+
},
296
+
[MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT] = {
297
+
.name = "adsp-top-dormant",
298
+
.sta_mask = MT8196_PWR_ACK,
299
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
300
+
.ctl_offs = 0xe54,
301
+
.pwr_sta_offs = 0xe54,
302
+
.pwr_sta2nd_offs = 0xe54,
303
+
/* Note: This is not managing powerdown (pdn), but sleep instead (slp) */
304
+
.sram_pdn_bits = BIT(9),
305
+
.sram_pdn_ack_bits = BIT(13),
306
+
.bp_cfg = {
307
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_ADSP_TOP,
308
+
MT8196_SPM_BUS_PROTECT_CON_SET,
309
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
310
+
MT8196_SPM_BUS_PROTECT_RDY),
311
+
},
312
+
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED,
313
+
},
314
+
[MT8196_POWER_DOMAIN_ADSP_INFRA] = {
315
+
.name = "adsp-infra",
316
+
.sta_mask = MT8196_PWR_ACK,
317
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
318
+
.ctl_offs = 0xe58,
319
+
.pwr_sta_offs = 0xe58,
320
+
.pwr_sta2nd_offs = 0xe58,
321
+
.bp_cfg = {
322
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_ADSP_INFRA,
323
+
MT8196_SPM_BUS_PROTECT_CON_SET,
324
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
325
+
MT8196_SPM_BUS_PROTECT_RDY),
326
+
},
327
+
.caps = MTK_SCPD_ALWAYS_ON,
328
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
329
+
},
330
+
[MT8196_POWER_DOMAIN_ADSP_AO] = {
331
+
.name = "adsp-ao",
332
+
.sta_mask = MT8196_PWR_ACK,
333
+
.sta2nd_mask = MT8196_PWR_ACK_2ND,
334
+
.ctl_offs = 0xe5c,
335
+
.pwr_sta_offs = 0xe5c,
336
+
.pwr_sta2nd_offs = 0xe5c,
337
+
.bp_cfg = {
338
+
BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_ADSP_AO,
339
+
MT8196_SPM_BUS_PROTECT_CON_SET,
340
+
MT8196_SPM_BUS_PROTECT_CON_CLR,
341
+
MT8196_SPM_BUS_PROTECT_RDY),
342
+
},
343
+
.caps = MTK_SCPD_ALWAYS_ON,
344
+
.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
345
+
},
346
+
};
347
+
348
+
static const struct scpsys_hwv_domain_data scpsys_hwv_domain_data_mt8196[] = {
349
+
[MT8196_POWER_DOMAIN_MM_PROC_DORMANT] = {
350
+
.name = "mm-proc-dormant",
351
+
.set = 0x0218,
352
+
.clr = 0x021c,
353
+
.done = 0x141c,
354
+
.en = 0x1410,
355
+
.set_sta = 0x146c,
356
+
.clr_sta = 0x1470,
357
+
.setclr_bit = 0,
358
+
.caps = MTK_SCPD_ALWAYS_ON,
359
+
},
360
+
[MT8196_POWER_DOMAIN_SSR] = {
361
+
.name = "ssrsys",
362
+
.set = 0x0218,
363
+
.clr = 0x021c,
364
+
.done = 0x141c,
365
+
.en = 0x1410,
366
+
.set_sta = 0x146c,
367
+
.clr_sta = 0x1470,
368
+
.setclr_bit = 1,
369
+
},
370
+
};
371
+
372
+
static const struct scpsys_soc_data mt8196_scpsys_data = {
373
+
.domains_data = scpsys_domain_data_mt8196,
374
+
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8196),
375
+
.bus_prot_blocks = scpsys_bus_prot_blocks_mt8196,
376
+
.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8196),
377
+
.type = SCPSYS_MTCMOS_TYPE_DIRECT_CTL,
378
+
};
379
+
380
+
static const struct scpsys_soc_data mt8196_scpsys_hwv_data = {
381
+
.hwv_domains_data = scpsys_hwv_domain_data_mt8196,
382
+
.num_hwv_domains = ARRAY_SIZE(scpsys_hwv_domain_data_mt8196),
383
+
.type = SCPSYS_MTCMOS_TYPE_HW_VOTER,
384
+
};
385
+
386
+
#endif /* __SOC_MEDIATEK_MT8196_PM_DOMAINS_H */
+15
-3
drivers/pmdomain/mediatek/mtk-pm-domains.c
+15
-3
drivers/pmdomain/mediatek/mtk-pm-domains.c
···
27
27
#include "mt8188-pm-domains.h"
28
28
#include "mt8192-pm-domains.h"
29
29
#include "mt8195-pm-domains.h"
30
+
#include "mt8196-pm-domains.h"
30
31
#include "mt8365-pm-domains.h"
31
32
32
33
#define MTK_POLL_DELAY_US 10
···
82
81
static bool scpsys_domain_is_on(struct scpsys_domain *pd)
83
82
{
84
83
struct scpsys *scpsys = pd->scpsys;
85
-
u32 status, status2;
84
+
u32 mask = pd->data->sta_mask;
85
+
u32 status, status2, mask2;
86
+
87
+
mask2 = pd->data->sta2nd_mask ? pd->data->sta2nd_mask : mask;
86
88
87
89
regmap_read(scpsys->base, pd->data->pwr_sta_offs, &status);
88
-
status &= pd->data->sta_mask;
90
+
status &= mask;
89
91
90
92
regmap_read(scpsys->base, pd->data->pwr_sta2nd_offs, &status2);
91
-
status2 &= pd->data->sta_mask;
93
+
status2 &= mask2;
92
94
93
95
/* A domain is on when both status bits are set. */
94
96
return status && status2;
···
1153
1149
{
1154
1150
.compatible = "mediatek,mt8195-power-controller",
1155
1151
.data = &mt8195_scpsys_data,
1152
+
},
1153
+
{
1154
+
.compatible = "mediatek,mt8196-power-controller",
1155
+
.data = &mt8196_scpsys_data,
1156
+
},
1157
+
{
1158
+
.compatible = "mediatek,mt8196-hwv-scp-power-controller",
1159
+
.data = &mt8196_scpsys_hwv_data,
1156
1160
},
1157
1161
{
1158
1162
.compatible = "mediatek,mt8365-power-controller",
+3
drivers/pmdomain/mediatek/mtk-pm-domains.h
+3
drivers/pmdomain/mediatek/mtk-pm-domains.h
···
62
62
BUS_PROT_BLOCK_INFRA,
63
63
BUS_PROT_BLOCK_INFRA_NAO,
64
64
BUS_PROT_BLOCK_SMI,
65
+
BUS_PROT_BLOCK_SPM,
65
66
BUS_PROT_BLOCK_COUNT,
66
67
};
67
68
···
144
143
* struct scpsys_domain_data - scp domain data for power on/off flow
145
144
* @name: The name of the power domain.
146
145
* @sta_mask: The mask for power on/off status bit.
146
+
* @sta2nd_mask: The mask for second power on/off status bit.
147
147
* @ctl_offs: The offset for main power control register.
148
148
* @sram_pdn_bits: The mask for sram power control bits.
149
149
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
···
157
155
struct scpsys_domain_data {
158
156
const char *name;
159
157
u32 sta_mask;
158
+
u32 sta2nd_mask;
160
159
int ctl_offs;
161
160
u32 sram_pdn_bits;
162
161
u32 sram_pdn_ack_bits;