···11+Binding for the AXS10x reset controller22+33+This binding describes the ARC AXS10x boards custom IP-block which allows44+to control reset signals of selected peripherals. For example DW GMAC, etc...55+This block is controlled via memory-mapped register (AKA CREG) which66+represents up-to 32 reset lines.77+88+As of today only the following lines are used:99+ - DW GMAC - line 51010+1111+This binding uses the common reset binding[1].1212+1313+[1] Documentation/devicetree/bindings/reset/reset.txt1414+1515+Required properties:1616+- compatible: should be "snps,axs10x-reset".1717+- reg: should always contain pair address - length: for creg reset1818+ bits register.1919+- #reset-cells: from common reset binding; Should always be set to 1.2020+2121+Example:2222+ reset: reset-controller@11220 {2323+ compatible = "snps,axs10x-reset";2424+ #reset-cells = <1>;2525+ reg = <0x11220 0x4>;2626+ };2727+2828+Specifying reset lines connected to IP modules:2929+ ethernet@.... {3030+ ....3131+ resets = <&reset 5>;3232+ ....3333+ };