Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: bcm: rpi: Set a default minimum rate

The M2MC clock provides the state machine clock for both HDMI
controllers.

However, if no HDMI monitor is plugged in at boot, its clock rate will
be left at 0 by the firmware and will make any register access end up in
a CPU stall, even though the clock was enabled.

We had some code in the HDMI controller to deal with this before, but it
makes more sense to have it in the clock driver. Move it there.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220225143534.405820-10-maxime@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Maxime Ripard and committed by
Stephen Boyd
542acfec 12c90f3f

+26
+26
drivers/clk/bcm/clk-raspberrypi.c
··· 76 76 struct raspberrypi_clk_variant { 77 77 bool export; 78 78 char *clkdev; 79 + unsigned long min_rate; 79 80 }; 80 81 81 82 static struct raspberrypi_clk_variant ··· 90 89 }, 91 90 [RPI_FIRMWARE_M2MC_CLK_ID] = { 92 91 .export = true, 92 + 93 + /* 94 + * If we boot without any cable connected to any of the 95 + * HDMI connector, the firmware will skip the HSM 96 + * initialization and leave it with a rate of 0, 97 + * resulting in a bus lockup when we're accessing the 98 + * registers even if it's enabled. 99 + * 100 + * Let's put a sensible default so that we don't end up 101 + * in this situation. 102 + */ 103 + .min_rate = 120000000, 93 104 }, 94 105 [RPI_FIRMWARE_V3D_CLK_ID] = { 95 106 .export = true, ··· 277 264 if (ret) { 278 265 dev_err(rpi->dev, "Failed to initialize clkdev\n"); 279 266 return ERR_PTR(ret); 267 + } 268 + } 269 + 270 + if (variant->min_rate) { 271 + unsigned long rate; 272 + 273 + clk_hw_set_rate_range(&data->hw, variant->min_rate, max_rate); 274 + 275 + rate = raspberrypi_fw_get_rate(&data->hw, 0); 276 + if (rate < variant->min_rate) { 277 + ret = raspberrypi_fw_set_rate(&data->hw, variant->min_rate, 0); 278 + if (ret) 279 + return ERR_PTR(ret); 280 280 } 281 281 } 282 282