tjh.dev / kernel
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staging: xillybus: Register's address offset notation update

In iowrite32() calls, the address of registers was expressed as e.g.
&ep->registers[fpga_msg_ctrl_reg]. This changes to the more common format
e.g. ep->registers + fpga_msg_ctrl_reg.

There is no functional change.

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Eli Billauer and committed by
Greg Kroah-Hartman 539889ee 049c1fb4

+45 -45
+1 -1
drivers/staging/xillybus/xillybus.h
··· 99 99 100 100 struct list_head ep_list; 101 101 int dma_using_dac; /* =1 if 64-bit DMA is used, =0 otherwise. */ 102 - __iomem u32 *registers; 102 + __iomem void *registers; 103 103 int fatal_error; 104 104 105 105 struct mutex register_mutex;
+44 -44
drivers/staging/xillybus/xillybus_core.c
··· 44 44 #define XILLY_RX_TIMEOUT (10*HZ/1000) 45 45 #define XILLY_TIMEOUT (100*HZ/1000) 46 46 47 - #define fpga_msg_ctrl_reg 0x0002 48 - #define fpga_dma_control_reg 0x0008 49 - #define fpga_dma_bufno_reg 0x0009 50 - #define fpga_dma_bufaddr_lowaddr_reg 0x000a 51 - #define fpga_dma_bufaddr_highaddr_reg 0x000b 52 - #define fpga_buf_ctrl_reg 0x000c 53 - #define fpga_buf_offset_reg 0x000d 54 - #define fpga_endian_reg 0x0010 47 + #define fpga_msg_ctrl_reg 0x0008 48 + #define fpga_dma_control_reg 0x0020 49 + #define fpga_dma_bufno_reg 0x0024 50 + #define fpga_dma_bufaddr_lowaddr_reg 0x0028 51 + #define fpga_dma_bufaddr_highaddr_reg 0x002c 52 + #define fpga_buf_ctrl_reg 0x0030 53 + #define fpga_buf_offset_reg 0x0034 54 + #define fpga_endian_reg 0x0040 55 55 56 56 #define XILLYMSG_OPCODE_RELEASEBUF 1 57 57 #define XILLYMSG_OPCODE_QUIESCEACK 2 ··· 170 170 DMA_FROM_DEVICE); 171 171 172 172 iowrite32(0x01, /* Message NACK */ 173 - &ep->registers[fpga_msg_ctrl_reg]); 173 + ep->registers + fpga_msg_ctrl_reg); 174 174 } 175 175 return IRQ_HANDLED; 176 176 } else if (buf[i] & (1 << 22)) /* Last message */ ··· 305 305 306 306 ep->msg_counter = (ep->msg_counter + 1) & 0xf; 307 307 ep->failed_messages = 0; 308 - iowrite32(0x03, &ep->registers[fpga_msg_ctrl_reg]); /* Message ACK */ 308 + iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */ 309 309 310 310 return IRQ_HANDLED; 311 311 } ··· 387 387 return rc; 388 388 389 389 iowrite32((u32) (dma_addr & 0xffffffff), 390 - &ep->registers[fpga_dma_bufaddr_lowaddr_reg]); 390 + ep->registers + fpga_dma_bufaddr_lowaddr_reg); 391 391 iowrite32(((u32) ((((u64) dma_addr) >> 32) & 0xffffffff)), 392 - &ep->registers[fpga_dma_bufaddr_highaddr_reg]); 392 + ep->registers + fpga_dma_bufaddr_highaddr_reg); 393 393 mmiowb(); 394 394 395 395 if (buffers) { /* Not the message buffer */ ··· 398 398 buffers[i] = this_buffer++; 399 399 400 400 iowrite32(s->regdirection | s->nbuffer++, 401 - &ep->registers[fpga_dma_bufno_reg]); 401 + ep->registers + fpga_dma_bufno_reg); 402 402 } else { 403 403 ep->msgbuf_addr = s->salami; 404 404 ep->msgbuf_dma_addr = dma_addr; 405 405 ep->msg_buf_size = bytebufsize; 406 406 407 407 iowrite32(s->regdirection, 408 - &ep->registers[fpga_dma_bufno_reg]); 408 + ep->registers + fpga_dma_bufno_reg); 409 409 } 410 410 411 411 s->left_of_salami -= bytebufsize; ··· 640 640 641 641 iowrite32(1 | 642 642 (3 << 24), /* Opcode 3 for channel 0 = Send IDT */ 643 - &endpoint->registers[fpga_buf_ctrl_reg]); 643 + endpoint->registers + fpga_buf_ctrl_reg); 644 644 mmiowb(); /* Just to appear safe */ 645 645 646 646 wait_event_interruptible_timeout(channel->wr_wait, ··· 812 812 813 813 iowrite32(1 | (channel->chan_num << 1) 814 814 | (bufidx << 12), 815 - &channel->endpoint->registers[ 816 - fpga_buf_ctrl_reg]); 815 + channel->endpoint->registers + 816 + fpga_buf_ctrl_reg); 817 817 mmiowb(); /* Just to appear safe */ 818 818 } 819 819 ··· 899 899 mutex_lock(&channel->endpoint->register_mutex); 900 900 901 901 iowrite32(offsetlimit, 902 - &channel->endpoint->registers[ 903 - fpga_buf_offset_reg]); 902 + channel->endpoint->registers + 903 + fpga_buf_offset_reg); 904 904 mmiowb(); 905 905 906 906 iowrite32(1 | (channel->chan_num << 1) | 907 907 (2 << 24) | /* 2 = offset limit */ 908 908 (waiting_bufidx << 12), 909 - &channel->endpoint->registers[ 910 - fpga_buf_ctrl_reg]); 909 + channel->endpoint->registers + 910 + fpga_buf_ctrl_reg); 911 911 912 912 mmiowb(); /* Just to appear safe */ 913 913 ··· 999 999 iowrite32(1 | (channel->chan_num << 1) | 1000 1000 (3 << 24) | /* Opcode 3, flush it all! */ 1001 1001 (waiting_bufidx << 12), 1002 - &channel->endpoint->registers[ 1003 - fpga_buf_ctrl_reg]); 1002 + channel->endpoint->registers + 1003 + fpga_buf_ctrl_reg); 1004 1004 mmiowb(); /* Just to appear safe */ 1005 1005 } 1006 1006 ··· 1112 1112 mutex_lock(&channel->endpoint->register_mutex); 1113 1113 1114 1114 iowrite32(end_offset_plus1 - 1, 1115 - &channel->endpoint->registers[fpga_buf_offset_reg]); 1115 + channel->endpoint->registers + fpga_buf_offset_reg); 1116 1116 mmiowb(); 1117 1117 1118 1118 iowrite32((channel->chan_num << 1) | /* Channel ID */ 1119 1119 (2 << 24) | /* Opcode 2, submit buffer */ 1120 1120 (bufidx << 12), 1121 - &channel->endpoint->registers[fpga_buf_ctrl_reg]); 1121 + channel->endpoint->registers + fpga_buf_ctrl_reg); 1122 1122 mmiowb(); /* Just to appear safe */ 1123 1123 1124 1124 mutex_unlock(&channel->endpoint->register_mutex); ··· 1362 1362 mutex_lock(&channel->endpoint->register_mutex); 1363 1363 1364 1364 iowrite32(end_offset_plus1 - 1, 1365 - &channel->endpoint->registers[ 1366 - fpga_buf_offset_reg]); 1365 + channel->endpoint->registers + 1366 + fpga_buf_offset_reg); 1367 1367 mmiowb(); 1368 1368 iowrite32((channel->chan_num << 1) | 1369 1369 (2 << 24) | /* 2 = submit buffer */ 1370 1370 (bufidx << 12), 1371 - &channel->endpoint->registers[ 1372 - fpga_buf_ctrl_reg]); 1371 + channel->endpoint->registers + 1372 + fpga_buf_ctrl_reg); 1373 1373 mmiowb(); /* Just to appear safe */ 1374 1374 1375 1375 mutex_unlock(&channel->endpoint-> ··· 1564 1564 iowrite32(1 | (channel->chan_num << 1) | 1565 1565 (4 << 24) | /* Opcode 4, open channel */ 1566 1566 ((channel->wr_synchronous & 1) << 23), 1567 - &channel->endpoint->registers[ 1568 - fpga_buf_ctrl_reg]); 1567 + channel->endpoint->registers + 1568 + fpga_buf_ctrl_reg); 1569 1569 mmiowb(); /* Just to appear safe */ 1570 1570 } 1571 1571 ··· 1586 1586 1587 1587 iowrite32((channel->chan_num << 1) | 1588 1588 (4 << 24), /* Opcode 4, open channel */ 1589 - &channel->endpoint->registers[ 1590 - fpga_buf_ctrl_reg]); 1589 + channel->endpoint->registers + 1590 + fpga_buf_ctrl_reg); 1591 1591 mmiowb(); /* Just to appear safe */ 1592 1592 } 1593 1593 ··· 1639 1639 1640 1640 iowrite32((channel->chan_num << 1) | /* Channel ID */ 1641 1641 (5 << 24), /* Opcode 5, close channel */ 1642 - &channel->endpoint->registers[ 1643 - fpga_buf_ctrl_reg]); 1642 + channel->endpoint->registers + 1643 + fpga_buf_ctrl_reg); 1644 1644 mmiowb(); /* Just to appear safe */ 1645 1645 } 1646 1646 mutex_unlock(&channel->rd_mutex); ··· 1660 1660 1661 1661 iowrite32(1 | (channel->chan_num << 1) | 1662 1662 (5 << 24), /* Opcode 5, close channel */ 1663 - &channel->endpoint->registers[ 1664 - fpga_buf_ctrl_reg]); 1663 + channel->endpoint->registers + 1664 + fpga_buf_ctrl_reg); 1665 1665 mmiowb(); /* Just to appear safe */ 1666 1666 1667 1667 /* ··· 1766 1766 mutex_lock(&channel->endpoint->register_mutex); 1767 1767 1768 1768 iowrite32(pos >> channel->log2_element_size, 1769 - &channel->endpoint->registers[fpga_buf_offset_reg]); 1769 + channel->endpoint->registers + fpga_buf_offset_reg); 1770 1770 mmiowb(); 1771 1771 iowrite32((channel->chan_num << 1) | 1772 1772 (6 << 24), /* Opcode 6, set address */ 1773 - &channel->endpoint->registers[fpga_buf_ctrl_reg]); 1773 + channel->endpoint->registers + fpga_buf_ctrl_reg); 1774 1774 mmiowb(); /* Just to appear safe */ 1775 1775 1776 1776 mutex_unlock(&channel->endpoint->register_mutex); ··· 1987 1987 endpoint->idtlen = -1; 1988 1988 wmb(); /* Make sure idtlen is set before sending command */ 1989 1989 iowrite32((u32) (endpoint->dma_using_dac & 0x0001), 1990 - &endpoint->registers[fpga_dma_control_reg]); 1990 + endpoint->registers + fpga_dma_control_reg); 1991 1991 mmiowb(); 1992 1992 1993 1993 wait_event_interruptible_timeout(endpoint->ep_wait, ··· 2027 2027 * necessary. 2028 2028 */ 2029 2029 2030 - iowrite32(1, &endpoint->registers[fpga_endian_reg]); 2030 + iowrite32(1, endpoint->registers + fpga_endian_reg); 2031 2031 mmiowb(); /* Writes below are affected by the one above. */ 2032 2032 2033 2033 /* Bootstrap phase I: Allocate temporary message buffer */ ··· 2044 2044 return rc; 2045 2045 2046 2046 /* Clear the message subsystem (and counter in particular) */ 2047 - iowrite32(0x04, &endpoint->registers[fpga_msg_ctrl_reg]); 2047 + iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg); 2048 2048 mmiowb(); 2049 2049 2050 2050 endpoint->idtlen = -1; ··· 2056 2056 * buffer size. 2057 2057 */ 2058 2058 iowrite32((u32) (endpoint->dma_using_dac & 0x0001), 2059 - &endpoint->registers[fpga_dma_control_reg]); 2059 + endpoint->registers + fpga_dma_control_reg); 2060 2060 mmiowb(); 2061 2061 2062 2062 wait_event_interruptible_timeout(endpoint->ep_wait, ··· 2070 2070 2071 2071 /* Enable DMA */ 2072 2072 iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)), 2073 - &endpoint->registers[fpga_dma_control_reg]); 2073 + endpoint->registers + fpga_dma_control_reg); 2074 2074 mmiowb(); 2075 2075 2076 2076 /* Bootstrap phase II: Allocate buffer for IDT and obtain it */