···63 if (huge) {64#ifdef CONFIG_HUGETLB_PAGE65 psize = get_slice_psize(mm, addr);0066#else67 BUG();68 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */69#endif70- } else71 psize = pte_pagesize_index(mm, addr, pte);0000007273- /* Mask the address for the correct page size */74- addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);7576 /* Build full vaddr */77 if (!is_kernel_addr(addr)) {
···63 if (huge) {64#ifdef CONFIG_HUGETLB_PAGE65 psize = get_slice_psize(mm, addr);66+ /* Mask the address for the correct page size */67+ addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);68#else69 BUG();70 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */71#endif72+ } else {73 psize = pte_pagesize_index(mm, addr, pte);74+ /* Mask the address for the standard page size. If we75+ * have a 64k page kernel, but the hardware does not76+ * support 64k pages, this might be different from the77+ * hardware page size encoded in the slice table. */78+ addr &= PAGE_MASK;79+ }80008182 /* Build full vaddr */83 if (!is_kernel_addr(addr)) {