tjh.dev
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Merge tag 'keystone-reset-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
Merge "Keystone Reset driver for 3.16" from Santosh Shilimkar:
* tag 'keystone-reset-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
power: reset: keystone-reset: introduce keystone reset driver
Documentation: dt: add bindings for keystone pll control controller
Documentation: dt: add bindings for keystone reset driver
Signed-off-by: Olof Johansson <olof@lixom.net>
+262
+20
Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
+20
Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
···
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* Device tree bindings for Texas Instruments keystone pll controller
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The main pll controller used to drive theC66x CorePacs, the switch fabric,
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and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
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the NETCP modules) requires a PLL Controller to manage the various clock
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divisions, gating, and synchronization.
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Required properties:
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- compatible: "ti,keystone-pllctrl", "syscon"
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- reg: contains offset/length value for pll controller
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registers space.
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Example:
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pllctrl: pll-controller@0x02310000 {
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compatible = "ti,keystone-pllctrl", "syscon";
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reg = <0x02310000 0x200>;
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};
+67
Documentation/devicetree/bindings/power/reset/keystone-reset.txt
+67
Documentation/devicetree/bindings/power/reset/keystone-reset.txt
···
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* Device tree bindings for Texas Instruments keystone reset
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This node is intended to allow SoC reset in case of software reset
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of selected watchdogs.
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The Keystone SoCs can contain up to 4 watchdog timers to reset
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SoC. Each watchdog timer event input is connected to the Reset Mux
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block. The Reset Mux block can be configured to cause reset or not.
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Additionally soft or hard reset can be configured.
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Required properties:
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- compatible: ti,keystone-reset
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- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
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access pll controller registers and the offset to use
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reset control registers.
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- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
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access device state control registers and the offset
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in order to use mux block registers for all watchdogs.
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Optional properties:
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- ti,soft-reset: Boolean option indicating soft reset.
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By default hard reset is used.
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- ti,wdt-list: WDT list that can cause SoC reset. It's not related
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to WDT driver, it's just needed to enable a SoC related
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reset that's triggered by one of WDTs. The list is
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in format: <0>, <2>; It can be in random order and
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begins from 0 to 3, as keystone can contain up to 4 SoC
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reset watchdogs and can be in random order.
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Example 1:
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Setup keystone reset so that in case software reset or
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WDT0 is triggered it issues hard reset for SoC.
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pllctrl: pll-controller@02310000 {
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compatible = "ti,keystone-pllctrl", "syscon";
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reg = <0x02310000 0x200>;
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};
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devctrl: device-state-control@02620000 {
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compatible = "ti,keystone-devctrl", "syscon";
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reg = <0x02620000 0x1000>;
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};
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rstctrl: reset-controller {
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compatible = "ti,keystone-reset";
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>;
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};
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Example 2:
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Setup keystone reset so that in case of software reset or
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WDT0 or WDT2 is triggered it issues soft reset for SoC.
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rstctrl: reset-controller {
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compatible = "ti,keystone-reset";
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>, <2>;
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ti,soft-reset;
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};
+8
drivers/power/reset/Kconfig
+8
drivers/power/reset/Kconfig
+1
drivers/power/reset/Makefile
+1
drivers/power/reset/Makefile
+166
drivers/power/reset/keystone-reset.c
+166
drivers/power/reset/keystone-reset.c
···
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/*
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* TI keystone reboot driver
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*
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* Copyright (C) 2014 Texas Instruments Incorporated. http://www.ti.com/
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*
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* Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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#include <asm/system_misc.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_platform.h>
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#define RSTYPE_RG 0x0
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#define RSCTRL_RG 0x4
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#define RSCFG_RG 0x8
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#define RSISO_RG 0xc
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#define RSCTRL_KEY_MASK 0x0000ffff
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#define RSCTRL_RESET_MASK BIT(16)
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#define RSCTRL_KEY 0x5a69
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#define RSMUX_OMODE_MASK 0xe
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#define RSMUX_OMODE_RESET_ON 0xa
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#define RSMUX_OMODE_RESET_OFF 0x0
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#define RSMUX_LOCK_MASK 0x1
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#define RSMUX_LOCK_SET 0x1
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#define RSCFG_RSTYPE_SOFT 0x300f
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#define RSCFG_RSTYPE_HARD 0x0
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#define WDT_MUX_NUMBER 0x4
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static int rspll_offset;
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static struct regmap *pllctrl_regs;
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/**
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* rsctrl_enable_rspll_write - enable access to RSCTRL, RSCFG
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* To be able to access to RSCTRL, RSCFG registers
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* we have to write a key before
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*/
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static inline int rsctrl_enable_rspll_write(void)
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{
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return regmap_update_bits(pllctrl_regs, rspll_offset + RSCTRL_RG,
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RSCTRL_KEY_MASK, RSCTRL_KEY);
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}
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static void rsctrl_restart(enum reboot_mode mode, const char *cmd)
56
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{
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/* enable write access to RSTCTRL */
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rsctrl_enable_rspll_write();
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/* reset the SOC */
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regmap_update_bits(pllctrl_regs, rspll_offset + RSCTRL_RG,
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RSCTRL_RESET_MASK, 0);
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}
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static struct of_device_id rsctrl_of_match[] = {
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{.compatible = "ti,keystone-reset", },
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{},
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};
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static int rsctrl_probe(struct platform_device *pdev)
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{
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int i;
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int ret;
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u32 val;
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unsigned int rg;
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u32 rsmux_offset;
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struct regmap *devctrl_regs;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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if (!np)
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return -ENODEV;
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/* get regmaps */
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pllctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pll");
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if (IS_ERR(pllctrl_regs))
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return PTR_ERR(pllctrl_regs);
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devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-dev");
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if (IS_ERR(devctrl_regs))
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return PTR_ERR(devctrl_regs);
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ret = of_property_read_u32_index(np, "ti,syscon-pll", 1, &rspll_offset);
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if (ret) {
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dev_err(dev, "couldn't read the reset pll offset!\n");
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return -EINVAL;
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}
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ret = of_property_read_u32_index(np, "ti,syscon-dev", 1, &rsmux_offset);
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if (ret) {
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dev_err(dev, "couldn't read the rsmux offset!\n");
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return -EINVAL;
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}
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/* set soft/hard reset */
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val = of_property_read_bool(np, "ti,soft-reset");
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val = val ? RSCFG_RSTYPE_SOFT : RSCFG_RSTYPE_HARD;
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ret = rsctrl_enable_rspll_write();
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if (ret)
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return ret;
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ret = regmap_write(pllctrl_regs, rspll_offset + RSCFG_RG, val);
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if (ret)
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return ret;
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arm_pm_restart = rsctrl_restart;
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/* disable a reset isolation for all module clocks */
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ret = regmap_write(pllctrl_regs, rspll_offset + RSISO_RG, 0);
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if (ret)
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return ret;
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/* enable a reset for watchdogs from wdt-list */
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for (i = 0; i < WDT_MUX_NUMBER; i++) {
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ret = of_property_read_u32_index(np, "ti,wdt-list", i, &val);
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if (ret == -EOVERFLOW && !i) {
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dev_err(dev, "ti,wdt-list property has to contain at"
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"least one entry\n");
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return -EINVAL;
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} else if (ret) {
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break;
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}
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if (val >= WDT_MUX_NUMBER) {
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dev_err(dev, "ti,wdt-list property can contain"
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"only numbers < 4\n");
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return -EINVAL;
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}
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rg = rsmux_offset + val * 4;
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ret = regmap_update_bits(devctrl_regs, rg, RSMUX_OMODE_MASK,
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RSMUX_OMODE_RESET_ON |
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RSMUX_LOCK_SET);
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if (ret)
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return ret;
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}
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return 0;
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}
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static struct platform_driver rsctrl_driver = {
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.probe = rsctrl_probe,
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.driver = {
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.owner = THIS_MODULE,
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.name = KBUILD_MODNAME,
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.of_match_table = rsctrl_of_match,
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},
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};
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module_platform_driver(rsctrl_driver);
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MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
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MODULE_DESCRIPTION("Texas Instruments keystone reset driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" KBUILD_MODNAME);