tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

mtd: rawnand: Use nanddev_get/set_ecc_requirements() when relevant

Instead of accessing ->strength/step_size directly.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-15-miquel.raynal@bootlin.com

Miquel Raynal 53576c7b 3316c8e3

+144 -86
+6 -4
drivers/mtd/nand/raw/atmel/nand-controller.c
··· 1043 1043 1044 1044 static int atmel_nand_pmecc_init(struct nand_chip *chip) 1045 1045 { 1046 + const struct nand_ecc_props *requirements = 1047 + nanddev_get_ecc_requirements(&chip->base); 1046 1048 struct mtd_info *mtd = nand_to_mtd(chip); 1047 1049 struct atmel_nand *nand = to_atmel_nand(chip); 1048 1050 struct atmel_nand_controller *nc; ··· 1074 1072 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; 1075 1073 else if (chip->ecc.strength) 1076 1074 req.ecc.strength = chip->ecc.strength; 1077 - else if (chip->base.eccreq.strength) 1078 - req.ecc.strength = chip->base.eccreq.strength; 1075 + else if (requirements->strength) 1076 + req.ecc.strength = requirements->strength; 1079 1077 else 1080 1078 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; 1081 1079 1082 1080 if (chip->ecc.size) 1083 1081 req.ecc.sectorsize = chip->ecc.size; 1084 - else if (chip->base.eccreq.step_size) 1085 - req.ecc.sectorsize = chip->base.eccreq.step_size; 1082 + else if (requirements->step_size) 1083 + req.ecc.sectorsize = requirements->step_size; 1086 1084 else 1087 1085 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; 1088 1086
+5 -3
drivers/mtd/nand/raw/brcmnand/brcmnand.c
··· 2532 2532 { 2533 2533 struct mtd_info *mtd = nand_to_mtd(&host->chip); 2534 2534 struct nand_chip *chip = &host->chip; 2535 + const struct nand_ecc_props *requirements = 2536 + nanddev_get_ecc_requirements(&chip->base); 2535 2537 struct brcmnand_controller *ctrl = host->ctrl; 2536 2538 struct brcmnand_cfg *cfg = &host->hwcfg; 2537 2539 char msg[128]; ··· 2591 2589 2592 2590 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2593 2591 (!chip->ecc.size || !chip->ecc.strength)) { 2594 - if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { 2592 + if (requirements->step_size && requirements->strength) { 2595 2593 /* use detected ECC parameters */ 2596 - chip->ecc.size = chip->base.eccreq.step_size; 2597 - chip->ecc.strength = chip->base.eccreq.strength; 2594 + chip->ecc.size = requirements->step_size; 2595 + chip->ecc.strength = requirements->strength; 2598 2596 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", 2599 2597 chip->ecc.size, chip->ecc.strength); 2600 2598 }
+7 -6
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
··· 272 272 default: 273 273 dev_err(this->dev, 274 274 "unsupported nand chip. ecc bits : %d, ecc size : %d\n", 275 - chip->base.eccreq.strength, 276 - chip->base.eccreq.step_size); 275 + nanddev_get_ecc_requirements(&chip->base)->strength, 276 + nanddev_get_ecc_requirements(&chip->base)->step_size); 277 277 return -EINVAL; 278 278 } 279 279 geo->ecc_chunk_size = ecc_step; ··· 510 510 static int common_nfc_set_geometry(struct gpmi_nand_data *this) 511 511 { 512 512 struct nand_chip *chip = &this->nand; 513 + const struct nand_ecc_props *requirements = 514 + nanddev_get_ecc_requirements(&chip->base); 513 515 514 516 if (chip->ecc.strength > 0 && chip->ecc.size > 0) 515 517 return set_geometry_by_ecc_info(this, chip->ecc.strength, ··· 519 517 520 518 if ((of_property_read_bool(this->dev->of_node, "fsl,use-minimum-ecc")) 521 519 || legacy_set_geometry(this)) { 522 - if (!(chip->base.eccreq.strength > 0 && 523 - chip->base.eccreq.step_size > 0)) 520 + if (!(requirements->strength > 0 && requirements->step_size > 0)) 524 521 return -EINVAL; 525 522 526 523 return set_geometry_by_ecc_info(this, 527 - chip->base.eccreq.strength, 528 - chip->base.eccreq.step_size); 524 + requirements->strength, 525 + requirements->step_size); 529 526 } 530 527 531 528 return 0;
+5 -3
drivers/mtd/nand/raw/marvell_nand.c
··· 2247 2247 struct nand_ecc_ctrl *ecc) 2248 2248 { 2249 2249 struct nand_chip *chip = mtd_to_nand(mtd); 2250 + const struct nand_ecc_props *requirements = 2251 + nanddev_get_ecc_requirements(&chip->base); 2250 2252 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2251 2253 int ret; 2252 2254 2253 2255 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2254 2256 (!ecc->size || !ecc->strength)) { 2255 - if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { 2256 - ecc->size = chip->base.eccreq.step_size; 2257 - ecc->strength = chip->base.eccreq.strength; 2257 + if (requirements->step_size && requirements->strength) { 2258 + ecc->size = requirements->step_size; 2259 + ecc->strength = requirements->strength; 2258 2260 } else { 2259 2261 dev_info(nfc->dev, 2260 2262 "No minimum ECC strength, using 1b/512B\n");
+4 -2
drivers/mtd/nand/raw/mtk_nand.c
··· 1253 1253 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd) 1254 1254 { 1255 1255 struct nand_chip *nand = mtd_to_nand(mtd); 1256 + const struct nand_ecc_props *requirements = 1257 + nanddev_get_ecc_requirements(&nand->base); 1256 1258 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1257 1259 u32 spare; 1258 1260 int free, ret; ··· 1268 1266 /* if optional dt settings not present */ 1269 1267 if (!nand->ecc.size || !nand->ecc.strength) { 1270 1268 /* use datasheet requirements */ 1271 - nand->ecc.strength = nand->base.eccreq.strength; 1272 - nand->ecc.size = nand->base.eccreq.step_size; 1269 + nand->ecc.strength = requirements->strength; 1270 + nand->ecc.size = requirements->step_size; 1273 1271 1274 1272 /* 1275 1273 * align eccstrength and eccsize
+17 -10
drivers/mtd/nand/raw/nand_base.c
··· 4750 4750 static bool find_full_id_nand(struct nand_chip *chip, 4751 4751 struct nand_flash_dev *type) 4752 4752 { 4753 + struct nand_device *base = &chip->base; 4754 + struct nand_ecc_props requirements; 4753 4755 struct mtd_info *mtd = nand_to_mtd(chip); 4754 4756 struct nand_memory_organization *memorg; 4755 4757 u8 *id_data = chip->id.data; ··· 4773 4771 memorg->pagesize * 4774 4772 memorg->pages_per_eraseblock); 4775 4773 chip->options |= type->options; 4776 - chip->base.eccreq.strength = NAND_ECC_STRENGTH(type); 4777 - chip->base.eccreq.step_size = NAND_ECC_STEP(type); 4774 + requirements.strength = NAND_ECC_STRENGTH(type); 4775 + requirements.step_size = NAND_ECC_STEP(type); 4776 + nanddev_set_ecc_requirements(base, &requirements); 4778 4777 4779 4778 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 4780 4779 if (!chip->parameters.model) ··· 5475 5472 nand_match_ecc_req(struct nand_chip *chip, 5476 5473 const struct nand_ecc_caps *caps, int oobavail) 5477 5474 { 5475 + const struct nand_ecc_props *requirements = 5476 + nanddev_get_ecc_requirements(&chip->base); 5478 5477 struct mtd_info *mtd = nand_to_mtd(chip); 5479 5478 const struct nand_ecc_step_info *stepinfo; 5480 - int req_step = chip->base.eccreq.step_size; 5481 - int req_strength = chip->base.eccreq.strength; 5479 + int req_step = requirements->step_size; 5480 + int req_strength = requirements->strength; 5482 5481 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; 5483 5482 int best_step, best_strength, best_ecc_bytes; 5484 5483 int best_ecc_bytes_total = INT_MAX; ··· 5671 5666 { 5672 5667 struct mtd_info *mtd = nand_to_mtd(chip); 5673 5668 struct nand_ecc_ctrl *ecc = &chip->ecc; 5669 + const struct nand_ecc_props *requirements = 5670 + nanddev_get_ecc_requirements(&chip->base); 5674 5671 int corr, ds_corr; 5675 5672 5676 - if (ecc->size == 0 || chip->base.eccreq.step_size == 0) 5673 + if (ecc->size == 0 || requirements->step_size == 0) 5677 5674 /* Not enough information */ 5678 5675 return true; 5679 5676 ··· 5684 5677 * the correction density. 5685 5678 */ 5686 5679 corr = (mtd->writesize * ecc->strength) / ecc->size; 5687 - ds_corr = (mtd->writesize * chip->base.eccreq.strength) / 5688 - chip->base.eccreq.step_size; 5680 + ds_corr = (mtd->writesize * requirements->strength) / 5681 + requirements->step_size; 5689 5682 5690 - return corr >= ds_corr && ecc->strength >= chip->base.eccreq.strength; 5683 + return corr >= ds_corr && ecc->strength >= requirements->strength; 5691 5684 } 5692 5685 5693 5686 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos) ··· 5974 5967 if (!nand_ecc_strength_good(chip)) 5975 5968 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n", 5976 5969 mtd->name, chip->ecc.strength, chip->ecc.size, 5977 - chip->base.eccreq.strength, 5978 - chip->base.eccreq.step_size); 5970 + nanddev_get_ecc_requirements(&chip->base)->strength, 5971 + nanddev_get_ecc_requirements(&chip->base)->step_size); 5979 5972 5980 5973 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 5981 5974 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
+10 -5
drivers/mtd/nand/raw/nand_esmt.c
··· 10 10 11 11 static void esmt_nand_decode_id(struct nand_chip *chip) 12 12 { 13 + struct nand_device *base = &chip->base; 14 + struct nand_ecc_props requirements = {}; 15 + 13 16 nand_decode_ext_id(chip); 14 17 15 18 /* Extract ECC requirements from 5th id byte. */ 16 19 if (chip->id.len >= 5 && nand_is_slc(chip)) { 17 - chip->base.eccreq.step_size = 512; 20 + requirements.step_size = 512; 18 21 switch (chip->id.data[4] & 0x3) { 19 22 case 0x0: 20 - chip->base.eccreq.strength = 4; 23 + requirements.strength = 4; 21 24 break; 22 25 case 0x1: 23 - chip->base.eccreq.strength = 2; 26 + requirements.strength = 2; 24 27 break; 25 28 case 0x2: 26 - chip->base.eccreq.strength = 1; 29 + requirements.strength = 1; 27 30 break; 28 31 default: 29 32 WARN(1, "Could not get ECC info"); 30 - chip->base.eccreq.step_size = 0; 33 + requirements.step_size = 0; 31 34 break; 32 35 } 33 36 } 37 + 38 + nanddev_set_ecc_requirements(base, &requirements); 34 39 } 35 40 36 41 static int esmt_nand_init(struct nand_chip *chip)
+24 -20
drivers/mtd/nand/raw/nand_hynix.c
··· 495 495 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip, 496 496 bool valid_jedecid) 497 497 { 498 + struct nand_device *base = &chip->base; 499 + struct nand_ecc_props requirements = {}; 498 500 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7; 499 501 500 502 if (valid_jedecid) { 501 503 /* Reference: H27UCG8T2E datasheet */ 502 - chip->base.eccreq.step_size = 1024; 504 + requirements.step_size = 1024; 503 505 504 506 switch (ecc_level) { 505 507 case 0: 506 - chip->base.eccreq.step_size = 0; 507 - chip->base.eccreq.strength = 0; 508 + requirements.step_size = 0; 509 + requirements.strength = 0; 508 510 break; 509 511 case 1: 510 - chip->base.eccreq.strength = 4; 512 + requirements.strength = 4; 511 513 break; 512 514 case 2: 513 - chip->base.eccreq.strength = 24; 515 + requirements.strength = 24; 514 516 break; 515 517 case 3: 516 - chip->base.eccreq.strength = 32; 518 + requirements.strength = 32; 517 519 break; 518 520 case 4: 519 - chip->base.eccreq.strength = 40; 521 + requirements.strength = 40; 520 522 break; 521 523 case 5: 522 - chip->base.eccreq.strength = 50; 524 + requirements.strength = 50; 523 525 break; 524 526 case 6: 525 - chip->base.eccreq.strength = 60; 527 + requirements.strength = 60; 526 528 break; 527 529 default: 528 530 /* ··· 545 543 if (nand_tech < 3) { 546 544 /* > 26nm, reference: H27UBG8T2A datasheet */ 547 545 if (ecc_level < 5) { 548 - chip->base.eccreq.step_size = 512; 549 - chip->base.eccreq.strength = 1 << ecc_level; 546 + requirements.step_size = 512; 547 + requirements.strength = 1 << ecc_level; 550 548 } else if (ecc_level < 7) { 551 549 if (ecc_level == 5) 552 - chip->base.eccreq.step_size = 2048; 550 + requirements.step_size = 2048; 553 551 else 554 - chip->base.eccreq.step_size = 1024; 555 - chip->base.eccreq.strength = 24; 552 + requirements.step_size = 1024; 553 + requirements.strength = 24; 556 554 } else { 557 555 /* 558 556 * We should never reach this case, but if that ··· 565 563 } else { 566 564 /* <= 26nm, reference: H27UBG8T2B datasheet */ 567 565 if (!ecc_level) { 568 - chip->base.eccreq.step_size = 0; 569 - chip->base.eccreq.strength = 0; 566 + requirements.step_size = 0; 567 + requirements.strength = 0; 570 568 } else if (ecc_level < 5) { 571 - chip->base.eccreq.step_size = 512; 572 - chip->base.eccreq.strength = 1 << (ecc_level - 1); 569 + requirements.step_size = 512; 570 + requirements.strength = 1 << (ecc_level - 1); 573 571 } else { 574 - chip->base.eccreq.step_size = 1024; 575 - chip->base.eccreq.strength = 24 + 572 + requirements.step_size = 1024; 573 + requirements.strength = 24 + 576 574 (8 * (ecc_level - 5)); 577 575 } 578 576 } 579 577 } 578 + 579 + nanddev_set_ecc_requirements(base, &requirements); 580 580 } 581 581 582 582 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
+7 -2
drivers/mtd/nand/raw/nand_jedec.c
··· 23 23 */ 24 24 int nand_jedec_detect(struct nand_chip *chip) 25 25 { 26 + struct nand_device *base = &chip->base; 26 27 struct mtd_info *mtd = nand_to_mtd(chip); 27 28 struct nand_memory_organization *memorg; 28 29 struct nand_jedec_params *p; ··· 121 120 ecc = &p->ecc_info[0]; 122 121 123 122 if (ecc->codeword_size >= 9) { 124 - chip->base.eccreq.strength = ecc->ecc_bits; 125 - chip->base.eccreq.step_size = 1 << ecc->codeword_size; 123 + struct nand_ecc_props requirements = { 124 + .strength = ecc->ecc_bits, 125 + .step_size = 1 << ecc->codeword_size, 126 + }; 127 + 128 + nanddev_set_ecc_requirements(base, &requirements); 126 129 } else { 127 130 pr_warn("Invalid codeword size\n"); 128 131 }
+11 -6
drivers/mtd/nand/raw/nand_micron.c
··· 413 413 */ 414 414 static int micron_supports_on_die_ecc(struct nand_chip *chip) 415 415 { 416 + const struct nand_ecc_props *requirements = 417 + nanddev_get_ecc_requirements(&chip->base); 416 418 u8 id[5]; 417 419 int ret; 418 420 ··· 427 425 /* 428 426 * We only support on-die ECC of 4/512 or 8/512 429 427 */ 430 - if (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8) 428 + if (requirements->strength != 4 && requirements->strength != 8) 431 429 return MICRON_ON_DIE_UNSUPPORTED; 432 430 433 431 /* 0x2 means on-die ECC is available. */ ··· 468 466 /* 469 467 * We only support on-die ECC of 4/512 or 8/512 470 468 */ 471 - if (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8) 469 + if (requirements->strength != 4 && requirements->strength != 8) 472 470 return MICRON_ON_DIE_UNSUPPORTED; 473 471 474 472 return MICRON_ON_DIE_SUPPORTED; ··· 476 474 477 475 static int micron_nand_init(struct nand_chip *chip) 478 476 { 477 + struct nand_device *base = &chip->base; 478 + const struct nand_ecc_props *requirements = 479 + nanddev_get_ecc_requirements(base); 479 480 struct mtd_info *mtd = nand_to_mtd(chip); 480 481 struct micron_nand *micron; 481 482 int ondie; ··· 528 523 * That's not needed for 8-bit ECC, because the status expose 529 524 * a better approximation of the number of bitflips in a page. 530 525 */ 531 - if (chip->base.eccreq.strength == 4) { 526 + if (requirements->strength == 4) { 532 527 micron->ecc.rawbuf = kmalloc(mtd->writesize + 533 528 mtd->oobsize, 534 529 GFP_KERNEL); ··· 538 533 } 539 534 } 540 535 541 - if (chip->base.eccreq.strength == 4) 536 + if (requirements->strength == 4) 542 537 mtd_set_ooblayout(mtd, 543 538 &micron_nand_on_die_4_ooblayout_ops); 544 539 else 545 540 mtd_set_ooblayout(mtd, 546 541 &micron_nand_on_die_8_ooblayout_ops); 547 542 548 - chip->ecc.bytes = chip->base.eccreq.strength * 2; 543 + chip->ecc.bytes = requirements->strength * 2; 549 544 chip->ecc.size = 512; 550 - chip->ecc.strength = chip->base.eccreq.strength; 545 + chip->ecc.strength = requirements->strength; 551 546 chip->ecc.algo = NAND_ECC_ALGO_BCH; 552 547 chip->ecc.read_page = micron_nand_read_page_on_die_ecc; 553 548 chip->ecc.write_page = micron_nand_write_page_on_die_ecc;
+13 -4
drivers/mtd/nand/raw/nand_onfi.c
··· 34 34 static int nand_flash_detect_ext_param_page(struct nand_chip *chip, 35 35 struct nand_onfi_params *p) 36 36 { 37 + struct nand_device *base = &chip->base; 38 + struct nand_ecc_props requirements; 37 39 struct onfi_ext_param_page *ep; 38 40 struct onfi_ext_section *s; 39 41 struct onfi_ext_ecc_info *ecc; ··· 96 94 goto ext_out; 97 95 } 98 96 99 - chip->base.eccreq.strength = ecc->ecc_bits; 100 - chip->base.eccreq.step_size = 1 << ecc->codeword_size; 97 + requirements.strength = ecc->ecc_bits; 98 + requirements.step_size = 1 << ecc->codeword_size; 99 + nanddev_set_ecc_requirements(base, &requirements); 100 + 101 101 ret = 0; 102 102 103 103 ext_out: ··· 143 139 */ 144 140 int nand_onfi_detect(struct nand_chip *chip) 145 141 { 142 + struct nand_device *base = &chip->base; 146 143 struct mtd_info *mtd = nand_to_mtd(chip); 147 144 struct nand_memory_organization *memorg; 148 145 struct nand_onfi_params *p = NULL, *pbuf; ··· 270 265 chip->options |= NAND_BUSWIDTH_16; 271 266 272 267 if (p->ecc_bits != 0xff) { 273 - chip->base.eccreq.strength = p->ecc_bits; 274 - chip->base.eccreq.step_size = 512; 268 + struct nand_ecc_props requirements = { 269 + .strength = p->ecc_bits, 270 + .step_size = 512, 271 + }; 272 + 273 + nanddev_set_ecc_requirements(base, &requirements); 275 274 } else if (onfi_version >= 21 && 276 275 (le16_to_cpu(p->features) & ONFI_FEATURE_EXT_PARAM_PAGE)) { 277 276
+13 -9
drivers/mtd/nand/raw/nand_samsung.c
··· 10 10 11 11 static void samsung_nand_decode_id(struct nand_chip *chip) 12 12 { 13 + struct nand_device *base = &chip->base; 14 + struct nand_ecc_props requirements = {}; 13 15 struct mtd_info *mtd = nand_to_mtd(chip); 14 16 struct nand_memory_organization *memorg; 15 17 ··· 73 71 /* Extract ECC requirements from 5th id byte*/ 74 72 extid = (chip->id.data[4] >> 4) & 0x07; 75 73 if (extid < 5) { 76 - chip->base.eccreq.step_size = 512; 77 - chip->base.eccreq.strength = 1 << extid; 74 + requirements.step_size = 512; 75 + requirements.strength = 1 << extid; 78 76 } else { 79 - chip->base.eccreq.step_size = 1024; 77 + requirements.step_size = 1024; 80 78 switch (extid) { 81 79 case 5: 82 - chip->base.eccreq.strength = 24; 80 + requirements.strength = 24; 83 81 break; 84 82 case 6: 85 - chip->base.eccreq.strength = 40; 83 + requirements.strength = 40; 86 84 break; 87 85 case 7: 88 - chip->base.eccreq.strength = 60; 86 + requirements.strength = 60; 89 87 break; 90 88 default: 91 89 WARN(1, "Could not decode ECC info"); 92 - chip->base.eccreq.step_size = 0; 90 + requirements.step_size = 0; 93 91 } 94 92 } 95 93 } else { ··· 99 97 switch (chip->id.data[1]) { 100 98 /* K9F4G08U0D-S[I|C]B0(T00) */ 101 99 case 0xDC: 102 - chip->base.eccreq.step_size = 512; 103 - chip->base.eccreq.strength = 1; 100 + requirements.step_size = 512; 101 + requirements.strength = 1; 104 102 break; 105 103 106 104 /* K9F1G08U0E 21nm chips do not support subpage write */ ··· 114 112 } 115 113 } 116 114 } 115 + 116 + nanddev_set_ecc_requirements(base, &requirements); 117 117 } 118 118 119 119 static int samsung_nand_init(struct nand_chip *chip)
+9 -5
drivers/mtd/nand/raw/nand_toshiba.c
··· 145 145 146 146 static void toshiba_nand_decode_id(struct nand_chip *chip) 147 147 { 148 + struct nand_device *base = &chip->base; 149 + struct nand_ecc_props requirements = {}; 148 150 struct mtd_info *mtd = nand_to_mtd(chip); 149 151 struct nand_memory_organization *memorg; 150 152 ··· 177 175 * - 24nm: 8 bit ECC for each 512Byte is required. 178 176 */ 179 177 if (chip->id.len >= 6 && nand_is_slc(chip)) { 180 - chip->base.eccreq.step_size = 512; 178 + requirements.step_size = 512; 181 179 switch (chip->id.data[5] & 0x7) { 182 180 case 0x4: 183 - chip->base.eccreq.strength = 1; 181 + requirements.strength = 1; 184 182 break; 185 183 case 0x5: 186 - chip->base.eccreq.strength = 4; 184 + requirements.strength = 4; 187 185 break; 188 186 case 0x6: 189 - chip->base.eccreq.strength = 8; 187 + requirements.strength = 8; 190 188 break; 191 189 default: 192 190 WARN(1, "Could not get ECC info"); 193 - chip->base.eccreq.step_size = 0; 191 + requirements.step_size = 0; 194 192 break; 195 193 } 196 194 } 195 + 196 + nanddev_set_ecc_requirements(base, &requirements); 197 197 } 198 198 199 199 static int
+4 -2
drivers/mtd/nand/raw/sunxi_nand.c
··· 1732 1732 1733 1733 static int sunxi_nand_attach_chip(struct nand_chip *nand) 1734 1734 { 1735 + const struct nand_ecc_props *requirements = 1736 + nanddev_get_ecc_requirements(&nand->base); 1735 1737 struct nand_ecc_ctrl *ecc = &nand->ecc; 1736 1738 struct device_node *np = nand_get_flash_node(nand); 1737 1739 int ret; ··· 1747 1745 nand->options |= NAND_SUBPAGE_READ; 1748 1746 1749 1747 if (!ecc->size) { 1750 - ecc->size = nand->base.eccreq.step_size; 1751 - ecc->strength = nand->base.eccreq.strength; 1748 + ecc->size = requirements->step_size; 1749 + ecc->strength = requirements->strength; 1752 1750 } 1753 1751 1754 1752 if (!ecc->size || !ecc->strength)
+8 -4
drivers/mtd/nand/raw/tegra_nand.c
··· 840 840 int strength_len, int bits_per_step, 841 841 int oobsize) 842 842 { 843 + const struct nand_ecc_props *requirements = 844 + nanddev_get_ecc_requirements(&chip->base); 843 845 bool maximize = chip->ecc.options & NAND_ECC_MAXIMIZE; 844 846 int i; 845 847 ··· 857 855 } else { 858 856 strength_sel = strength[i]; 859 857 860 - if (strength_sel < chip->base.eccreq.strength) 858 + if (strength_sel < requirements->strength) 861 859 continue; 862 860 } 863 861 ··· 910 908 static int tegra_nand_attach_chip(struct nand_chip *chip) 911 909 { 912 910 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); 911 + const struct nand_ecc_props *requirements = 912 + nanddev_get_ecc_requirements(&chip->base); 913 913 struct tegra_nand_chip *nand = to_tegra_chip(chip); 914 914 struct mtd_info *mtd = nand_to_mtd(chip); 915 915 int bits_per_step; ··· 923 919 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 924 920 chip->ecc.size = 512; 925 921 chip->ecc.steps = mtd->writesize / chip->ecc.size; 926 - if (chip->base.eccreq.step_size != 512) { 922 + if (requirements->step_size != 512) { 927 923 dev_err(ctrl->dev, "Unsupported step size %d\n", 928 - chip->base.eccreq.step_size); 924 + requirements->step_size); 929 925 return -EINVAL; 930 926 } 931 927 ··· 956 952 if (ret < 0) { 957 953 dev_err(ctrl->dev, 958 954 "No valid strength found, minimum %d\n", 959 - chip->base.eccreq.strength); 955 + requirements->strength); 960 956 return ret; 961 957 } 962 958
+1 -1
drivers/mtd/nand/spi/core.c
··· 902 902 continue; 903 903 904 904 nand->memorg = table[i].memorg; 905 - nand->eccreq = table[i].eccreq; 905 + nanddev_set_ecc_requirements(nand, &table[i].eccreq); 906 906 spinand->eccinfo = table[i].eccinfo; 907 907 spinand->flags = table[i].flags; 908 908 spinand->id.len = 1 + table[i].devid.len;