tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'asoc-v6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
ASoC: Additional v6.16 updates
A couple more updates on top of the last set I sent you, a new driver
for the ES8375 and a fix for the Cirrus KUnit tests from Jaroslav.
+996
-1
+71
Documentation/devicetree/bindings/sound/everest,es8375.yaml
+71
Documentation/devicetree/bindings/sound/everest,es8375.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/sound/everest,es8375.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Everest ES8375 audio CODEC
8
+
9
+
maintainers:
10
+
- Michael Zhang <zhangyi@everest-semi.com>
11
+
12
+
allOf:
13
+
- $ref: dai-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: everest,es8375
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
clocks:
23
+
items:
24
+
- description: clock for master clock (MCLK)
25
+
26
+
clock-names:
27
+
items:
28
+
- const: mclk
29
+
30
+
vdda-supply:
31
+
description:
32
+
Analogue power supply.
33
+
34
+
vddd-supply:
35
+
description:
36
+
Interface power supply.
37
+
38
+
everest,mclk-src:
39
+
$ref: /schemas/types.yaml#/definitions/uint8
40
+
description: |
41
+
Represents the MCLK/SCLK pair pins used as the internal clock.
42
+
0 represents selecting MCLK.
43
+
1 represents selecting SCLK.
44
+
enum: [0, 1]
45
+
default: 0
46
+
47
+
"#sound-dai-cells":
48
+
const: 0
49
+
50
+
required:
51
+
- compatible
52
+
- reg
53
+
- "#sound-dai-cells"
54
+
- vdda-supply
55
+
- vddd-supply
56
+
57
+
additionalProperties: false
58
+
59
+
examples:
60
+
- |
61
+
i2c {
62
+
#address-cells = <1>;
63
+
#size-cells = <0>;
64
+
es8375: codec@18 {
65
+
compatible = "everest,es8375";
66
+
reg = <0x18>;
67
+
vdda-supply = <&vdd3v3>;
68
+
vddd-supply = <&vdd3v3>;
69
+
#sound-dai-cells = <0>;
70
+
};
71
+
};
+2
-1
drivers/firmware/cirrus/test/cs_dsp_mock_bin.c
+2
-1
drivers/firmware/cirrus/test/cs_dsp_mock_bin.c
···
96
96
97
97
if (info_len % 4) {
98
98
/* Create a padded string with length a multiple of 4 */
99
+
size_t copy_len = info_len;
99
100
info_len = round_up(info_len, 4);
100
101
tmp = kunit_kzalloc(builder->test_priv->test, info_len, GFP_KERNEL);
101
102
KUNIT_ASSERT_NOT_ERR_OR_NULL(builder->test_priv->test, tmp);
102
-
memcpy(tmp, info, info_len);
103
+
memcpy(tmp, info, copy_len);
103
104
info = tmp;
104
105
}
105
106
+5
sound/soc/codecs/Kconfig
+5
sound/soc/codecs/Kconfig
···
120
120
imply SND_SOC_ES8326
121
121
imply SND_SOC_ES8328_SPI
122
122
imply SND_SOC_ES8328_I2C
123
+
imply SND_SOC_ES8375
123
124
imply SND_SOC_ES8389
124
125
imply SND_SOC_ES7134
125
126
imply SND_SOC_ES7241
···
1212
1211
tristate "Everest Semi ES8328 CODEC (SPI)"
1213
1212
depends on SPI_MASTER
1214
1213
select SND_SOC_ES8328
1214
+
1215
+
config SND_SOC_ES8375
1216
+
tristate "Everest Semi ES8375 CODEC"
1217
+
depends on I2C
1215
1218
1216
1219
config SND_SOC_ES8389
1217
1220
tristate "Everest Semi ES8389 CODEC"
+2
sound/soc/codecs/Makefile
+2
sound/soc/codecs/Makefile
···
134
134
snd-soc-es8328-y := es8328.o
135
135
snd-soc-es8328-i2c-y := es8328-i2c.o
136
136
snd-soc-es8328-spi-y := es8328-spi.o
137
+
snd-soc-es8375-y := es8375.o
137
138
snd-soc-es8389-y := es8389.o
138
139
snd-soc-framer-y := framer-codec.o
139
140
snd-soc-gtm601-y := gtm601.o
···
558
557
obj-$(CONFIG_SND_SOC_ES8328) += snd-soc-es8328.o
559
558
obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
560
559
obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
560
+
obj-$(CONFIG_SND_SOC_ES8375) += snd-soc-es8375.o
561
561
obj-$(CONFIG_SND_SOC_ES8389) += snd-soc-es8389.o
562
562
obj-$(CONFIG_SND_SOC_FRAMER) += snd-soc-framer.o
563
563
obj-$(CONFIG_SND_SOC_GTM601) += snd-soc-gtm601.o
+793
sound/soc/codecs/es8375.c
+793
sound/soc/codecs/es8375.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* es8375.c -- ES8375 ALSA SoC Audio Codec
4
+
*
5
+
* Copyright Everest Semiconductor Co., Ltd
6
+
*
7
+
* Authors: Michael Zhang (zhangyi@everest-semi.com)
8
+
*/
9
+
10
+
#include <linux/gpio/consumer.h>
11
+
#include <linux/clk.h>
12
+
#include <linux/module.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/delay.h>
15
+
#include <linux/i2c.h>
16
+
#include <linux/regmap.h>
17
+
#include <linux/regulator/consumer.h>
18
+
#include <sound/core.h>
19
+
#include <sound/pcm.h>
20
+
#include <sound/pcm_params.h>
21
+
#include <sound/tlv.h>
22
+
#include <sound/soc.h>
23
+
#include <linux/acpi.h>
24
+
#include "es8375.h"
25
+
26
+
struct es8375_priv {
27
+
struct regmap *regmap;
28
+
struct clk *mclk;
29
+
struct regulator_bulk_data core_supply[2];
30
+
unsigned int mclk_freq;
31
+
int mastermode;
32
+
u8 mclk_src;
33
+
u8 vddd;
34
+
enum snd_soc_bias_level bias_level;
35
+
};
36
+
37
+
static const char * const es8375_core_supplies[] = {
38
+
"vddd",
39
+
"vdda",
40
+
};
41
+
42
+
static const DECLARE_TLV_DB_SCALE(es8375_adc_osr_gain_tlv, -3100, 100, 0);
43
+
static const DECLARE_TLV_DB_SCALE(es8375_adc_volume_tlv, -9550, 50, 0);
44
+
static const DECLARE_TLV_DB_SCALE(es8375_adc_automute_attn_tlv, 0, 100, 0);
45
+
static const DECLARE_TLV_DB_SCALE(es8375_adc_dmic_volume_tlv, 0, 600, 0);
46
+
static const DECLARE_TLV_DB_SCALE(es8375_dac_volume_tlv, -9550, 50, 0);
47
+
static const DECLARE_TLV_DB_SCALE(es8375_dac_vppscale_tlv, -388, 12, 0);
48
+
static const DECLARE_TLV_DB_SCALE(es8375_dac_automute_attn_tlv, 0, 400, 0);
49
+
static const DECLARE_TLV_DB_SCALE(es8375_automute_ng_tlv, -9600, 600, 0);
50
+
51
+
static const char *const es8375_ramprate_txt[] = {
52
+
"0.125dB/LRCK",
53
+
"0.125dB/2LRCK",
54
+
"0.125dB/4LRCK",
55
+
"0.125dB/8LRCK",
56
+
"0.125dB/16LRCK",
57
+
"0.125dB/32LRCK",
58
+
"0.125dB/64LRCK",
59
+
"0.125dB/128LRCK",
60
+
"disable softramp",
61
+
};
62
+
static SOC_ENUM_SINGLE_DECL(es8375_adc_ramprate, ES8375_ADC2,
63
+
ADC_RAMPRATE_SHIFT_0, es8375_ramprate_txt);
64
+
static SOC_ENUM_SINGLE_DECL(es8375_dac_ramprate, ES8375_DAC2,
65
+
DAC_RAMPRATE_SHIFT_0, es8375_ramprate_txt);
66
+
67
+
static const char *const es8375_automute_ws_txt[] = {
68
+
"256 samples",
69
+
"512 samples",
70
+
"1024 samples",
71
+
"2048 samples",
72
+
"4096 samples",
73
+
"8192 samples",
74
+
"16384 samples",
75
+
"32768 samples",
76
+
};
77
+
static SOC_ENUM_SINGLE_DECL(es8375_adc_automute_ws, ES8375_ADC_AUTOMUTE,
78
+
ADC_AUTOMUTE_WS_SHIFT_3, es8375_automute_ws_txt);
79
+
static SOC_ENUM_SINGLE_DECL(es8375_dac_automute_ws, ES8375_DAC_AUTOMUTE,
80
+
DAC_AUTOMUTE_WS_SHIFT_5, es8375_automute_ws_txt);
81
+
82
+
static const char *const es8375_dmic_pol_txt[] = {
83
+
"Low",
84
+
"High",
85
+
};
86
+
87
+
static SOC_ENUM_SINGLE_DECL(es8375_dmic_pol, ES8375_ADC1,
88
+
DMIC_POL_SHIFT_4, es8375_dmic_pol_txt);
89
+
90
+
static const char *const es8375_adc_hpf_txt[] = {
91
+
"Freeze Offset",
92
+
"Dynamic HPF",
93
+
};
94
+
95
+
static SOC_ENUM_SINGLE_DECL(es8375_adc_hpf, ES8375_HPF1,
96
+
ADC_HPF_SHIFT_5, es8375_adc_hpf_txt);
97
+
98
+
static const char *const es8375_dmic_mux_txt[] = {
99
+
"AMIC",
100
+
"DMIC",
101
+
};
102
+
static const struct soc_enum es8375_dmic_mux_enum =
103
+
SOC_ENUM_SINGLE(ES8375_ADC1, ADC_SRC_SHIFT_7,
104
+
ARRAY_SIZE(es8375_dmic_mux_txt), es8375_dmic_mux_txt);
105
+
106
+
static const struct snd_kcontrol_new es8375_dmic_mux_controls =
107
+
SOC_DAPM_ENUM("ADC MUX", es8375_dmic_mux_enum);
108
+
109
+
static const struct snd_kcontrol_new es8375_snd_controls[] = {
110
+
SOC_SINGLE_TLV("ADC OSR Volume", ES8375_ADC_OSR_GAIN,
111
+
ADC_OSR_GAIN_SHIFT_0, ES8375_ADC_OSR_GAIN_MAX, 0,
112
+
es8375_adc_osr_gain_tlv),
113
+
SOC_SINGLE("ADC Invert Switch", ES8375_ADC1, ADC_INV_SHIFT_6, 1, 0),
114
+
SOC_SINGLE("ADC RAM Clear", ES8375_ADC1, ADC_RAMCLR_SHIFT_5, 1, 0),
115
+
SOC_ENUM("DMIC Polarity", es8375_dmic_pol),
116
+
SOC_SINGLE_TLV("DMIC Volume", ES8375_ADC1,
117
+
DMIC_GAIN_SHIFT_2, ES8375_DMIC_GAIN_MAX,
118
+
0, es8375_adc_dmic_volume_tlv),
119
+
SOC_ENUM("ADC Ramp Rate", es8375_adc_ramprate),
120
+
SOC_SINGLE_TLV("ADC Volume", ES8375_ADC_VOLUME,
121
+
ADC_VOLUME_SHIFT_0, ES8375_ADC_VOLUME_MAX,
122
+
0, es8375_adc_volume_tlv),
123
+
SOC_SINGLE("ADC Automute Switch", ES8375_ADC_AUTOMUTE,
124
+
ADC_AUTOMUTE_SHIFT_7, 1, 0),
125
+
SOC_ENUM("ADC Automute Winsize", es8375_adc_automute_ws),
126
+
SOC_SINGLE_TLV("ADC Automute Noise Gate", ES8375_ADC_AUTOMUTE,
127
+
ADC_AUTOMUTE_NG_SHIFT_0, ES8375_AUTOMUTE_NG_MAX,
128
+
0, es8375_automute_ng_tlv),
129
+
SOC_SINGLE_TLV("ADC Automute Volume", ES8375_ADC_AUTOMUTE_ATTN,
130
+
ADC_AUTOMUTE_ATTN_SHIFT_0, ES8375_ADC_AUTOMUTE_ATTN_MAX,
131
+
0, es8375_adc_automute_attn_tlv),
132
+
SOC_ENUM("ADC HPF", es8375_adc_hpf),
133
+
134
+
SOC_SINGLE("DAC DSM Mute Switch", ES8375_DAC1, DAC_DSMMUTE_SHIFT_7, 1, 0),
135
+
SOC_SINGLE("DAC DEM Mute Switch", ES8375_DAC1, DAC_DEMMUTE_SHIFT_6, 1, 0),
136
+
SOC_SINGLE("DAC Invert Switch", ES8375_DAC1, DAC_INV_SHIFT_5, 1, 0),
137
+
SOC_SINGLE("DAC RAM Clear", ES8375_DAC1, DAC_RAMCLR_SHIFT_4, 1, 0),
138
+
SOC_ENUM("DAC Ramp Rate", es8375_dac_ramprate),
139
+
SOC_SINGLE_TLV("DAC Volume", ES8375_DAC_VOLUME,
140
+
DAC_VOLUME_SHIFT_0, ES8375_DAC_VOLUME_MAX,
141
+
0, es8375_dac_volume_tlv),
142
+
SOC_SINGLE_TLV("DAC VPP Scale", ES8375_DAC_VPPSCALE,
143
+
DAC_VPPSCALE_SHIFT_0, ES8375_DAC_VPPSCALE_MAX,
144
+
0, es8375_dac_vppscale_tlv),
145
+
SOC_SINGLE("DAC Automute Switch", ES8375_DAC_AUTOMUTE1,
146
+
DAC_AUTOMUTE_EN_SHIFT_7, 1, 0),
147
+
SOC_SINGLE_TLV("DAC Automute Noise Gate", ES8375_DAC_AUTOMUTE1,
148
+
DAC_AUTOMUTE_NG_SHIFT_0, ES8375_AUTOMUTE_NG_MAX,
149
+
0, es8375_automute_ng_tlv),
150
+
SOC_ENUM("DAC Automute Winsize", es8375_dac_automute_ws),
151
+
SOC_SINGLE_TLV("DAC Automute Volume", ES8375_DAC_AUTOMUTE,
152
+
DAC_AUTOMUTE_ATTN_SHIFT_0, ES8375_DAC_AUTOMUTE_ATTN_MAX,
153
+
0, es8375_dac_automute_attn_tlv),
154
+
};
155
+
156
+
static const struct snd_soc_dapm_widget es8375_dapm_widgets[] = {
157
+
SND_SOC_DAPM_INPUT("MIC1"),
158
+
SND_SOC_DAPM_INPUT("DMIC"),
159
+
SND_SOC_DAPM_PGA("PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
160
+
SND_SOC_DAPM_ADC("Mono ADC", NULL, SND_SOC_NOPM, 0, 0),
161
+
SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, ES8375_SDP2,
162
+
ES8375_ADC_P2S_MUTE_SHIFT_5, 1),
163
+
164
+
SND_SOC_DAPM_MUX("ADC MUX", SND_SOC_NOPM, 0, 0, &es8375_dmic_mux_controls),
165
+
166
+
SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, ES8375_SDP,
167
+
SND_SOC_NOPM, 0),
168
+
SND_SOC_DAPM_DAC("Mono DAC", NULL, SND_SOC_NOPM, 0, 0),
169
+
SND_SOC_DAPM_OUTPUT("OUT"),
170
+
};
171
+
172
+
static const struct snd_soc_dapm_route es8375_dapm_routes[] = {
173
+
{"ADC MUX", "AMIC", "MIC1"},
174
+
{"ADC MUX", "DMIC", "DMIC"},
175
+
{"PGA", NULL, "ADC MUX"},
176
+
{"Mono ADC", NULL, "PGA"},
177
+
{"AIF1TX", NULL, "Mono ADC"},
178
+
179
+
{"Mono DAC", NULL, "AIF1RX"},
180
+
{"OUT", NULL, "Mono DAC"},
181
+
};
182
+
183
+
struct _coeff_div {
184
+
u16 mclk_lrck_ratio;
185
+
u32 mclk;
186
+
u32 rate;
187
+
u8 Reg0x04;
188
+
u8 Reg0x05;
189
+
u8 Reg0x06;
190
+
u8 Reg0x07;
191
+
u8 Reg0x08;
192
+
u8 Reg0x09;
193
+
u8 Reg0x0A;
194
+
u8 Reg0x0B;
195
+
u8 Reg0x19;
196
+
u8 dvdd_vol;
197
+
u8 dmic_sel;
198
+
};
199
+
200
+
static const struct _coeff_div coeff_div[] = {
201
+
{32, 256000, 8000, 0x05, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x95, 0x00, 0x1F, 2, 2},
202
+
{32, 512000, 16000, 0x05, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x94, 0x00, 0x1F, 2, 2},
203
+
{32, 1536000, 48000, 0x05, 0x33, 0xD5, 0x55, 0x1F, 0x00, 0x93, 0x00, 0x1F, 2, 2},
204
+
{36, 288000, 8000, 0x05, 0x34, 0xDD, 0x55, 0x23, 0x08, 0x95, 0x00, 0x1F, 2, 2},
205
+
{36, 576000, 16000, 0x05, 0x34, 0xDD, 0x55, 0x23, 0x08, 0x94, 0x00, 0x1F, 2, 2},
206
+
{36, 1728000, 48000, 0x05, 0x33, 0xD5, 0x55, 0x23, 0x08, 0x93, 0x00, 0x1F, 2, 2},
207
+
{48, 384000, 8000, 0x05, 0x14, 0x5D, 0x55, 0x17, 0x20, 0x94, 0x00, 0x28, 2, 2},
208
+
{48, 768000, 16000, 0x05, 0x14, 0x5D, 0x55, 0x17, 0x20, 0x94, 0x00, 0x28, 2, 2},
209
+
{48, 2304000, 48000, 0x05, 0x11, 0x53, 0x55, 0x17, 0x20, 0x92, 0x00, 0x28, 2, 2},
210
+
{50, 400000, 8000, 0x05, 0x14, 0x5D, 0x55, 0x18, 0x24, 0x94, 0x00, 0x27, 2, 2},
211
+
{50, 800000, 16000, 0x05, 0x14, 0x5D, 0x55, 0x18, 0x24, 0x94, 0x00, 0x27, 2, 2},
212
+
{50, 2400000, 48000, 0x05, 0x11, 0x53, 0x55, 0x18, 0x24, 0x92, 0x00, 0x27, 2, 2},
213
+
{64, 512000, 8000, 0x05, 0x14, 0x5D, 0x33, 0x1F, 0x00, 0x94, 0x00, 0x1F, 2, 2},
214
+
{64, 1024000, 16000, 0x05, 0x13, 0x55, 0x33, 0x1F, 0x00, 0x93, 0x00, 0x1F, 2, 2},
215
+
{64, 3072000, 48000, 0x05, 0x11, 0x53, 0x33, 0x1F, 0x00, 0x92, 0x00, 0x1F, 2, 2},
216
+
{72, 576000, 8000, 0x05, 0x14, 0x5D, 0x33, 0x23, 0x08, 0x94, 0x00, 0x1F, 2, 2},
217
+
{72, 1152000, 16000, 0x05, 0x13, 0x55, 0x33, 0x23, 0x08, 0x93, 0x00, 0x1F, 2, 2},
218
+
{72, 3456000, 48000, 0x05, 0x11, 0x53, 0x33, 0x23, 0x08, 0x92, 0x00, 0x1F, 2, 2},
219
+
{96, 768000, 8000, 0x15, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x94, 0x00, 0x1F, 2, 2},
220
+
{96, 1536000, 16000, 0x15, 0x34, 0xDD, 0x55, 0x1F, 0x00, 0x93, 0x00, 0x1F, 2, 2},
221
+
{96, 4608000, 48000, 0x15, 0x33, 0xD5, 0x55, 0x1F, 0x00, 0x92, 0x00, 0x1F, 2, 2},
222
+
{100, 800000, 8000, 0x05, 0x03, 0x35, 0x33, 0x18, 0x24, 0x94, 0x00, 0x27, 2, 2},
223
+
{100, 1600000, 16000, 0x05, 0x03, 0x35, 0x33, 0x18, 0x24, 0x93, 0x00, 0x27, 2, 2},
224
+
{100, 4800000, 48000, 0x03, 0x00, 0x31, 0x33, 0x18, 0x24, 0x92, 0x00, 0x27, 2, 2},
225
+
{128, 1024000, 8000, 0x05, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x93, 0x01, 0x1F, 2, 2},
226
+
{128, 2048000, 16000, 0x03, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x01, 0x1F, 2, 2},
227
+
{128, 6144000, 48000, 0x03, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x01, 0x1F, 2, 2},
228
+
{144, 1152000, 8000, 0x05, 0x03, 0x35, 0x11, 0x23, 0x08, 0x93, 0x01, 0x1F, 2, 2},
229
+
{144, 2304000, 16000, 0x03, 0x01, 0x33, 0x11, 0x23, 0x08, 0x92, 0x01, 0x1F, 2, 2},
230
+
{144, 6912000, 48000, 0x03, 0x00, 0x31, 0x11, 0x23, 0x08, 0x92, 0x01, 0x1F, 2, 2},
231
+
{192, 1536000, 8000, 0x15, 0x14, 0x5D, 0x33, 0x1F, 0x00, 0x93, 0x02, 0x1F, 2, 2},
232
+
{192, 3072000, 16000, 0x15, 0x13, 0x55, 0x33, 0x1F, 0x00, 0x92, 0x02, 0x1F, 2, 2},
233
+
{192, 9216000, 48000, 0x15, 0x11, 0x53, 0x33, 0x1F, 0x00, 0x92, 0x02, 0x1F, 2, 2},
234
+
{250, 12000000, 48000, 0x25, 0x11, 0x53, 0x55, 0x18, 0x24, 0x92, 0x04, 0x27, 2, 2},
235
+
{256, 2048000, 8000, 0x0D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x03, 0x1F, 2, 2},
236
+
{256, 4096000, 16000, 0x0B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x03, 0x1F, 2, 2},
237
+
{256, 12288000, 48000, 0x0B, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x03, 0x1F, 2, 2},
238
+
{384, 3072000, 8000, 0x15, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x05, 0x1F, 2, 2},
239
+
{384, 6144000, 16000, 0x13, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x05, 0x1F, 2, 2},
240
+
{384, 18432000, 48000, 0x13, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x05, 0x1F, 2, 2},
241
+
{400, 19200000, 48000, 0x1B, 0x00, 0x31, 0x33, 0x18, 0x24, 0x92, 0x04, 0x27, 2, 2},
242
+
{500, 24000000, 48000, 0x23, 0x00, 0x31, 0x33, 0x18, 0x24, 0x92, 0x04, 0x27, 2, 2},
243
+
{512, 4096000, 8000, 0x1D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x07, 0x1F, 2, 2},
244
+
{512, 8192000, 16000, 0x1B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x07, 0x1F, 2, 2},
245
+
{512, 24576000, 48000, 0x1B, 0x00, 0x31, 0x11, 0x1F, 0x00, 0x92, 0x07, 0x1F, 2, 2},
246
+
{768, 6144000, 8000, 0x2D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x0B, 0x1F, 2, 2},
247
+
{768, 12288000, 16000, 0x2B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x0B, 0x1F, 2, 2},
248
+
{1024, 8192000, 8000, 0x3D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
249
+
{1024, 16384000, 16000, 0x3B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
250
+
{1152, 9216000, 8000, 0x45, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
251
+
{1152, 18432000, 16000, 0x43, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x0F, 0x1F, 2, 2},
252
+
{1200, 9600000, 8000, 0x5D, 0x03, 0x35, 0x33, 0x18, 0x24, 0x92, 0x11, 0x27, 2, 2},
253
+
{1200, 19200000, 16000, 0x5D, 0x03, 0x35, 0x33, 0x18, 0x24, 0x92, 0x11, 0x27, 2, 2},
254
+
{1536, 12288000, 8000, 0x5D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x17, 0x1F, 2, 2},
255
+
{1536, 24576000, 16000, 0x5B, 0x01, 0x33, 0x11, 0x1F, 0x00, 0x92, 0x17, 0x1F, 2, 2},
256
+
{2048, 16384000, 8000, 0x7D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x1F, 0x1F, 2, 2},
257
+
{2304, 18432000, 8000, 0x8D, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x23, 0x1F, 2, 2},
258
+
{2400, 19200000, 8000, 0xBD, 0x03, 0x35, 0x33, 0x18, 0x24, 0x92, 0x25, 0x27, 2, 2},
259
+
{3072, 24576000, 8000, 0xBD, 0x03, 0x35, 0x11, 0x1F, 0x00, 0x92, 0x2F, 0x1F, 2, 2},
260
+
{32, 3072000, 96000, 0x05, 0x11, 0x53, 0x55, 0x0F, 0x00, 0x92, 0x00, 0x37, 2, 2},
261
+
{64, 6144000, 96000, 0x03, 0x00, 0x31, 0x33, 0x0F, 0x00, 0x92, 0x00, 0x37, 2, 2},
262
+
{96, 9216000, 96000, 0x15, 0x11, 0x53, 0x55, 0x0F, 0x00, 0x92, 0x00, 0x37, 2, 2},
263
+
{128, 12288000, 96000, 0x0B, 0x00, 0x31, 0x33, 0x0F, 0x00, 0x92, 0x01, 0x37, 2, 2},
264
+
};
265
+
266
+
static inline int get_coeff(u8 vddd, u8 dmic, int mclk, int rate)
267
+
{
268
+
int i;
269
+
u8 dmic_det, vddd_det;
270
+
271
+
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
272
+
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) {
273
+
vddd_det = ~(coeff_div[i].dvdd_vol ^ vddd) & 0x01;
274
+
dmic_det = ~(coeff_div[i].dmic_sel ^ dmic) & 0x01;
275
+
vddd_det |= ~(coeff_div[i].dvdd_vol % 2) & 0x01;
276
+
dmic_det |= ~(coeff_div[i].dmic_sel % 2) & 0x01;
277
+
278
+
if (vddd_det && dmic_det)
279
+
return i;
280
+
}
281
+
}
282
+
283
+
return -EINVAL;
284
+
}
285
+
286
+
static int es8375_hw_params(struct snd_pcm_substream *substream,
287
+
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
288
+
{
289
+
struct snd_soc_component *component = dai->component;
290
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
291
+
int par_width = params_width(params);
292
+
u8 dmic_enable, iface = 0;
293
+
unsigned int regv;
294
+
int coeff, ret;
295
+
296
+
if (es8375->mclk_src == ES8375_BCLK_PIN) {
297
+
regmap_update_bits(es8375->regmap,
298
+
ES8375_MCLK_SEL, 0x80, 0x80);
299
+
300
+
es8375->mclk_freq = 2 * (unsigned int)par_width * params_rate(params);
301
+
}
302
+
303
+
regmap_read(es8375->regmap, ES8375_ADC1, ®v);
304
+
dmic_enable = regv >> 7 & 0x01;
305
+
306
+
ret = regulator_get_voltage(es8375->core_supply[ES8375_SUPPLY_VD].consumer);
307
+
switch (ret) {
308
+
case 1800000 ... 2000000:
309
+
es8375->vddd = ES8375_1V8;
310
+
break;
311
+
case 2500000 ... 3300000:
312
+
es8375->vddd = ES8375_3V3;
313
+
break;
314
+
default:
315
+
es8375->vddd = ES8375_3V3;
316
+
break;
317
+
}
318
+
319
+
coeff = get_coeff(es8375->vddd, dmic_enable, es8375->mclk_freq, params_rate(params));
320
+
if (coeff < 0) {
321
+
dev_warn(component->dev, "Clock coefficients do not match");
322
+
}
323
+
regmap_write(es8375->regmap, ES8375_CLK_MGR4,
324
+
coeff_div[coeff].Reg0x04);
325
+
regmap_write(es8375->regmap, ES8375_CLK_MGR5,
326
+
coeff_div[coeff].Reg0x05);
327
+
regmap_write(es8375->regmap, ES8375_CLK_MGR6,
328
+
coeff_div[coeff].Reg0x06);
329
+
regmap_write(es8375->regmap, ES8375_CLK_MGR7,
330
+
coeff_div[coeff].Reg0x07);
331
+
regmap_write(es8375->regmap, ES8375_CLK_MGR8,
332
+
coeff_div[coeff].Reg0x08);
333
+
regmap_write(es8375->regmap, ES8375_CLK_MGR9,
334
+
coeff_div[coeff].Reg0x09);
335
+
regmap_write(es8375->regmap, ES8375_CLK_MGR10,
336
+
coeff_div[coeff].Reg0x0A);
337
+
regmap_write(es8375->regmap, ES8375_CLK_MGR11,
338
+
coeff_div[coeff].Reg0x0B);
339
+
regmap_write(es8375->regmap, ES8375_ADC_OSR_GAIN,
340
+
coeff_div[coeff].Reg0x19);
341
+
342
+
switch (params_format(params)) {
343
+
case SNDRV_PCM_FORMAT_S16_LE:
344
+
iface |= 0x0c;
345
+
break;
346
+
case SNDRV_PCM_FORMAT_S20_3LE:
347
+
iface |= 0x04;
348
+
break;
349
+
case SNDRV_PCM_FORMAT_S24_LE:
350
+
break;
351
+
case SNDRV_PCM_FORMAT_S32_LE:
352
+
iface |= 0x10;
353
+
break;
354
+
}
355
+
356
+
regmap_update_bits(es8375->regmap, ES8375_SDP, 0x1c, iface);
357
+
358
+
return 0;
359
+
}
360
+
361
+
static int es8375_set_sysclk(struct snd_soc_dai *dai, int clk_id,
362
+
unsigned int freq, int dir)
363
+
{
364
+
struct snd_soc_component *component = dai->component;
365
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
366
+
367
+
es8375->mclk_freq = freq;
368
+
369
+
return 0;
370
+
}
371
+
372
+
static int es8375_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
373
+
{
374
+
struct snd_soc_component *component = dai->component;
375
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
376
+
unsigned int iface, codeciface;
377
+
378
+
regmap_read(es8375->regmap, ES8375_SDP, &codeciface);
379
+
380
+
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
381
+
case SND_SOC_DAIFMT_CBC_CFP:
382
+
es8375->mastermode = 1;
383
+
regmap_update_bits(es8375->regmap, ES8375_RESET1,
384
+
0x80, 0x80);
385
+
break;
386
+
case SND_SOC_DAIFMT_CBC_CFC:
387
+
es8375->mastermode = 0;
388
+
regmap_update_bits(es8375->regmap, ES8375_RESET1,
389
+
0x80, 0x00);
390
+
break;
391
+
default:
392
+
return -EINVAL;
393
+
}
394
+
395
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
396
+
case SND_SOC_DAIFMT_I2S:
397
+
codeciface &= 0xFC;
398
+
break;
399
+
case SND_SOC_DAIFMT_RIGHT_J:
400
+
return -EINVAL;
401
+
case SND_SOC_DAIFMT_LEFT_J:
402
+
codeciface &= 0xFC;
403
+
codeciface |= 0x01;
404
+
break;
405
+
case SND_SOC_DAIFMT_DSP_A:
406
+
codeciface &= 0xDC;
407
+
codeciface |= 0x03;
408
+
break;
409
+
case SND_SOC_DAIFMT_DSP_B:
410
+
codeciface &= 0xDC;
411
+
codeciface |= 0x23;
412
+
break;
413
+
default:
414
+
return -EINVAL;
415
+
}
416
+
417
+
regmap_read(es8375->regmap, ES8375_CLK_MGR3, &iface);
418
+
419
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
420
+
case SND_SOC_DAIFMT_NB_NF:
421
+
iface &= 0xFE;
422
+
codeciface &= 0xDF;
423
+
break;
424
+
case SND_SOC_DAIFMT_IB_IF:
425
+
iface |= 0x01;
426
+
codeciface |= 0x20;
427
+
break;
428
+
case SND_SOC_DAIFMT_IB_NF:
429
+
iface |= 0x01;
430
+
codeciface &= 0xDF;
431
+
break;
432
+
case SND_SOC_DAIFMT_NB_IF:
433
+
iface &= 0xFE;
434
+
codeciface |= 0x20;
435
+
break;
436
+
default:
437
+
return -EINVAL;
438
+
}
439
+
440
+
regmap_write(es8375->regmap, ES8375_CLK_MGR3, iface);
441
+
regmap_write(es8375->regmap, ES8375_SDP, codeciface);
442
+
443
+
return 0;
444
+
}
445
+
446
+
static int es8375_set_bias_level(struct snd_soc_component *component,
447
+
enum snd_soc_bias_level level)
448
+
{
449
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
450
+
int ret;
451
+
452
+
switch (level) {
453
+
case SND_SOC_BIAS_ON:
454
+
ret = clk_prepare_enable(es8375->mclk);
455
+
if (ret) {
456
+
dev_err(component->dev, "unable to prepare mclk\n");
457
+
return ret;
458
+
}
459
+
regmap_write(es8375->regmap, ES8375_CSM1, 0xA6);
460
+
break;
461
+
case SND_SOC_BIAS_PREPARE:
462
+
break;
463
+
case SND_SOC_BIAS_STANDBY:
464
+
regmap_write(es8375->regmap, ES8375_CSM1, 0x96);
465
+
clk_disable_unprepare(es8375->mclk);
466
+
break;
467
+
case SND_SOC_BIAS_OFF:
468
+
break;
469
+
}
470
+
return 0;
471
+
}
472
+
473
+
static int es8375_mute(struct snd_soc_dai *dai, int mute, int stream)
474
+
{
475
+
struct snd_soc_component *component = dai->component;
476
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
477
+
478
+
if (mute) {
479
+
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
480
+
regmap_update_bits(es8375->regmap, ES8375_SDP, 0x40, 0x40);
481
+
else
482
+
regmap_update_bits(es8375->regmap, ES8375_SDP2, 0x20, 0x20);
483
+
} else {
484
+
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
485
+
regmap_update_bits(es8375->regmap, ES8375_SDP, 0x40, 0x00);
486
+
else
487
+
regmap_update_bits(es8375->regmap, ES8375_SDP2, 0x20, 0x00);
488
+
}
489
+
490
+
return 0;
491
+
}
492
+
493
+
#define es8375_RATES SNDRV_PCM_RATE_8000_96000
494
+
495
+
#define es8375_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
496
+
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
497
+
498
+
static const struct snd_soc_dai_ops es8375_ops = {
499
+
.hw_params = es8375_hw_params,
500
+
.mute_stream = es8375_mute,
501
+
.set_sysclk = es8375_set_sysclk,
502
+
.set_fmt = es8375_set_dai_fmt,
503
+
};
504
+
505
+
static struct snd_soc_dai_driver es8375_dai = {
506
+
.name = "ES8375 HiFi",
507
+
.playback = {
508
+
.stream_name = "AIF1 Playback",
509
+
.channels_min = 1,
510
+
.channels_max = 2,
511
+
.rates = es8375_RATES,
512
+
.formats = es8375_FORMATS,
513
+
},
514
+
.capture = {
515
+
.stream_name = "AIF1 Capture",
516
+
.channels_min = 1,
517
+
.channels_max = 2,
518
+
.rates = es8375_RATES,
519
+
.formats = es8375_FORMATS,
520
+
},
521
+
.ops = &es8375_ops,
522
+
.symmetric_rate = 1,
523
+
};
524
+
525
+
static void es8375_init(struct snd_soc_component *component)
526
+
{
527
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
528
+
529
+
regmap_write(es8375->regmap, ES8375_CLK_MGR10, 0x95);
530
+
regmap_write(es8375->regmap, ES8375_CLK_MGR3, 0x48);
531
+
regmap_write(es8375->regmap, ES8375_DIV_SPKCLK, 0x18);
532
+
regmap_write(es8375->regmap, ES8375_CLK_MGR4, 0x02);
533
+
regmap_write(es8375->regmap, ES8375_CLK_MGR5, 0x05);
534
+
regmap_write(es8375->regmap, ES8375_CSM1, 0x82);
535
+
regmap_write(es8375->regmap, ES8375_VMID_CHARGE2, 0x20);
536
+
regmap_write(es8375->regmap, ES8375_VMID_CHARGE3, 0x20);
537
+
regmap_write(es8375->regmap, ES8375_DAC_CAL, 0x28);
538
+
regmap_write(es8375->regmap, ES8375_ANALOG_SPK1, 0xFC);
539
+
regmap_write(es8375->regmap, ES8375_ANALOG_SPK2, 0xE0);
540
+
regmap_write(es8375->regmap, ES8375_VMID_SEL, 0xFE);
541
+
regmap_write(es8375->regmap, ES8375_ANALOG1, 0xB8);
542
+
regmap_write(es8375->regmap, ES8375_SYS_CTRL2, 0x03);
543
+
regmap_write(es8375->regmap, ES8375_CLK_MGR2, 0x16);
544
+
regmap_write(es8375->regmap, ES8375_RESET1, 0x00);
545
+
msleep(80);
546
+
regmap_write(es8375->regmap, ES8375_CLK_MGR3, 0x00);
547
+
regmap_write(es8375->regmap, ES8375_CSM1, 0x86);
548
+
regmap_write(es8375->regmap, ES8375_CLK_MGR4, 0x0B);
549
+
regmap_write(es8375->regmap, ES8375_CLK_MGR5, 0x00);
550
+
regmap_write(es8375->regmap, ES8375_CLK_MGR6, 0x31);
551
+
regmap_write(es8375->regmap, ES8375_CLK_MGR7, 0x11);
552
+
regmap_write(es8375->regmap, ES8375_CLK_MGR8, 0x1F);
553
+
regmap_write(es8375->regmap, ES8375_CLK_MGR9, 0x00);
554
+
regmap_write(es8375->regmap, ES8375_ADC_OSR_GAIN, 0x1F);
555
+
regmap_write(es8375->regmap, ES8375_ADC2, 0x00);
556
+
regmap_write(es8375->regmap, ES8375_DAC2, 0x00);
557
+
regmap_write(es8375->regmap, ES8375_DAC_OTP, 0x88);
558
+
regmap_write(es8375->regmap, ES8375_ANALOG_SPK2, 0xE7);
559
+
regmap_write(es8375->regmap, ES8375_ANALOG2, 0xF0);
560
+
regmap_write(es8375->regmap, ES8375_ANALOG3, 0x40);
561
+
regmap_write(es8375->regmap, ES8375_CLK_MGR2, 0xFE);
562
+
563
+
regmap_update_bits(es8375->regmap, ES8375_SDP, 0x40, 0x40);
564
+
regmap_update_bits(es8375->regmap, ES8375_SDP2, 0x20, 0x20);
565
+
}
566
+
567
+
static int es8375_suspend(struct snd_soc_component *component)
568
+
{
569
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
570
+
571
+
regmap_write(es8375->regmap, ES8375_CSM1, 0x96);
572
+
regcache_cache_only(es8375->regmap, true);
573
+
regcache_mark_dirty(es8375->regmap);
574
+
return 0;
575
+
}
576
+
577
+
static int es8375_resume(struct snd_soc_component *component)
578
+
{
579
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
580
+
unsigned int reg;
581
+
582
+
regcache_cache_only(es8375->regmap, false);
583
+
regcache_cache_bypass(es8375->regmap, true);
584
+
regmap_read(es8375->regmap, ES8375_CLK_MGR2, ®);
585
+
regcache_cache_bypass(es8375->regmap, false);
586
+
587
+
if (reg == 0x00)
588
+
es8375_init(component);
589
+
else
590
+
es8375_set_bias_level(component, SND_SOC_BIAS_ON);
591
+
592
+
regcache_sync(es8375->regmap);
593
+
594
+
return 0;
595
+
}
596
+
597
+
static int es8375_codec_probe(struct snd_soc_component *component)
598
+
{
599
+
struct es8375_priv *es8375 = snd_soc_component_get_drvdata(component);
600
+
601
+
es8375->mastermode = 0;
602
+
603
+
es8375_init(component);
604
+
605
+
return 0;
606
+
}
607
+
608
+
static bool es8375_writeable_register(struct device *dev, unsigned int reg)
609
+
{
610
+
switch (reg) {
611
+
case ES8375_CHIP_VERSION:
612
+
case ES8375_CHIP_ID0:
613
+
case ES8375_CHIP_ID1:
614
+
case ES8375_SPK_OFFSET:
615
+
case ES8375_FLAGS2:
616
+
return false;
617
+
default:
618
+
return true;
619
+
}
620
+
}
621
+
622
+
static struct regmap_config es8375_regmap_config = {
623
+
.reg_bits = 8,
624
+
.val_bits = 8,
625
+
.max_register = ES8375_REG_MAX,
626
+
.cache_type = REGCACHE_MAPLE,
627
+
.use_single_read = true,
628
+
.use_single_write = true,
629
+
.writeable_reg = es8375_writeable_register,
630
+
};
631
+
632
+
static struct snd_soc_component_driver es8375_codec_driver = {
633
+
.probe = es8375_codec_probe,
634
+
.suspend = es8375_suspend,
635
+
.resume = es8375_resume,
636
+
.set_bias_level = es8375_set_bias_level,
637
+
.controls = es8375_snd_controls,
638
+
.num_controls = ARRAY_SIZE(es8375_snd_controls),
639
+
.dapm_widgets = es8375_dapm_widgets,
640
+
.num_dapm_widgets = ARRAY_SIZE(es8375_dapm_widgets),
641
+
.dapm_routes = es8375_dapm_routes,
642
+
.num_dapm_routes = ARRAY_SIZE(es8375_dapm_routes),
643
+
644
+
.idle_bias_on = 1,
645
+
.suspend_bias_off = 1,
646
+
};
647
+
648
+
static int es8375_read_device_properities(struct device *dev, struct es8375_priv *es8375)
649
+
{
650
+
int ret, i;
651
+
652
+
ret = device_property_read_u8(dev, "everest,mclk-src", &es8375->mclk_src);
653
+
if (ret != 0)
654
+
es8375->mclk_src = ES8375_MCLK_SOURCE;
655
+
dev_dbg(dev, "mclk-src %x", es8375->mclk_src);
656
+
657
+
for (i = 0; i < ARRAY_SIZE(es8375_core_supplies); i++)
658
+
es8375->core_supply[i].supply = es8375_core_supplies[i];
659
+
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8375_core_supplies), es8375->core_supply);
660
+
if (ret) {
661
+
dev_err(dev, "Failed to request core supplies %d\n", ret);
662
+
return ret;
663
+
}
664
+
665
+
es8375->mclk = devm_clk_get(dev, "mclk");
666
+
if (IS_ERR(es8375->mclk))
667
+
return dev_err_probe(dev, PTR_ERR(es8375->mclk), "unable to get mclk\n");
668
+
669
+
if (!es8375->mclk)
670
+
dev_warn(dev, "assuming static mclk\n");
671
+
672
+
ret = clk_prepare_enable(es8375->mclk);
673
+
if (ret) {
674
+
dev_err(dev, "unable to enable mclk\n");
675
+
return ret;
676
+
}
677
+
ret = regulator_bulk_enable(ARRAY_SIZE(es8375_core_supplies), es8375->core_supply);
678
+
if (ret) {
679
+
dev_err(dev, "Failed to enable core supplies: %d\n", ret);
680
+
clk_disable_unprepare(es8375->mclk);
681
+
return ret;
682
+
}
683
+
684
+
return 0;
685
+
}
686
+
687
+
static int es8375_i2c_probe(struct i2c_client *i2c_client)
688
+
{
689
+
struct es8375_priv *es8375;
690
+
struct device *dev = &i2c_client->dev;
691
+
int ret;
692
+
unsigned int val;
693
+
694
+
es8375 = devm_kzalloc(&i2c_client->dev, sizeof(*es8375), GFP_KERNEL);
695
+
if (!es8375)
696
+
return -ENOMEM;
697
+
698
+
es8375->regmap = devm_regmap_init_i2c(i2c_client,
699
+
&es8375_regmap_config);
700
+
if (IS_ERR(es8375->regmap))
701
+
return dev_err_probe(&i2c_client->dev, PTR_ERR(es8375->regmap),
702
+
"regmap_init() failed\n");
703
+
704
+
i2c_set_clientdata(i2c_client, es8375);
705
+
706
+
ret = regmap_read(es8375->regmap, ES8375_CHIP_ID1, &val);
707
+
if (ret < 0) {
708
+
dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n",
709
+
i2c_client->addr);
710
+
return ret;
711
+
}
712
+
713
+
if (val != 0x83) {
714
+
dev_err(&i2c_client->dev, "device at addr %X is not an es8375\n",
715
+
i2c_client->addr);
716
+
return -ENODEV;
717
+
}
718
+
719
+
ret = regmap_read(es8375->regmap, ES8375_CHIP_ID0, &val);
720
+
if (val != 0x75) {
721
+
dev_err(&i2c_client->dev, "device at addr %X is not an es8375\n",
722
+
i2c_client->addr);
723
+
return -ENODEV;
724
+
}
725
+
726
+
ret = es8375_read_device_properities(dev, es8375);
727
+
if (ret != 0) {
728
+
dev_err(&i2c_client->dev, "get an error from dts info %X\n", ret);
729
+
return ret;
730
+
}
731
+
732
+
return devm_snd_soc_register_component(&i2c_client->dev, &es8375_codec_driver,
733
+
&es8375_dai, 1);
734
+
}
735
+
736
+
static void es8375_i2c_shutdown(struct i2c_client *i2c)
737
+
{
738
+
struct es8375_priv *es8375;
739
+
740
+
es8375 = i2c_get_clientdata(i2c);
741
+
742
+
regmap_write(es8375->regmap, ES8375_CSM1, 0x3C);
743
+
regmap_write(es8375->regmap, ES8375_CLK_MGR3, 0x48);
744
+
regmap_write(es8375->regmap, ES8375_CSM2, 0x80);
745
+
regmap_write(es8375->regmap, ES8375_CSM1, 0x3E);
746
+
regmap_write(es8375->regmap, ES8375_CLK_MGR10, 0x15);
747
+
regmap_write(es8375->regmap, ES8375_SYS_CTRL2, 0x0C);
748
+
regmap_write(es8375->regmap, ES8375_RESET1, 0x00);
749
+
regmap_write(es8375->regmap, ES8375_CSM2, 0x00);
750
+
751
+
regulator_bulk_disable(ARRAY_SIZE(es8375_core_supplies), es8375->core_supply);
752
+
clk_disable_unprepare(es8375->mclk);
753
+
}
754
+
755
+
static const struct i2c_device_id es8375_id[] = {
756
+
{"es8375"},
757
+
{ }
758
+
};
759
+
MODULE_DEVICE_TABLE(i2c, es8375_id);
760
+
761
+
#ifdef CONFIG_ACPI
762
+
static const struct acpi_device_id es8375_acpi_match[] = {
763
+
{"ESSX8375", 0},
764
+
{},
765
+
};
766
+
767
+
MODULE_DEVICE_TABLE(acpi, es8375_acpi_match);
768
+
#endif
769
+
770
+
#ifdef CONFIG_OF
771
+
static const struct of_device_id es8375_of_match[] = {
772
+
{.compatible = "everest,es8375",},
773
+
{}
774
+
};
775
+
776
+
MODULE_DEVICE_TABLE(of, es8375_of_match);
777
+
#endif
778
+
779
+
static struct i2c_driver es8375_i2c_driver = {
780
+
.driver = {
781
+
.name = "es8375",
782
+
.of_match_table = of_match_ptr(es8375_of_match),
783
+
.acpi_match_table = ACPI_PTR(es8375_acpi_match),
784
+
},
785
+
.shutdown = es8375_i2c_shutdown,
786
+
.probe = es8375_i2c_probe,
787
+
.id_table = es8375_id,
788
+
};
789
+
module_i2c_driver(es8375_i2c_driver);
790
+
791
+
MODULE_DESCRIPTION("ASoC ES8375 driver");
792
+
MODULE_AUTHOR("Michael Zhang <zhangyi@everest-semi.com>");
793
+
MODULE_LICENSE("GPL");
+123
sound/soc/codecs/es8375.h
+123
sound/soc/codecs/es8375.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* ES8375.h -- ES8375 ALSA SoC Audio Codec
4
+
*
5
+
* Authors:
6
+
*
7
+
* Based on ES8375.h by Michael Zhang
8
+
*/
9
+
#ifndef _ES8375_H
10
+
#define _ES8375_H
11
+
12
+
// Registors
13
+
#define ES8375_RESET1 0x00
14
+
#define ES8375_MCLK_SEL 0x01
15
+
#define ES8375_CLK_MGR2 0x02
16
+
#define ES8375_CLK_MGR3 0x03
17
+
#define ES8375_CLK_MGR4 0x04
18
+
#define ES8375_CLK_MGR5 0x05
19
+
#define ES8375_CLK_MGR6 0x06
20
+
#define ES8375_CLK_MGR7 0x07
21
+
#define ES8375_CLK_MGR8 0x08
22
+
#define ES8375_CLK_MGR9 0x09
23
+
#define ES8375_CLK_MGR10 0x0A
24
+
#define ES8375_CLK_MGR11 0x0B
25
+
#define ES8375_CLK_MGR12 0x0C
26
+
#define ES8375_DIV_SPKCLK 0x0E
27
+
#define ES8375_CSM1 0x0F
28
+
#define ES8375_CSM2 0x10
29
+
#define ES8375_VMID_CHARGE2 0x11
30
+
#define ES8375_VMID_CHARGE3 0x12
31
+
#define ES8375_SDP 0x15
32
+
#define ES8375_SDP2 0x16
33
+
#define ES8375_ADC1 0x17
34
+
#define ES8375_ADC2 0x18
35
+
#define ES8375_ADC_OSR_GAIN 0x19
36
+
#define ES8375_ADC_VOLUME 0x1A
37
+
#define ES8375_ADC_AUTOMUTE 0x1B
38
+
#define ES8375_ADC_AUTOMUTE_ATTN 0x1C
39
+
#define ES8375_HPF1 0x1D
40
+
#define ES8375_DAC1 0x1F
41
+
#define ES8375_DAC2 0x20
42
+
#define ES8375_DAC_VOLUME 0x21
43
+
#define ES8375_DAC_VPPSCALE 0x22
44
+
#define ES8375_DAC_AUTOMUTE1 0x23
45
+
#define ES8375_DAC_AUTOMUTE 0x24
46
+
#define ES8375_DAC_CAL 0x25
47
+
#define ES8375_DAC_OTP 0x27
48
+
#define ES8375_ANALOG_SPK1 0x28
49
+
#define ES8375_ANALOG_SPK2 0x29
50
+
#define ES8375_VMID_SEL 0x2D
51
+
#define ES8375_ANALOG1 0x2E
52
+
#define ES8375_ANALOG2 0x32
53
+
#define ES8375_ANALOG3 0x37
54
+
#define ES8375_ADC2DAC_CLKTRI 0xF8
55
+
#define ES8375_SYS_CTRL2 0xF9
56
+
#define ES8375_FLAGS2 0xFB
57
+
#define ES8375_SPK_OFFSET 0xFC
58
+
#define ES8375_CHIP_ID1 0xFD
59
+
#define ES8375_CHIP_ID0 0xFE
60
+
#define ES8375_CHIP_VERSION 0xFF
61
+
62
+
// Bit Shifts
63
+
#define ADC_OSR_GAIN_SHIFT_0 0
64
+
#define ADC_RAMPRATE_SHIFT_0 0
65
+
#define ADC_VOLUME_SHIFT_0 0
66
+
#define ADC_AUTOMUTE_NG_SHIFT_0 0
67
+
#define ADC_AUTOMUTE_ATTN_SHIFT_0 0
68
+
#define DAC_RAMPRATE_SHIFT_0 0
69
+
#define DAC_VOLUME_SHIFT_0 0
70
+
#define DAC_VPPSCALE_SHIFT_0 0
71
+
#define DAC_AUTOMUTE_NG_SHIFT_0 0
72
+
#define DAC_AUTOMUTE_ATTN_SHIFT_0 0
73
+
#define DMIC_GAIN_SHIFT_2 2
74
+
#define ADC_AUTOMUTE_WS_SHIFT_3 3
75
+
#define DMIC_POL_SHIFT_4 4
76
+
#define DAC_RAMCLR_SHIFT_4 4
77
+
#define ES8375_EN_MODL_SHIFT_4 4
78
+
#define ADC_RAMCLR_SHIFT_5 5
79
+
#define ADC_HPF_SHIFT_5 5
80
+
#define DAC_INV_SHIFT_5 5
81
+
#define DAC_AUTOMUTE_WS_SHIFT_5 5
82
+
#define ES8375_EN_PGAL_SHIFT_5 5
83
+
#define ES8375_ADC_P2S_MUTE_SHIFT_5 5
84
+
#define ADC_INV_SHIFT_6 6
85
+
#define DAC_DEMMUTE_SHIFT_6 6
86
+
#define ES8375_DAC_S2P_MUTE_SHIFT_6 6
87
+
#define ADC_SRC_SHIFT_7 7
88
+
#define ADC_AUTOMUTE_SHIFT_7 7
89
+
#define DAC_DSMMUTE_SHIFT_7 7
90
+
#define DAC_AUTOMUTE_EN_SHIFT_7 7
91
+
92
+
// Function values
93
+
#define ES8375_ADC_OSR_GAIN_MAX 0x3F
94
+
#define ES8375_DMIC_GAIN_MAX 0x04
95
+
#define ES8375_ADC_AUTOMUTE_ATTN_MAX 0x1F
96
+
#define ES8375_AUTOMUTE_NG_MAX 0x07
97
+
#define ES8375_ADC_VOLUME_MAX 0xFF
98
+
#define ES8375_DAC_VOLUME_MAX 0xFF
99
+
#define ES8375_DAC_VPPSCALE_MAX 0x3F
100
+
#define ES8375_DAC_AUTOMUTE_ATTN_MAX 0x17
101
+
#define ES8375_REG_MAX 0xFF
102
+
103
+
enum ES8375_supplies {
104
+
ES8375_SUPPLY_VD = 0,
105
+
ES8375_SUPPLY_VA,
106
+
};
107
+
108
+
// Properties
109
+
#define ES8375_3V3 1
110
+
#define ES8375_1V8 0
111
+
112
+
#define ES8375_MCLK_PIN 0
113
+
#define ES8375_BCLK_PIN 1
114
+
#define ES8375_MCLK_SOURCE ES8375_MCLK_PIN
115
+
116
+
#define DMIC_POSITIVE_EDGE 0
117
+
#define DMIC_NEGATIVE_EDGE 1
118
+
#define DMIC_POL DMIC_POSITIVE_EDGE
119
+
120
+
#define PA_SHUTDOWN 0
121
+
#define PA_ENABLE 1
122
+
123
+
#endif