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[ARM] 4521/2: S3C: Reorganise VA mapping headers

Reorganise the definition of the virtual addresses
used into a common header and update the users to
rename S3C2410 items into a more common S3C defined
macros.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by Ben Dooks and committed by Russell King 530ef3c2 bf2a3a26

+65 -39
unified split
+9 -23
include/asm-arm/arch-s3c2410/map.h
··· 13 #ifndef __ASM_ARCH_MAP_H 14 #define __ASM_ARCH_MAP_H 15 16 - /* we have a bit of a tight squeeze to fit all our registers from 17 - * 0xF00000000 upwards, since we use all of the nGCS space in some 18 - * capacity, and also need to fit the S3C2410 registers in as well... 19 - * 20 - * we try to ensure stuff like the IRQ registers are available for 21 - * an single MOVS instruction (ie, only 8 bits of set data) 22 - * 23 - * Note, we are trying to remove some of these from the implementation 24 - * as they are only useful to certain drivers... 25 - */ 26 27 - #ifndef __ASSEMBLY__ 28 - #define S3C2410_ADDR(x) ((void __iomem __force *)0xF0000000 + (x)) 29 - #else 30 - #define S3C2410_ADDR(x) (0xF0000000 + (x)) 31 - #endif 32 33 /* interrupt controller is the first thing we put in, to make 34 * the assembly code for the irq detection easier 35 */ 36 - #define S3C24XX_VA_IRQ S3C2410_ADDR(0x00000000) 37 #define S3C2410_PA_IRQ (0x4A000000) 38 #define S3C24XX_SZ_IRQ SZ_1M 39 40 /* memory controller registers */ 41 - #define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000) 42 #define S3C2410_PA_MEMCTRL (0x48000000) 43 #define S3C24XX_SZ_MEMCTRL SZ_1M 44 ··· 38 #define S3C24XX_SZ_DMA SZ_1M 39 40 /* Clock and Power management */ 41 - #define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000) 42 #define S3C2410_PA_CLKPWR (0x4C000000) 43 #define S3C24XX_SZ_CLKPWR SZ_1M 44 ··· 51 #define S3C24XX_SZ_NAND SZ_1M 52 53 /* UARTs */ 54 - #define S3C24XX_VA_UART S3C2410_ADDR(0x00400000) 55 #define S3C2410_PA_UART (0x50000000) 56 #define S3C24XX_SZ_UART SZ_1M 57 58 /* Timers */ 59 - #define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000) 60 #define S3C2410_PA_TIMER (0x51000000) 61 #define S3C24XX_SZ_TIMER SZ_1M 62 ··· 65 #define S3C24XX_SZ_USBDEV SZ_1M 66 67 /* Watchdog */ 68 - #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000) 69 #define S3C2410_PA_WATCHDOG (0x53000000) 70 #define S3C24XX_SZ_WATCHDOG SZ_1M 71 ··· 83 * it is the same distance apart from the UART in the 84 * phsyical address space, as the initial mapping for the IO 85 * is done as a 1:1 maping. This puts it (currently) at 86 - * 0xF6800000, which is not in the way of any current mapping 87 * by the base system. 88 */ 89 ··· 139 #define S3C2410_CS7 (0x38000000) 140 141 #define S3C2410_SDRAM_PA (S3C2410_CS6) 142 - 143 144 /* Use a single interface for common resources between S3C24XX cpus */ 145
··· 13 #ifndef __ASM_ARCH_MAP_H 14 #define __ASM_ARCH_MAP_H 15 16 + #include <asm/plat-s3c/map.h> 17 18 + #define S3C2410_ADDR(x) S3C_ADDR(x) 19 20 /* interrupt controller is the first thing we put in, to make 21 * the assembly code for the irq detection easier 22 */ 23 + #define S3C24XX_VA_IRQ S3C_VA_IRQ 24 #define S3C2410_PA_IRQ (0x4A000000) 25 #define S3C24XX_SZ_IRQ SZ_1M 26 27 /* memory controller registers */ 28 + #define S3C24XX_VA_MEMCTRL S3C_VA_MEM 29 #define S3C2410_PA_MEMCTRL (0x48000000) 30 #define S3C24XX_SZ_MEMCTRL SZ_1M 31 ··· 51 #define S3C24XX_SZ_DMA SZ_1M 52 53 /* Clock and Power management */ 54 + #define S3C24XX_VA_CLKPWR S3C_VA_SYS 55 #define S3C2410_PA_CLKPWR (0x4C000000) 56 #define S3C24XX_SZ_CLKPWR SZ_1M 57 ··· 64 #define S3C24XX_SZ_NAND SZ_1M 65 66 /* UARTs */ 67 + #define S3C24XX_VA_UART S3C_VA_UART 68 #define S3C2410_PA_UART (0x50000000) 69 #define S3C24XX_SZ_UART SZ_1M 70 71 /* Timers */ 72 + #define S3C24XX_VA_TIMER S3C_VA_TIMER 73 #define S3C2410_PA_TIMER (0x51000000) 74 #define S3C24XX_SZ_TIMER SZ_1M 75 ··· 78 #define S3C24XX_SZ_USBDEV SZ_1M 79 80 /* Watchdog */ 81 + #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG 82 #define S3C2410_PA_WATCHDOG (0x53000000) 83 #define S3C24XX_SZ_WATCHDOG SZ_1M 84 ··· 96 * it is the same distance apart from the UART in the 97 * phsyical address space, as the initial mapping for the IO 98 * is done as a 1:1 maping. This puts it (currently) at 99 + * 0xFA800000, which is not in the way of any current mapping 100 * by the base system. 101 */ 102 ··· 152 #define S3C2410_CS7 (0x38000000) 153 154 #define S3C2410_SDRAM_PA (S3C2410_CS6) 155 156 /* Use a single interface for common resources between S3C24XX cpus */ 157
+40
include/asm-arm/plat-s3c/map.h
···
··· 1 + /* linux/include/asm-arm/plat-s3c/map.h 2 + * 3 + * Copyright 2003, 2007 Simtec Electronics 4 + * http://armlinux.simtec.co.uk/ 5 + * Ben Dooks <ben@simtec.co.uk> 6 + * 7 + * S3C - Memory map definitions (virtual addresses) 8 + * 9 + * This program is free software; you can redistribute it and/or modify 10 + * it under the terms of the GNU General Public License version 2 as 11 + * published by the Free Software Foundation. 12 + */ 13 + 14 + #ifndef __ASM_PLAT_MAP_H 15 + #define __ASM_PLAT_MAP_H __FILE__ 16 + 17 + /* Fit all our registers in at 0xF4000000 upwards, trying to use as 18 + * little of the VA space as possible so vmalloc and friends have a 19 + * better chance of getting memory. 20 + * 21 + * we try to ensure stuff like the IRQ registers are available for 22 + * an single MOVS instruction (ie, only 8 bits of set data) 23 + */ 24 + 25 + #define S3C_ADDR_BASE (0xF4000000) 26 + 27 + #ifndef __ASSEMBLY__ 28 + #define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) 29 + #else 30 + #define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) 31 + #endif 32 + 33 + #define S3C_VA_IRQ S3C_ADDR(0x000000000) /* irq controller(s) */ 34 + #define S3C_VA_SYS S3C_ADDR(0x001000000) /* system control */ 35 + #define S3C_VA_MEM S3C_ADDR(0x002000000) /* system control */ 36 + #define S3C_VA_TIMER S3C_ADDR(0x003000000) /* timer block */ 37 + #define S3C_VA_WATCHDOG S3C_ADDR(0x004000000) /* watchdog */ 38 + #define S3C_VA_UART S3C_ADDR(0x010000000) /* UART */ 39 + 40 + #endif /* __ASM_PLAT_MAP_H */
+4 -4
include/asm-arm/plat-s3c/regs-serial.h
··· 32 #ifndef __ASM_ARM_REGS_SERIAL_H 33 #define __ASM_ARM_REGS_SERIAL_H 34 35 - #define S3C24XX_VA_UART0 (S3C24XX_VA_UART) 36 - #define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 ) 37 - #define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 ) 38 - #define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 ) 39 40 #define S3C2410_PA_UART0 (S3C24XX_PA_UART) 41 #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
··· 32 #ifndef __ASM_ARM_REGS_SERIAL_H 33 #define __ASM_ARM_REGS_SERIAL_H 34 35 + #define S3C24XX_VA_UART0 (S3C_VA_UART) 36 + #define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) 37 + #define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) 38 + #define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) 39 40 #define S3C2410_PA_UART0 (S3C24XX_PA_UART) 41 #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
+8 -8
include/asm-arm/plat-s3c/regs-timer.h
··· 14 #ifndef __ASM_ARCH_REGS_TIMER_H 15 #define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $" 16 17 - #define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x)) 18 - #define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c)) 19 20 - #define S3C2410_TCFG0 S3C2410_TIMERREG(0x00) 21 - #define S3C2410_TCFG1 S3C2410_TIMERREG(0x04) 22 - #define S3C2410_TCON S3C2410_TIMERREG(0x08) 23 24 #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) 25 #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) ··· 71 72 /* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ 73 74 - #define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00) 75 - #define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04) 76 - #define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) 77 78 #define S3C2410_TCON_T4RELOAD (1<<22) 79 #define S3C2410_TCON_T4MANUALUPD (1<<21)
··· 14 #ifndef __ASM_ARCH_REGS_TIMER_H 15 #define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $" 16 17 + #define S3C_TIMERREG(x) (S3C_VA_TIMER + (x)) 18 + #define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c)) 19 20 + #define S3C2410_TCFG0 S3C_TIMERREG(0x00) 21 + #define S3C2410_TCFG1 S3C_TIMERREG(0x04) 22 + #define S3C2410_TCON S3C_TIMERREG(0x08) 23 24 #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) 25 #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) ··· 71 72 /* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ 73 74 + #define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00) 75 + #define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04) 76 + #define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) 77 78 #define S3C2410_TCON_T4RELOAD (1<<22) 79 #define S3C2410_TCON_T4MANUALUPD (1<<21)
+4 -4
include/asm-arm/plat-s3c/regs-watchdog.h
··· 14 #ifndef __ASM_ARCH_REGS_WATCHDOG_H 15 #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $" 16 17 - #define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG) 18 19 - #define S3C2410_WTCON S3C2410_WDOGREG(0x00) 20 - #define S3C2410_WTDAT S3C2410_WDOGREG(0x04) 21 - #define S3C2410_WTCNT S3C2410_WDOGREG(0x08) 22 23 /* the watchdog can either generate a reset pulse, or an 24 * interrupt.
··· 14 #ifndef __ASM_ARCH_REGS_WATCHDOG_H 15 #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $" 16 17 + #define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) 18 19 + #define S3C2410_WTCON S3C_WDOGREG(0x00) 20 + #define S3C2410_WTDAT S3C_WDOGREG(0x04) 21 + #define S3C2410_WTCNT S3C_WDOGREG(0x08) 22 23 /* the watchdog can either generate a reset pulse, or an 24 * interrupt.