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ASoC: dt-binding: Convert mt8183-afe-pcm to dt-schema
Convert the MediaTek MT8183 AFE PCM Device Tree binding from the old
.txt format to dt-schema format to improve validation.
While converting, also document all clock inputs and memory-region
used by the AFE block.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Link: https://patch.msgid.link/20250826-mtk-dtb-warnings-v3-2-20e89886a20e@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Julien Massot
and committed by
Mark Brown
52aefc1e
5fa7d739
+228
-42
+228
Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml
+228
Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mediatek,mt8183-audio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek AFE PCM controller for mt8183
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maintainers:
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- Julien Massot <jmassot@collabora.com>
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properties:
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compatible:
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const: mediatek,mt8183-audio
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: audiosys
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power-domains:
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maxItems: 1
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memory-region:
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maxItems: 1
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clocks:
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items:
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- description: AFE clock
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- description: ADDA DAC clock
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- description: ADDA DAC pre-distortion clock
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- description: ADDA ADC clock
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- description: ADDA6 ADC clock
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- description: Audio low-jitter 22.5792m clock
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- description: Audio low-jitter 24.576m clock
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- description: Audio PLL1 tuner clock
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- description: Audio PLL2 tuner clock
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- description: I2S1 bit clock
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- description: I2S2 bit clock
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- description: I2S3 bit clock
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- description: I2S4 bit clock
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- description: Audio Time-Division Multiplexing interface clock
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- description: Powerdown Audio test model clock
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- description: Audio infra sys clock
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- description: Audio infra 26M clock
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- description: Mux for audio clock
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- description: Mux for audio internal bus clock
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- description: Mux main divider by 4
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- description: Primary audio mux
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- description: Primary audio PLL
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- description: Secondary audio mux
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- description: Secondary audio PLL
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- description: Primary audio en-generator clock
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- description: Primary PLL divider by 4 for IEC
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- description: Secondary audio en-generator clock
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- description: Secondary PLL divider by 8 for IEC
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- description: Mux selector for I2S port 0
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- description: Mux selector for I2S port 1
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- description: Mux selector for I2S port 2
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- description: Mux selector for I2S port 3
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- description: Mux selector for I2S port 4
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- description: Mux selector for I2S port 5
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- description: APLL1 and APLL2 divider for I2S port 0
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- description: APLL1 and APLL2 divider for I2S port 1
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- description: APLL1 and APLL2 divider for I2S port 2
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- description: APLL1 and APLL2 divider for I2S port 3
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- description: APLL1 and APLL2 divider for I2S port 4
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- description: APLL1 and APLL2 divider for IEC
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- description: 26MHz clock for audio subsystem
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clock-names:
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items:
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- const: aud_afe_clk
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- const: aud_dac_clk
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- const: aud_dac_predis_clk
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- const: aud_adc_clk
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- const: aud_adc_adda6_clk
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- const: aud_apll22m_clk
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- const: aud_apll24m_clk
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- const: aud_apll1_tuner_clk
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- const: aud_apll2_tuner_clk
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- const: aud_i2s1_bclk_sw
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- const: aud_i2s2_bclk_sw
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- const: aud_i2s3_bclk_sw
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- const: aud_i2s4_bclk_sw
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- const: aud_tdm_clk
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- const: aud_tml_clk
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- const: aud_infra_clk
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- const: mtkaif_26m_clk
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- const: top_mux_audio
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- const: top_mux_aud_intbus
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- const: top_syspll_d2_d4
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- const: top_mux_aud_1
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- const: top_apll1_ck
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- const: top_mux_aud_2
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- const: top_apll2_ck
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- const: top_mux_aud_eng1
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- const: top_apll1_d8
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- const: top_mux_aud_eng2
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- const: top_apll2_d8
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- const: top_i2s0_m_sel
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- const: top_i2s1_m_sel
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- const: top_i2s2_m_sel
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- const: top_i2s3_m_sel
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- const: top_i2s4_m_sel
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- const: top_i2s5_m_sel
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- const: top_apll12_div0
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- const: top_apll12_div1
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- const: top_apll12_div2
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- const: top_apll12_div3
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- const: top_apll12_div4
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- const: top_apll12_divb
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- const: top_clk26m_clk
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required:
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- compatible
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- interrupts
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- resets
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- reset-names
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- power-domains
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/reset/mt8183-resets.h>
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audio-controller {
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compatible = "mediatek,mt8183-audio";
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
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resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
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reset-names = "audiosys";
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power-domains = <&spm MT8183_POWER_DOMAIN_AUDIO>;
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clocks = <&audiosys CLK_AUDIO_AFE>,
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<&audiosys CLK_AUDIO_DAC>,
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<&audiosys CLK_AUDIO_DAC_PREDIS>,
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<&audiosys CLK_AUDIO_ADC>,
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<&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
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<&audiosys CLK_AUDIO_22M>,
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<&audiosys CLK_AUDIO_24M>,
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<&audiosys CLK_AUDIO_APLL_TUNER>,
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<&audiosys CLK_AUDIO_APLL2_TUNER>,
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<&audiosys CLK_AUDIO_I2S1>,
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<&audiosys CLK_AUDIO_I2S2>,
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<&audiosys CLK_AUDIO_I2S3>,
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<&audiosys CLK_AUDIO_I2S4>,
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<&audiosys CLK_AUDIO_TDM>,
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<&audiosys CLK_AUDIO_TML>,
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<&infracfg CLK_INFRA_AUDIO>,
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<&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
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<&topckgen CLK_TOP_MUX_AUDIO>,
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<&topckgen CLK_TOP_MUX_AUD_INTBUS>,
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<&topckgen CLK_TOP_SYSPLL_D2_D4>,
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<&topckgen CLK_TOP_MUX_AUD_1>,
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<&topckgen CLK_TOP_APLL1_CK>,
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<&topckgen CLK_TOP_MUX_AUD_2>,
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<&topckgen CLK_TOP_APLL2_CK>,
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<&topckgen CLK_TOP_MUX_AUD_ENG1>,
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<&topckgen CLK_TOP_APLL1_D8>,
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<&topckgen CLK_TOP_MUX_AUD_ENG2>,
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<&topckgen CLK_TOP_APLL2_D8>,
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<&topckgen CLK_TOP_MUX_APLL_I2S0>,
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<&topckgen CLK_TOP_MUX_APLL_I2S1>,
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<&topckgen CLK_TOP_MUX_APLL_I2S2>,
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<&topckgen CLK_TOP_MUX_APLL_I2S3>,
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<&topckgen CLK_TOP_MUX_APLL_I2S4>,
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<&topckgen CLK_TOP_MUX_APLL_I2S5>,
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<&topckgen CLK_TOP_APLL12_DIV0>,
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<&topckgen CLK_TOP_APLL12_DIV1>,
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<&topckgen CLK_TOP_APLL12_DIV2>,
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<&topckgen CLK_TOP_APLL12_DIV3>,
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<&topckgen CLK_TOP_APLL12_DIV4>,
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<&topckgen CLK_TOP_APLL12_DIVB>,
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<&clk26m>;
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clock-names = "aud_afe_clk",
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"aud_dac_clk",
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"aud_dac_predis_clk",
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"aud_adc_clk",
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"aud_adc_adda6_clk",
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"aud_apll22m_clk",
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"aud_apll24m_clk",
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"aud_apll1_tuner_clk",
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"aud_apll2_tuner_clk",
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"aud_i2s1_bclk_sw",
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"aud_i2s2_bclk_sw",
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"aud_i2s3_bclk_sw",
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"aud_i2s4_bclk_sw",
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"aud_tdm_clk",
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"aud_tml_clk",
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"aud_infra_clk",
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"mtkaif_26m_clk",
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"top_mux_audio",
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"top_mux_aud_intbus",
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"top_syspll_d2_d4",
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"top_mux_aud_1",
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"top_apll1_ck",
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"top_mux_aud_2",
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"top_apll2_ck",
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"top_mux_aud_eng1",
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"top_apll1_d8",
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"top_mux_aud_eng2",
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"top_apll2_d8",
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"top_i2s0_m_sel",
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"top_i2s1_m_sel",
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"top_i2s2_m_sel",
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"top_i2s3_m_sel",
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"top_i2s4_m_sel",
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"top_i2s5_m_sel",
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"top_apll12_div0",
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"top_apll12_div1",
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"top_apll12_div2",
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"top_apll12_div3",
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"top_apll12_div4",
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"top_apll12_divb",
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"top_clk26m_clk";
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};
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...
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Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt
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Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt
···
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Mediatek AFE PCM controller for mt8183
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Required properties:
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- compatible = "mediatek,mt68183-audio";
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- reg: register location and size
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- interrupts: should contain AFE interrupt
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- resets: Must contain an entry for each entry in reset-names
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See ../reset/reset.txt for details.
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- reset-names: should have these reset names:
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"audiosys";
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- power-domains: should define the power domain
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- clocks: Must contain an entry for each entry in clock-names
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- clock-names: should have these clock names:
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"infra_sys_audio_clk",
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"mtkaif_26m_clk",
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"top_mux_audio",
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"top_mux_aud_intbus",
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"top_sys_pll3_d4",
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"top_clk26m_clk";
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-
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Example:
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afe: mt8183-afe-pcm@11220000 {
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compatible = "mediatek,mt8183-audio";
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reg = <0 0x11220000 0 0x1000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
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resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
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reset-names = "audiosys";
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power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>;
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clocks = <&infrasys CLK_INFRA_AUDIO>,
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<&infrasys CLK_INFRA_AUDIO_26M_BCLK>,
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<&topckgen CLK_TOP_MUX_AUDIO>,
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<&topckgen CLK_TOP_MUX_AUD_INTBUS>,
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<&topckgen CLK_TOP_SYSPLL_D2_D4>,
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<&clk26m>;
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clock-names = "infra_sys_audio_clk",
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"mtkaif_26m_clk",
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"top_mux_audio",
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"top_mux_aud_intbus",
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"top_sys_pll_d2_d4",
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"top_clk26m_clk";
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};