tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm: meson: use match data to detect vpu compatibility

This patch introduce new enum which contains all VPU family (GXBB,
GXL, GXM and G12A).
This enum is used to detect the VPU compatible with the device.

We only need to set .data to the corresponding enum in the device
table, no need to check .compatible string anymore.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87imqpz21w.fsf@masson.i-did-not-set--mail-host-address--so-tickle-me

authored by

Julien Masson and committed by
Neil Armstrong 528a25d0 ade92599

+77 -62
+1 -1
drivers/gpu/drm/meson/meson_crtc.c
··· 575 575 return ret; 576 576 } 577 577 578 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 578 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 579 579 meson_crtc->enable_osd1 = meson_g12a_crtc_enable_osd1; 580 580 meson_crtc->enable_vd1 = meson_g12a_crtc_enable_vd1; 581 581 meson_crtc->viu_offset = MESON_G12A_VIU_OFFSET;
+10 -4
drivers/gpu/drm/meson/meson_drv.c
··· 209 209 priv->drm = drm; 210 210 priv->dev = dev; 211 211 212 + priv->compat = (enum vpu_compatible)of_device_get_match_data(priv->dev); 213 + 212 214 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu"); 213 215 regs = devm_ioremap_resource(dev, res); 214 216 if (IS_ERR(regs)) { ··· 455 453 }; 456 454 457 455 static const struct of_device_id dt_match[] = { 458 - { .compatible = "amlogic,meson-gxbb-vpu" }, 459 - { .compatible = "amlogic,meson-gxl-vpu" }, 460 - { .compatible = "amlogic,meson-gxm-vpu" }, 461 - { .compatible = "amlogic,meson-g12a-vpu" }, 456 + { .compatible = "amlogic,meson-gxbb-vpu", 457 + .data = (void *)VPU_COMPATIBLE_GXBB }, 458 + { .compatible = "amlogic,meson-gxl-vpu", 459 + .data = (void *)VPU_COMPATIBLE_GXL }, 460 + { .compatible = "amlogic,meson-gxm-vpu", 461 + .data = (void *)VPU_COMPATIBLE_GXM }, 462 + { .compatible = "amlogic,meson-g12a-vpu", 463 + .data = (void *)VPU_COMPATIBLE_G12A }, 462 464 {} 463 465 }; 464 466 MODULE_DEVICE_TABLE(of, dt_match);
+11 -2
drivers/gpu/drm/meson/meson_drv.h
··· 9 9 10 10 #include <linux/device.h> 11 11 #include <linux/of.h> 12 + #include <linux/of_device.h> 12 13 #include <linux/regmap.h> 13 14 14 15 struct drm_crtc; ··· 17 16 struct drm_plane; 18 17 struct meson_drm; 19 18 19 + enum vpu_compatible { 20 + VPU_COMPATIBLE_GXBB = 0, 21 + VPU_COMPATIBLE_GXL = 1, 22 + VPU_COMPATIBLE_GXM = 2, 23 + VPU_COMPATIBLE_G12A = 3, 24 + }; 25 + 20 26 struct meson_drm { 21 27 struct device *dev; 28 + enum vpu_compatible compat; 22 29 void __iomem *io_base; 23 30 struct regmap *hhi; 24 31 int vsync_irq; ··· 125 116 }; 126 117 127 118 static inline int meson_vpu_is_compatible(struct meson_drm *priv, 128 - const char *compat) 119 + enum vpu_compatible family) 129 120 { 130 - return of_device_is_compatible(priv->dev->of_node, compat); 121 + return priv->compat == family; 131 122 } 132 123 133 124 #endif /* __MESON_DRV_H */
+1 -1
drivers/gpu/drm/meson/meson_dw_hdmi.c
··· 937 937 reset_control_reset(meson_dw_hdmi->hdmitx_phy); 938 938 939 939 /* Enable APB3 fail on error */ 940 - if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 940 + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 941 941 writel_bits_relaxed(BIT(15), BIT(15), 942 942 meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); 943 943 writel_bits_relaxed(BIT(15), BIT(15),
+1 -1
drivers/gpu/drm/meson/meson_overlay.c
··· 513 513 priv->viu.vd1_enabled = false; 514 514 515 515 /* Disable VD1 */ 516 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 516 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 517 517 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); 518 518 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); 519 519 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
+5 -5
drivers/gpu/drm/meson/meson_plane.c
··· 138 138 OSD_ENDIANNESS_LE); 139 139 140 140 /* On GXBB, Use the old non-HDR RGB2YUV converter */ 141 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 141 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) 142 142 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; 143 143 144 144 switch (fb->format->format) { ··· 292 292 priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; 293 293 priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; 294 294 295 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 295 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 296 296 priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1; 297 297 priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1; 298 298 priv->viu.osb_blend0_size = dst_h << 16 | dst_w; ··· 308 308 309 309 if (!meson_plane->enabled) { 310 310 /* Reset OSD1 before enabling it on GXL+ SoCs */ 311 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 312 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 311 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 312 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) 313 313 meson_viu_osd1_reset(priv); 314 314 315 315 meson_plane->enabled = true; ··· 327 327 struct meson_drm *priv = meson_plane->priv; 328 328 329 329 /* Disable OSD1 */ 330 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 330 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 331 331 writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0, 332 332 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); 333 333 else
+32 -32
drivers/gpu/drm/meson/meson_vclk.c
··· 242 242 unsigned int val; 243 243 244 244 /* Setup PLL to output 1.485GHz */ 245 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { 245 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { 246 246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); 247 247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); 248 248 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); ··· 254 254 /* Poll for lock bit */ 255 255 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, 256 256 (val & HDMI_PLL_LOCK), 10, 0); 257 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 258 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) { 257 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 258 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { 259 259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); 260 260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); 261 261 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844); ··· 272 272 /* Poll for lock bit */ 273 273 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, 274 274 (val & HDMI_PLL_LOCK), 10, 0); 275 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 275 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 276 276 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); 277 277 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000); 278 278 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); ··· 300 300 VCLK2_DIV_MASK, (55 - 1)); 301 301 302 302 /* select vid_pll for vclk2 */ 303 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 303 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 304 304 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, 305 305 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); 306 306 else ··· 455 455 { 456 456 unsigned int val; 457 457 458 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { 458 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { 459 459 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m); 460 460 if (frac) 461 461 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, ··· 475 475 /* Poll for lock bit */ 476 476 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, 477 477 val, (val & HDMI_PLL_LOCK), 10, 0); 478 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 479 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) { 478 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 479 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { 480 480 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m); 481 481 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); 482 482 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); ··· 493 493 /* Poll for lock bit */ 494 494 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, 495 495 (val & HDMI_PLL_LOCK), 10, 0); 496 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 496 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 497 497 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m); 498 498 499 499 /* Enable and reset */ ··· 545 545 } while(1); 546 546 } 547 547 548 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 548 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) 549 549 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, 550 550 3 << 16, pll_od_to_reg(od1) << 16); 551 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 552 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 551 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 552 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) 553 553 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, 554 554 3 << 21, pll_od_to_reg(od1) << 21); 555 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 555 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 556 556 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, 557 557 3 << 16, pll_od_to_reg(od1) << 16); 558 558 559 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 559 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) 560 560 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, 561 561 3 << 22, pll_od_to_reg(od2) << 22); 562 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 563 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 562 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 563 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) 564 564 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, 565 565 3 << 23, pll_od_to_reg(od2) << 23); 566 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 566 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 567 567 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, 568 568 3 << 18, pll_od_to_reg(od2) << 18); 569 569 570 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 570 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) 571 571 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, 572 572 3 << 18, pll_od_to_reg(od3) << 18); 573 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 574 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 573 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 574 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) 575 575 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, 576 576 3 << 19, pll_od_to_reg(od3) << 19); 577 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 577 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 578 578 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, 579 579 3 << 20, pll_od_to_reg(od3) << 20); 580 580 } ··· 585 585 unsigned int pll_freq) 586 586 { 587 587 /* The GXBB PLL has a /2 pre-multiplier */ 588 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 588 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) 589 589 pll_freq /= 2; 590 590 591 591 return pll_freq / XTAL_FREQ; ··· 605 605 unsigned int frac; 606 606 607 607 /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */ 608 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { 608 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { 609 609 frac_max = HDMI_FRAC_MAX_GXBB; 610 610 parent_freq *= 2; 611 611 } 612 612 613 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 613 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 614 614 frac_max = HDMI_FRAC_MAX_G12A; 615 615 616 616 /* We can have a perfect match !*/ ··· 631 631 unsigned int m, 632 632 unsigned int frac) 633 633 { 634 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { 634 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { 635 635 /* Empiric supported min/max dividers */ 636 636 if (m < 53 || m > 123) 637 637 return false; 638 638 if (frac >= HDMI_FRAC_MAX_GXBB) 639 639 return false; 640 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 641 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu") || 642 - meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 640 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 641 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) || 642 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 643 643 /* Empiric supported min/max dividers */ 644 644 if (m < 106 || m > 247) 645 645 return false; ··· 759 759 /* Set HDMI PLL rate */ 760 760 if (!od1 && !od2 && !od3) { 761 761 meson_hdmi_pll_generic_set(priv, pll_base_freq); 762 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { 762 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { 763 763 switch (pll_base_freq) { 764 764 case 2970000: 765 765 m = 0x3d; ··· 776 776 } 777 777 778 778 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); 779 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 780 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) { 779 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 780 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { 781 781 switch (pll_base_freq) { 782 782 case 2970000: 783 783 m = 0x7b; ··· 794 794 } 795 795 796 796 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); 797 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 797 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 798 798 switch (pll_base_freq) { 799 799 case 2970000: 800 800 m = 0x7b;
+1 -1
drivers/gpu/drm/meson/meson_venc.c
··· 1759 1759 void meson_venc_init(struct meson_drm *priv) 1760 1760 { 1761 1761 /* Disable CVBS VDAC */ 1762 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 1762 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 1763 1763 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); 1764 1764 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); 1765 1765 } else {
+5 -5
drivers/gpu/drm/meson/meson_venc_cvbs.c
··· 155 155 struct meson_drm *priv = meson_venc_cvbs->priv; 156 156 157 157 /* Disable CVBS VDAC */ 158 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 158 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 159 159 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); 160 160 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); 161 161 } else { ··· 174 174 writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, 175 175 priv->io_base + _REG(VENC_VDAC_DACSEL0)); 176 176 177 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { 177 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { 178 178 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1); 179 179 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); 180 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 181 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) { 180 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 181 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { 182 182 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001); 183 183 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); 184 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 184 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 185 185 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); 186 186 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); 187 187 }
+5 -5
drivers/gpu/drm/meson/meson_viu.c
··· 353 353 priv->io_base + _REG(VIU_OSD2_CTRL_STAT)); 354 354 355 355 /* On GXL/GXM, Use the 10bit HDR conversion matrix */ 356 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 357 - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 356 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || 357 + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) 358 358 meson_viu_load_matrix(priv); 359 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 359 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 360 360 meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff, 361 361 true); 362 362 ··· 367 367 VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */ 368 368 VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */ 369 369 370 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 370 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 371 371 reg |= meson_viu_osd_burst_length_reg(32); 372 372 else 373 373 reg |= meson_viu_osd_burst_length_reg(64); ··· 394 394 writel_relaxed(0x00FF00C0, 395 395 priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE)); 396 396 397 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 397 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 398 398 writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) | 399 399 VIU_OSD_BLEND_REORDER(1, 0) | 400 400 VIU_OSD_BLEND_REORDER(2, 0) |
+5 -5
drivers/gpu/drm/meson/meson_vpp.c
··· 91 91 void meson_vpp_init(struct meson_drm *priv) 92 92 { 93 93 /* set dummy data default YUV black */ 94 - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 94 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) 95 95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); 96 - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) { 96 + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { 97 97 writel_bits_relaxed(0xff << 16, 0xff << 16, 98 98 priv->io_base + _REG(VIU_MISC_CTRL1)); 99 99 writel_relaxed(VPP_PPS_DUMMY_DATA_MODE, 100 100 priv->io_base + _REG(VPP_DOLBY_CTRL)); 101 101 writel_relaxed(0x1020080, 102 102 priv->io_base + _REG(VPP_DUMMY_DATA1)); 103 - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 103 + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 104 104 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); 105 105 106 106 /* Initialize vpu fifo control registers */ 107 - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 107 + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) 108 108 writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, 109 109 priv->io_base + _REG(VPP_OFIFO_SIZE)); 110 110 else ··· 113 113 writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4), 114 114 priv->io_base + _REG(VPP_HOLD_LINES)); 115 115 116 - if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 116 + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 117 117 /* Turn off preblend */ 118 118 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, 119 119 priv->io_base + _REG(VPP_MISC));