Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

soc/tegra: pmc: Add Tegra264 support

The PMC block on Tegra264 has undergone a few small changes since it's
Tegra234 predecessor. Match on the new compatible string to select the
updated SoC-specific data.

Link: https://lore.kernel.org/r/20250506133118.1011777-8-thierry.reding@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>

+121
+121
drivers/soc/tegra/pmc.c
··· 4248 4248 .has_single_mmio_aperture = false, 4249 4249 }; 4250 4250 4251 + static const struct tegra_pmc_regs tegra264_pmc_regs = { 4252 + .scratch0 = 0x684, 4253 + .rst_status = 0x4, 4254 + .rst_source_shift = 0x2, 4255 + .rst_source_mask = 0x1fc, 4256 + .rst_level_shift = 0x0, 4257 + .rst_level_mask = 0x3, 4258 + }; 4259 + 4260 + static const char * const tegra264_reset_sources[] = { 4261 + "SYS_RESET_N", /* 0x0 */ 4262 + "CSDC_RTC_XTAL", 4263 + "VREFRO_POWER_BAD", 4264 + "SCPM_SOC_XTAL", 4265 + "SCPM_RTC_XTAL", 4266 + "FMON_32K", 4267 + "FMON_OSC", 4268 + "POD_RTC", 4269 + "POD_IO", /* 0x8 */ 4270 + "POD_PLUS_IO_SPLL", 4271 + "POD_PLUS_SOC", 4272 + "VMON_PLUS_UV", 4273 + "VMON_PLUS_OV", 4274 + "FUSECRC_FAULT", 4275 + "OSC_FAULT", 4276 + "BPMP_BOOT_FAULT", 4277 + "SCPM_BPMP_CORE_CLK", /* 0x10 */ 4278 + "SCPM_PSC_SE_CLK", 4279 + "VMON_SOC_MIN", 4280 + "VMON_SOC_MAX", 4281 + "VMON_MSS_MIN", 4282 + "VMON_MSS_MAX", 4283 + "POD_PLUS_IO_VMON", 4284 + "NVJTAG_SEL_MONITOR", 4285 + "NV_THERM_FAULT", /* 0x18 */ 4286 + "FSI_THERM_FAULT", 4287 + "PSC_SW", 4288 + "SCPM_OESP_SE_CLK", 4289 + "SCPM_SB_SE_CLK", 4290 + "POD_CPU", 4291 + "POD_GPU", 4292 + "DCLS_GPU", 4293 + "POD_MSS", /* 0x20 */ 4294 + "FMON_FSI", 4295 + "POD_FSI", 4296 + "VMON_FSI_MIN", 4297 + "VMON_FSI_MAX", 4298 + "VMON_CPU0_MIN", 4299 + "VMON_CPU0_MAX", 4300 + "BPMP_FMON", 4301 + "AO_WDT_POR", /* 0x28 */ 4302 + "BPMP_WDT_POR", 4303 + "AO_TKE_WDT_POR", 4304 + "RCE0_WDT_POR", 4305 + "RCE1_WDT_POR", 4306 + "DCE_WDT_POR", 4307 + "FSI_R5_WDT_POR", 4308 + "FSI_R52_0_WDT_POR", 4309 + "FSI_R52_1_WDT_POR", /* 0x30 */ 4310 + "FSI_R52_2_WDT_POR", 4311 + "FSI_R52_3_WDT_POR", 4312 + "TOP_0_WDT_POR", 4313 + "TOP_1_WDT_POR", 4314 + "TOP_2_WDT_POR", 4315 + "APE_C0_WDT_POR", 4316 + "APE_C1_WDT_POR", 4317 + "GPU_TKE_WDT_POR", /* 0x38 */ 4318 + "PSC_WDT_POR", 4319 + "OESP_WDT_POR", 4320 + "SB_WDT_POR", 4321 + "SW_MAIN", 4322 + "L0L1_RST_OUT_N", 4323 + "FSI_HSM", 4324 + "CSITE_SW", 4325 + "AO_WDT_DBG", /* 0x40 */ 4326 + "BPMP_WDT_DBG", 4327 + "AO_TKE_WDT_DBG", 4328 + "RCE0_WDT_DBG", 4329 + "RCE1_WDT_DBG", 4330 + "DCE_WDT_DBG", 4331 + "FSI_R5_WDT_DBG", 4332 + "FSI_R52_0_WDT_DBG", 4333 + "FSI_R52_1_WDT_DBG", /* 0x48 */ 4334 + "FSI_R52_2_WDT_DBG", 4335 + "FSI_R52_3_WDT_DBG", 4336 + "TOP_0_WDT_DBG", 4337 + "TOP_1_WDT_DBG", 4338 + "TOP_2_WDT_DBG", 4339 + "APE_C0_WDT_DBG", 4340 + "APE_C1_WDT_DBG", 4341 + "PSC_WDT_DBG", /* 0x50 */ 4342 + "OESP_WDT_DBG", 4343 + "SB_WDT_DBG", 4344 + "TSC_0_WDT_DBG", 4345 + "TSC_1_WDT_DBG", 4346 + "L2_RST_OUT_N", 4347 + "SC7" 4348 + }; 4349 + 4350 + static const struct tegra_wake_event tegra264_wake_events[] = { 4351 + }; 4352 + 4353 + static const struct tegra_pmc_soc tegra264_pmc_soc = { 4354 + .has_impl_33v_pwr = true, 4355 + .regs = &tegra264_pmc_regs, 4356 + .init = tegra186_pmc_init, 4357 + .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4358 + .set_wake_filters = tegra186_pmc_set_wake_filters, 4359 + .irq_set_wake = tegra186_pmc_irq_set_wake, 4360 + .irq_set_type = tegra186_pmc_irq_set_type, 4361 + .reset_sources = tegra264_reset_sources, 4362 + .num_reset_sources = ARRAY_SIZE(tegra264_reset_sources), 4363 + .reset_levels = tegra186_reset_levels, 4364 + .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4365 + .wake_events = tegra264_wake_events, 4366 + .num_wake_events = ARRAY_SIZE(tegra264_wake_events), 4367 + .max_wake_events = 128, 4368 + .max_wake_vectors = 4, 4369 + }; 4370 + 4251 4371 static const struct of_device_id tegra_pmc_match[] = { 4372 + { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, 4252 4373 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4253 4374 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4254 4375 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },