tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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MIPS: BCM63xx: Add support for second uart.

The BCm63xx SOC has two uarts. Some boards use the second one for
bluetooth. This patch changes platform device registration code to
handle this. Changes to the UART driver were already merged in
6a2c7eabfd09ca7986bf96b8958a87ca041a19d8.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
To: linux-mips@linux-mips.org
Cc: Maxime Bizon <mbizon@freebox.fr>
Patchwork: http://patchwork.linux-mips.org/patch/900/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Maxime Bizon and committed by
Ralf Baechle 524ef29c 97befcf4

+102 -19
unified split
+24 -3
arch/mips/bcm63xx/boards/board_bcm963xx.c
··· 18 18 #include <asm/addrspace.h> 19 19 #include <bcm63xx_board.h> 20 20 #include <bcm63xx_cpu.h> 21 + #include <bcm63xx_dev_uart.h> 21 22 #include <bcm63xx_regs.h> 22 23 #include <bcm63xx_io.h> 23 24 #include <bcm63xx_dev_pci.h> ··· 41 40 .name = "96338GW", 42 41 .expected_cpu_id = 0x6338, 43 42 43 + .has_uart0 = 1, 44 44 .has_enet0 = 1, 45 45 .enet0 = { 46 46 .force_speed_100 = 1, ··· 84 82 .name = "96338W", 85 83 .expected_cpu_id = 0x6338, 86 84 85 + .has_uart0 = 1, 87 86 .has_enet0 = 1, 88 87 .enet0 = { 89 88 .force_speed_100 = 1, ··· 129 126 static struct board_info __initdata board_96345gw2 = { 130 127 .name = "96345GW2", 131 128 .expected_cpu_id = 0x6345, 129 + 130 + .has_uart0 = 1, 132 131 }; 133 132 #endif 134 133 ··· 142 137 .name = "96348R", 143 138 .expected_cpu_id = 0x6348, 144 139 140 + .has_uart0 = 1, 145 141 .has_enet0 = 1, 146 142 .has_pci = 1, 147 143 ··· 186 180 .name = "96348GW-10", 187 181 .expected_cpu_id = 0x6348, 188 182 183 + .has_uart0 = 1, 189 184 .has_enet0 = 1, 190 185 .has_enet1 = 1, 191 186 .has_pci = 1, ··· 246 239 .name = "96348GW-11", 247 240 .expected_cpu_id = 0x6348, 248 241 242 + .has_uart0 = 1, 249 243 .has_enet0 = 1, 250 244 .has_enet1 = 1, 251 245 .has_pci = 1, ··· 300 292 .name = "96348GW", 301 293 .expected_cpu_id = 0x6348, 302 294 295 + .has_uart0 = 1, 303 296 .has_enet0 = 1, 304 297 .has_enet1 = 1, 305 298 .has_pci = 1, ··· 358 349 .name = "F@ST2404", 359 350 .expected_cpu_id = 0x6348, 360 351 361 - .has_enet0 = 1, 362 - .has_enet1 = 1, 363 - .has_pci = 1, 352 + .has_uart0 = 1, 353 + .has_enet0 = 1, 354 + .has_enet1 = 1, 355 + .has_pci = 1, 364 356 365 357 .enet0 = { 366 358 .has_phy = 1, ··· 401 391 .name = "DV201AMR", 402 392 .expected_cpu_id = 0x6348, 403 393 394 + .has_uart0 = 1, 404 395 .has_pci = 1, 405 396 .has_ohci0 = 1, 406 397 ··· 421 410 .name = "96348GW-A", 422 411 .expected_cpu_id = 0x6348, 423 412 413 + .has_uart0 = 1, 424 414 .has_enet0 = 1, 425 415 .has_enet1 = 1, 426 416 .has_pci = 1, ··· 447 435 .name = "96358VW", 448 436 .expected_cpu_id = 0x6358, 449 437 438 + .has_uart0 = 1, 450 439 .has_enet0 = 1, 451 440 .has_enet1 = 1, 452 441 .has_pci = 1, ··· 499 486 .name = "96358VW2", 500 487 .expected_cpu_id = 0x6358, 501 488 489 + .has_uart0 = 1, 502 490 .has_enet0 = 1, 503 491 .has_enet1 = 1, 504 492 .has_pci = 1, ··· 547 533 .name = "AGPF-S0", 548 534 .expected_cpu_id = 0x6358, 549 535 536 + .has_uart0 = 1, 550 537 .has_enet0 = 1, 551 538 .has_enet1 = 1, 552 539 .has_pci = 1, ··· 848 833 int __init board_register_devices(void) 849 834 { 850 835 u32 val; 836 + 837 + if (board.has_uart0) 838 + bcm63xx_uart_register(0); 839 + 840 + if (board.has_uart1) 841 + bcm63xx_uart_register(1); 851 842 852 843 if (board.has_pccard) 853 844 bcm63xx_pcmcia_register();
+5
arch/mips/bcm63xx/cpu.c
··· 36 36 [RSET_TIMER] = BCM_6338_TIMER_BASE, 37 37 [RSET_WDT] = BCM_6338_WDT_BASE, 38 38 [RSET_UART0] = BCM_6338_UART0_BASE, 39 + [RSET_UART1] = BCM_6338_UART1_BASE, 39 40 [RSET_GPIO] = BCM_6338_GPIO_BASE, 40 41 [RSET_SPI] = BCM_6338_SPI_BASE, 41 42 [RSET_OHCI0] = BCM_6338_OHCI0_BASE, ··· 73 72 [RSET_TIMER] = BCM_6345_TIMER_BASE, 74 73 [RSET_WDT] = BCM_6345_WDT_BASE, 75 74 [RSET_UART0] = BCM_6345_UART0_BASE, 75 + [RSET_UART1] = BCM_6345_UART1_BASE, 76 76 [RSET_GPIO] = BCM_6345_GPIO_BASE, 77 77 [RSET_SPI] = BCM_6345_SPI_BASE, 78 78 [RSET_UDC0] = BCM_6345_UDC0_BASE, ··· 111 109 [RSET_TIMER] = BCM_6348_TIMER_BASE, 112 110 [RSET_WDT] = BCM_6348_WDT_BASE, 113 111 [RSET_UART0] = BCM_6348_UART0_BASE, 112 + [RSET_UART1] = BCM_6348_UART1_BASE, 114 113 [RSET_GPIO] = BCM_6348_GPIO_BASE, 115 114 [RSET_SPI] = BCM_6348_SPI_BASE, 116 115 [RSET_OHCI0] = BCM_6348_OHCI0_BASE, ··· 153 150 [RSET_TIMER] = BCM_6358_TIMER_BASE, 154 151 [RSET_WDT] = BCM_6358_WDT_BASE, 155 152 [RSET_UART0] = BCM_6358_UART0_BASE, 153 + [RSET_UART1] = BCM_6358_UART1_BASE, 156 154 [RSET_GPIO] = BCM_6358_GPIO_BASE, 157 155 [RSET_SPI] = BCM_6358_SPI_BASE, 158 156 [RSET_OHCI0] = BCM_6358_OHCI0_BASE, ··· 174 170 static const int bcm96358_irqs[] = { 175 171 [IRQ_TIMER] = BCM_6358_TIMER_IRQ, 176 172 [IRQ_UART0] = BCM_6358_UART0_IRQ, 173 + [IRQ_UART1] = BCM_6358_UART1_IRQ, 177 174 [IRQ_DSL] = BCM_6358_DSL_IRQ, 178 175 [IRQ_ENET0] = BCM_6358_ENET0_IRQ, 179 176 [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
+50 -16
arch/mips/bcm63xx/dev-uart.c
··· 11 11 #include <linux/platform_device.h> 12 12 #include <bcm63xx_cpu.h> 13 13 14 - static struct resource uart_resources[] = { 14 + static struct resource uart0_resources[] = { 15 15 { 16 - .start = -1, /* filled at runtime */ 17 - .end = -1, /* filled at runtime */ 16 + /* start & end filled at runtime */ 18 17 .flags = IORESOURCE_MEM, 19 18 }, 20 19 { 21 - .start = -1, /* filled at runtime */ 20 + /* start filled at runtime */ 22 21 .flags = IORESOURCE_IRQ, 23 22 }, 24 23 }; 25 24 26 - static struct platform_device bcm63xx_uart_device = { 27 - .name = "bcm63xx_uart", 28 - .id = 0, 29 - .num_resources = ARRAY_SIZE(uart_resources), 30 - .resource = uart_resources, 25 + static struct resource uart1_resources[] = { 26 + { 27 + /* start & end filled at runtime */ 28 + .flags = IORESOURCE_MEM, 29 + }, 30 + { 31 + /* start filled at runtime */ 32 + .flags = IORESOURCE_IRQ, 33 + }, 31 34 }; 32 35 33 - int __init bcm63xx_uart_register(void) 36 + static struct platform_device bcm63xx_uart_devices[] = { 37 + { 38 + .name = "bcm63xx_uart", 39 + .id = 0, 40 + .num_resources = ARRAY_SIZE(uart0_resources), 41 + .resource = uart0_resources, 42 + }, 43 + 44 + { 45 + .name = "bcm63xx_uart", 46 + .id = 1, 47 + .num_resources = ARRAY_SIZE(uart1_resources), 48 + .resource = uart1_resources, 49 + } 50 + }; 51 + 52 + int __init bcm63xx_uart_register(unsigned int id) 34 53 { 35 - uart_resources[0].start = bcm63xx_regset_address(RSET_UART0); 36 - uart_resources[0].end = uart_resources[0].start; 37 - uart_resources[0].end += RSET_UART_SIZE - 1; 38 - uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); 39 - return platform_device_register(&bcm63xx_uart_device); 54 + if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) 55 + return -ENODEV; 56 + 57 + if (id == 1 && !BCMCPU_IS_6358()) 58 + return -ENODEV; 59 + 60 + if (id == 0) { 61 + uart0_resources[0].start = bcm63xx_regset_address(RSET_UART0); 62 + uart0_resources[0].end = uart0_resources[0].start + 63 + RSET_UART_SIZE - 1; 64 + uart0_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); 65 + } 66 + 67 + if (id == 1) { 68 + uart1_resources[0].start = bcm63xx_regset_address(RSET_UART1); 69 + uart1_resources[0].end = uart1_resources[0].start + 70 + RSET_UART_SIZE - 1; 71 + uart1_resources[1].start = bcm63xx_get_irq_number(IRQ_UART1); 72 + } 73 + 74 + return platform_device_register(&bcm63xx_uart_devices[id]); 40 75 } 41 - arch_initcall(bcm63xx_uart_register);
+15
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
··· 85 85 RSET_TIMER, 86 86 RSET_WDT, 87 87 RSET_UART0, 88 + RSET_UART1, 88 89 RSET_GPIO, 89 90 RSET_SPI, 90 91 RSET_UDC0, ··· 124 123 #define BCM_6338_TIMER_BASE (0xfffe0200) 125 124 #define BCM_6338_WDT_BASE (0xfffe021c) 126 125 #define BCM_6338_UART0_BASE (0xfffe0300) 126 + #define BCM_6338_UART1_BASE (0xdeadbeef) 127 127 #define BCM_6338_GPIO_BASE (0xfffe0400) 128 128 #define BCM_6338_SPI_BASE (0xfffe0c00) 129 129 #define BCM_6338_UDC0_BASE (0xdeadbeef) ··· 155 153 #define BCM_6345_TIMER_BASE (0xfffe0200) 156 154 #define BCM_6345_WDT_BASE (0xfffe021c) 157 155 #define BCM_6345_UART0_BASE (0xfffe0300) 156 + #define BCM_6345_UART1_BASE (0xdeadbeef) 158 157 #define BCM_6345_GPIO_BASE (0xfffe0400) 159 158 #define BCM_6345_SPI_BASE (0xdeadbeef) 160 159 #define BCM_6345_UDC0_BASE (0xdeadbeef) ··· 185 182 #define BCM_6348_TIMER_BASE (0xfffe0200) 186 183 #define BCM_6348_WDT_BASE (0xfffe021c) 187 184 #define BCM_6348_UART0_BASE (0xfffe0300) 185 + #define BCM_6348_UART1_BASE (0xdeadbeef) 188 186 #define BCM_6348_GPIO_BASE (0xfffe0400) 189 187 #define BCM_6348_SPI_BASE (0xfffe0c00) 190 188 #define BCM_6348_UDC0_BASE (0xfffe1000) ··· 212 208 #define BCM_6358_TIMER_BASE (0xfffe0040) 213 209 #define BCM_6358_WDT_BASE (0xfffe005c) 214 210 #define BCM_6358_UART0_BASE (0xfffe0100) 211 + #define BCM_6358_UART1_BASE (0xfffe0120) 215 212 #define BCM_6358_GPIO_BASE (0xfffe0080) 216 213 #define BCM_6358_SPI_BASE (0xdeadbeef) 217 214 #define BCM_6358_UDC0_BASE (0xfffe0800) ··· 251 246 return BCM_6338_WDT_BASE; 252 247 case RSET_UART0: 253 248 return BCM_6338_UART0_BASE; 249 + case RSET_UART1: 250 + return BCM_6338_UART1_BASE; 254 251 case RSET_GPIO: 255 252 return BCM_6338_GPIO_BASE; 256 253 case RSET_SPI: ··· 299 292 return BCM_6345_WDT_BASE; 300 293 case RSET_UART0: 301 294 return BCM_6345_UART0_BASE; 295 + case RSET_UART1: 296 + return BCM_6345_UART1_BASE; 302 297 case RSET_GPIO: 303 298 return BCM_6345_GPIO_BASE; 304 299 case RSET_SPI: ··· 347 338 return BCM_6348_WDT_BASE; 348 339 case RSET_UART0: 349 340 return BCM_6348_UART0_BASE; 341 + case RSET_UART1: 342 + return BCM_6348_UART1_BASE; 350 343 case RSET_GPIO: 351 344 return BCM_6348_GPIO_BASE; 352 345 case RSET_SPI: ··· 395 384 return BCM_6358_WDT_BASE; 396 385 case RSET_UART0: 397 386 return BCM_6358_UART0_BASE; 387 + case RSET_UART1: 388 + return BCM_6358_UART1_BASE; 398 389 case RSET_GPIO: 399 390 return BCM_6358_GPIO_BASE; 400 391 case RSET_SPI: ··· 442 429 enum bcm63xx_irq { 443 430 IRQ_TIMER = 0, 444 431 IRQ_UART0, 432 + IRQ_UART1, 445 433 IRQ_DSL, 446 434 IRQ_ENET0, 447 435 IRQ_ENET1, ··· 524 510 */ 525 511 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 526 512 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 513 + #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 527 514 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 528 515 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 529 516 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
+6
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
··· 1 + #ifndef BCM63XX_DEV_UART_H_ 2 + #define BCM63XX_DEV_UART_H_ 3 + 4 + int bcm63xx_uart_register(unsigned int id); 5 + 6 + #endif /* BCM63XX_DEV_UART_H_ */
+2
arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
··· 45 45 unsigned int has_ohci0:1; 46 46 unsigned int has_ehci0:1; 47 47 unsigned int has_dsp:1; 48 + unsigned int has_uart0:1; 49 + unsigned int has_uart1:1; 48 50 49 51 /* ethernet config */ 50 52 struct bcm63xx_enet_platform_data enet0;