tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'sh/pci-express-integration'
+85
-11
+31
-9
arch/sh/drivers/pci/pcie-sh7786.c
+31
-9
arch/sh/drivers/pci/pcie-sh7786.c
···
51
51
.name = "PCIe0 MEM 2",
52
52
.start = 0xfe100000,
53
53
.end = 0xfe100000 + SZ_1M - 1,
54
+
.flags = IORESOURCE_MEM,
54
55
},
55
56
};
56
57
···
75
74
.name = "PCIe1 MEM 2",
76
75
.start = 0xfe300000,
77
76
.end = 0xfe300000 + SZ_1M - 1,
77
+
.flags = IORESOURCE_MEM,
78
78
},
79
79
};
80
80
···
84
82
.name = "PCIe2 IO",
85
83
.start = 0xfc800000,
86
84
.end = 0xfc800000 + SZ_4M - 1,
85
+
.flags = IORESOURCE_IO,
87
86
}, {
88
87
.name = "PCIe2 MEM 0",
89
88
.start = 0x80000000,
···
99
96
.name = "PCIe2 MEM 2",
100
97
.start = 0xfcd00000,
101
98
.end = 0xfcd00000 + SZ_1M - 1,
99
+
.flags = IORESOURCE_MEM,
102
100
},
103
101
};
104
102
···
208
204
return -ETIMEDOUT;
209
205
}
210
206
207
+
static void pcie_reset(struct sh7786_pcie_port *port)
208
+
{
209
+
struct pci_channel *chan = port->hose;
210
+
211
+
pci_write_reg(chan, 1, SH4A_PCIESRSTR);
212
+
pci_write_reg(chan, 0, SH4A_PCIETCTLR);
213
+
pci_write_reg(chan, 0, SH4A_PCIESRSTR);
214
+
pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
215
+
}
216
+
211
217
static int pcie_init(struct sh7786_pcie_port *port)
212
218
{
213
219
struct pci_channel *chan = port->hose;
214
220
unsigned int data;
215
221
phys_addr_t memphys;
216
222
size_t memsize;
217
-
int ret, i;
223
+
int ret, i, win;
218
224
219
225
/* Begin initialization */
220
-
pci_write_reg(chan, 0, SH4A_PCIETCTLR);
226
+
pcie_reset(port);
221
227
222
228
/* Initialize as type1. */
223
229
data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
···
341
327
printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
342
328
port->index, (data >> 20) & 0x3f);
343
329
344
-
345
-
for (i = 0; i < chan->nr_resources; i++) {
330
+
for (i = win = 0; i < chan->nr_resources; i++) {
346
331
struct resource *res = chan->resources + i;
347
332
resource_size_t size;
348
333
u32 enable_mask;
349
334
350
-
pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
335
+
/*
336
+
* We can't use the 32-bit mode windows in legacy 29-bit
337
+
* mode, so just skip them entirely.
338
+
*/
339
+
if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
340
+
continue;
341
+
342
+
pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
351
343
352
344
size = resource_size(res);
353
345
···
362
342
* keeps things pretty simple.
363
343
*/
364
344
__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
365
-
chan->reg_base + SH4A_PCIEPAMR(i));
345
+
chan->reg_base + SH4A_PCIEPAMR(win));
366
346
367
-
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
368
-
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
347
+
pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
348
+
pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
369
349
370
350
enable_mask = MASK_PARE;
371
351
if (res->flags & IORESOURCE_IO)
372
352
enable_mask |= MASK_SPC;
373
353
374
-
pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
354
+
pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
355
+
356
+
win++;
375
357
}
376
358
377
359
return 0;
+54
-2
arch/sh/drivers/pci/pcie-sh7786.h
+54
-2
arch/sh/drivers/pci/pcie-sh7786.h
···
55
55
#define BITS_ERRRCV (0) /* 0 ERRRCV 0 */
56
56
#define MASK_ERRRCV (1<<BITS_ERRRCV)
57
57
58
+
/* PCIEENBLR */
59
+
#define SH4A_PCIEENBLR (0x000008) /* R/W - 0x0000 0001 32 */
60
+
58
61
/* PCIEECR */
59
-
#define SH4A_PCIEECR (0x000008) /* R/W - 0x0000 0000 32 */
62
+
#define SH4A_PCIEECR (0x00000C) /* R/W - 0x0000 0000 32 */
60
63
#define BITS_ENBL (0) /* 0 ENBL 0 R/W */
61
64
#define MASK_ENBL (1<<BITS_ENBL)
62
65
···
116
113
#define BITS_MDATA (0)
117
114
#define MASK_MDATA (0xffffffff<<BITS_MDATA)
118
115
116
+
/* PCIEUNLOCKCR */
117
+
#define SH4A_PCIEUNLOCKCR (0x000048) /* R/W - 0x0000 0000 32 */
118
+
119
+
/* PCIEIDR */
120
+
#define SH4A_PCIEIDR (0x000060) /* R/W - 0x0101 1101 32 */
121
+
122
+
/* PCIEDBGCTLR */
123
+
#define SH4A_PCIEDBGCTLR (0x000100) /* R/W - 0x0000 0000 32 */
124
+
125
+
/* PCIEINTXR */
126
+
#define SH4A_PCIEINTXR (0x004000) /* R/W - 0x0000 0000 32 */
127
+
128
+
/* PCIERMSGR */
129
+
#define SH4A_PCIERMSGR (0x004010) /* R/W - 0x0000 0000 32 */
130
+
131
+
/* PCIERSTR */
132
+
#define SH4A_PCIERSTR(x) (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
133
+
134
+
/* PCIESRSTR */
135
+
#define SH4A_PCIESRSTR (0x008040) /* R/W - 0x0000 0000 32 */
136
+
119
137
/* PCIEPHYCTLR */
120
138
#define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
121
139
#define BITS_CKE (0)
···
144
120
145
121
/* PCIERMSGIER */
146
122
#define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */
123
+
124
+
/* PCIEPHYCTLR */
125
+
#define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
147
126
148
127
/* PCIEPHYADRR */
149
128
#define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */
···
179
152
#define MASK_CFINT (1<<BITS_CFINT)
180
153
181
154
/* PCIETSTR */
182
-
#define SH4A_PCIETSTR (0x020004) /* R/W R/W 0x0000 0000 32 */
155
+
#define SH4A_PCIETSTR (0x020004) /* R 0x0000 0000 32 */
183
156
184
157
/* PCIEINTR */
185
158
#define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */
···
263
236
#define BITS_INTPM (8)
264
237
#define MASK_INTPM (1<<BITS_INTPM)
265
238
239
+
/* PCIEEH0R */
240
+
#define SH4A_PCIEEHR(x) (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
241
+
266
242
/* PCIEAIR */
267
243
#define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */
268
244
···
274
244
275
245
/* PCIEERRFR */ // Rev1.18
276
246
#define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18
247
+
248
+
/* PCIEERRFER */
249
+
#define SH4A_PCIEERRFER (0x020024) /* R/W R/W 0x0000 0000 32 */
250
+
251
+
/* PCIEERRFR2 */
252
+
#define SH4A_PCIEERRFR2 (0x020028) /* R/W R/W 0x0000 0000 32 */
253
+
254
+
/* PCIEMSIR */
255
+
#define SH4A_PCIEMSIR (0x020040) /* R/W - 0x0000 0000 32 */
256
+
257
+
/* PCIEMSIFR */
258
+
#define SH4A_PCIEMSIFR (0x020044) /* R/W R/W 0x0000 0000 32 */
259
+
260
+
/* PCIEPWRCTLR */
261
+
#define SH4A_PCIEPWRCTLR (0x020100) /* R/W - 0x0000 0000 32 */
262
+
263
+
/* PCIEPCCTLR */
264
+
#define SH4A_PCIEPCCTLR (0x020180) /* R/W - 0x0000 0000 32 */
265
+
277
266
// Rev1.18
278
267
/* PCIELAR0 */
279
268
#define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */
···
401
352
#define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */
402
353
#define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */
403
354
#define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */
355
+
#define SH4A_PCIEDMCHSR0 (0x02112C) /* R/W - 0x0000 0000 32 */
404
356
#define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */
405
357
#define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */
406
358
#define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */
···
413
363
#define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */
414
364
#define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */
415
365
#define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */
366
+
#define SH4A_PCIEDMCHSR1 (0x02116C) /* R/W - 0x0000 0000 32 */
416
367
#define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */
417
368
#define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */
418
369
#define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */
···
436
385
#define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */
437
386
#define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */
438
387
#define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */
388
+
#define SH4A_PCIEDMCHSR3 (0x0211EC) /* R/W R/W 0x0000 0000 32 */
439
389
#define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */
440
390
#define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */
441
391
#define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */