tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'usb-serial-4.2-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial into usb-linus

Johan writes:

USB-serial fixes for v4.2-rc2

Here's an idr memory-leak fix and a couple of new device ids.

Included is also a build fix for mos7720 on the mn10300 architecture,
which has a register with the same name as one of the driver defines.

Signed-off-by: Johan Hovold <johan@kernel.org>

Greg Kroah-Hartman 51f007e1 d4669bb1

+141 -115
+1
drivers/usb/serial/cp210x.c
··· 187 187 { USB_DEVICE(0x1FB9, 0x0602) }, /* Lake Shore Model 648 Magnet Power Supply */ 188 188 { USB_DEVICE(0x1FB9, 0x0700) }, /* Lake Shore Model 737 VSM Controller */ 189 189 { USB_DEVICE(0x1FB9, 0x0701) }, /* Lake Shore Model 776 Hall Matrix */ 190 + { USB_DEVICE(0x2626, 0xEA60) }, /* Aruba Networks 7xxx USB Serial Console */ 190 191 { USB_DEVICE(0x3195, 0xF190) }, /* Link Instruments MSO-19 */ 191 192 { USB_DEVICE(0x3195, 0xF280) }, /* Link Instruments MSO-28 */ 192 193 { USB_DEVICE(0x3195, 0xF281) }, /* Link Instruments MSO-28 */
+138 -115
drivers/usb/serial/mos7720.c
··· 121 121 static const unsigned int dummy; /* for clarity in register access fns */ 122 122 123 123 enum mos_regs { 124 - THR, /* serial port regs */ 125 - RHR, 126 - IER, 127 - FCR, 128 - ISR, 129 - LCR, 130 - MCR, 131 - LSR, 132 - MSR, 133 - SPR, 134 - DLL, 135 - DLM, 136 - DPR, /* parallel port regs */ 137 - DSR, 138 - DCR, 139 - ECR, 140 - SP1_REG, /* device control regs */ 141 - SP2_REG, /* serial port 2 (7720 only) */ 142 - PP_REG, 143 - SP_CONTROL_REG, 124 + MOS7720_THR, /* serial port regs */ 125 + MOS7720_RHR, 126 + MOS7720_IER, 127 + MOS7720_FCR, 128 + MOS7720_ISR, 129 + MOS7720_LCR, 130 + MOS7720_MCR, 131 + MOS7720_LSR, 132 + MOS7720_MSR, 133 + MOS7720_SPR, 134 + MOS7720_DLL, 135 + MOS7720_DLM, 136 + MOS7720_DPR, /* parallel port regs */ 137 + MOS7720_DSR, 138 + MOS7720_DCR, 139 + MOS7720_ECR, 140 + MOS7720_SP1_REG, /* device control regs */ 141 + MOS7720_SP2_REG, /* serial port 2 (7720 only) */ 142 + MOS7720_PP_REG, 143 + MOS7720_SP_CONTROL_REG, 144 144 }; 145 145 146 146 /* ··· 150 150 static inline __u16 get_reg_index(enum mos_regs reg) 151 151 { 152 152 static const __u16 mos7715_index_lookup_table[] = { 153 - 0x00, /* THR */ 154 - 0x00, /* RHR */ 155 - 0x01, /* IER */ 156 - 0x02, /* FCR */ 157 - 0x02, /* ISR */ 158 - 0x03, /* LCR */ 159 - 0x04, /* MCR */ 160 - 0x05, /* LSR */ 161 - 0x06, /* MSR */ 162 - 0x07, /* SPR */ 163 - 0x00, /* DLL */ 164 - 0x01, /* DLM */ 165 - 0x00, /* DPR */ 166 - 0x01, /* DSR */ 167 - 0x02, /* DCR */ 168 - 0x0a, /* ECR */ 169 - 0x01, /* SP1_REG */ 170 - 0x02, /* SP2_REG (7720 only) */ 171 - 0x04, /* PP_REG (7715 only) */ 172 - 0x08, /* SP_CONTROL_REG */ 153 + 0x00, /* MOS7720_THR */ 154 + 0x00, /* MOS7720_RHR */ 155 + 0x01, /* MOS7720_IER */ 156 + 0x02, /* MOS7720_FCR */ 157 + 0x02, /* MOS7720_ISR */ 158 + 0x03, /* MOS7720_LCR */ 159 + 0x04, /* MOS7720_MCR */ 160 + 0x05, /* MOS7720_LSR */ 161 + 0x06, /* MOS7720_MSR */ 162 + 0x07, /* MOS7720_SPR */ 163 + 0x00, /* MOS7720_DLL */ 164 + 0x01, /* MOS7720_DLM */ 165 + 0x00, /* MOS7720_DPR */ 166 + 0x01, /* MOS7720_DSR */ 167 + 0x02, /* MOS7720_DCR */ 168 + 0x0a, /* MOS7720_ECR */ 169 + 0x01, /* MOS7720_SP1_REG */ 170 + 0x02, /* MOS7720_SP2_REG (7720 only) */ 171 + 0x04, /* MOS7720_PP_REG (7715 only) */ 172 + 0x08, /* MOS7720_SP_CONTROL_REG */ 173 173 }; 174 174 return mos7715_index_lookup_table[reg]; 175 175 } ··· 181 181 static inline __u16 get_reg_value(enum mos_regs reg, 182 182 unsigned int serial_portnum) 183 183 { 184 - if (reg >= SP1_REG) /* control reg */ 184 + if (reg >= MOS7720_SP1_REG) /* control reg */ 185 185 return 0x0000; 186 186 187 - else if (reg >= DPR) /* parallel port reg (7715 only) */ 187 + else if (reg >= MOS7720_DPR) /* parallel port reg (7715 only) */ 188 188 return 0x0100; 189 189 190 190 else /* serial port reg */ ··· 252 252 enum mos7715_pp_modes mode) 253 253 { 254 254 mos_parport->shadowECR = mode; 255 - write_mos_reg(mos_parport->serial, dummy, ECR, mos_parport->shadowECR); 255 + write_mos_reg(mos_parport->serial, dummy, MOS7720_ECR, 256 + mos_parport->shadowECR); 256 257 return 0; 257 258 } 258 259 ··· 487 486 if (parport_prologue(pp) < 0) 488 487 return; 489 488 mos7715_change_mode(mos_parport, SPP); 490 - write_mos_reg(mos_parport->serial, dummy, DPR, (__u8)d); 489 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DPR, (__u8)d); 491 490 parport_epilogue(pp); 492 491 } 493 492 ··· 498 497 499 498 if (parport_prologue(pp) < 0) 500 499 return 0; 501 - read_mos_reg(mos_parport->serial, dummy, DPR, &d); 500 + read_mos_reg(mos_parport->serial, dummy, MOS7720_DPR, &d); 502 501 parport_epilogue(pp); 503 502 return d; 504 503 } ··· 511 510 if (parport_prologue(pp) < 0) 512 511 return; 513 512 data = ((__u8)d & 0x0f) | (mos_parport->shadowDCR & 0xf0); 514 - write_mos_reg(mos_parport->serial, dummy, DCR, data); 513 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, data); 515 514 mos_parport->shadowDCR = data; 516 515 parport_epilogue(pp); 517 516 } ··· 544 543 if (parport_prologue(pp) < 0) 545 544 return 0; 546 545 mos_parport->shadowDCR = (mos_parport->shadowDCR & (~mask)) ^ val; 547 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 546 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 547 + mos_parport->shadowDCR); 548 548 dcr = mos_parport->shadowDCR & 0x0f; 549 549 parport_epilogue(pp); 550 550 return dcr; ··· 583 581 return; 584 582 mos7715_change_mode(mos_parport, PS2); 585 583 mos_parport->shadowDCR &= ~0x20; 586 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 584 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 585 + mos_parport->shadowDCR); 587 586 parport_epilogue(pp); 588 587 } 589 588 ··· 596 593 return; 597 594 mos7715_change_mode(mos_parport, PS2); 598 595 mos_parport->shadowDCR |= 0x20; 599 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 596 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 597 + mos_parport->shadowDCR); 600 598 parport_epilogue(pp); 601 599 } 602 600 ··· 637 633 spin_unlock(&release_lock); 638 634 return; 639 635 } 640 - write_parport_reg_nonblock(mos_parport, DCR, mos_parport->shadowDCR); 641 - write_parport_reg_nonblock(mos_parport, ECR, mos_parport->shadowECR); 636 + write_parport_reg_nonblock(mos_parport, MOS7720_DCR, 637 + mos_parport->shadowDCR); 638 + write_parport_reg_nonblock(mos_parport, MOS7720_ECR, 639 + mos_parport->shadowECR); 642 640 spin_unlock(&release_lock); 643 641 } 644 642 ··· 720 714 init_completion(&mos_parport->syncmsg_compl); 721 715 722 716 /* cycle parallel port reset bit */ 723 - write_mos_reg(mos_parport->serial, dummy, PP_REG, (__u8)0x80); 724 - write_mos_reg(mos_parport->serial, dummy, PP_REG, (__u8)0x00); 717 + write_mos_reg(mos_parport->serial, dummy, MOS7720_PP_REG, (__u8)0x80); 718 + write_mos_reg(mos_parport->serial, dummy, MOS7720_PP_REG, (__u8)0x00); 725 719 726 720 /* initialize device registers */ 727 721 mos_parport->shadowDCR = DCR_INIT_VAL; 728 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 722 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 723 + mos_parport->shadowDCR); 729 724 mos_parport->shadowECR = ECR_INIT_VAL; 730 - write_mos_reg(mos_parport->serial, dummy, ECR, mos_parport->shadowECR); 725 + write_mos_reg(mos_parport->serial, dummy, MOS7720_ECR, 726 + mos_parport->shadowECR); 731 727 732 728 /* register with parport core */ 733 729 mos_parport->pp = parport_register_port(0, PARPORT_IRQ_NONE, ··· 1041 1033 /* Initialize MCS7720 -- Write Init values to corresponding Registers 1042 1034 * 1043 1035 * Register Index 1044 - * 0 : THR/RHR 1045 - * 1 : IER 1046 - * 2 : FCR 1047 - * 3 : LCR 1048 - * 4 : MCR 1049 - * 5 : LSR 1050 - * 6 : MSR 1051 - * 7 : SPR 1036 + * 0 : MOS7720_THR/MOS7720_RHR 1037 + * 1 : MOS7720_IER 1038 + * 2 : MOS7720_FCR 1039 + * 3 : MOS7720_LCR 1040 + * 4 : MOS7720_MCR 1041 + * 5 : MOS7720_LSR 1042 + * 6 : MOS7720_MSR 1043 + * 7 : MOS7720_SPR 1052 1044 * 1053 1045 * 0x08 : SP1/2 Control Reg 1054 1046 */ 1055 1047 port_number = port->port_number; 1056 - read_mos_reg(serial, port_number, LSR, &data); 1048 + read_mos_reg(serial, port_number, MOS7720_LSR, &data); 1057 1049 1058 1050 dev_dbg(&port->dev, "SS::%p LSR:%x\n", mos7720_port, data); 1059 1051 1060 - write_mos_reg(serial, dummy, SP1_REG, 0x02); 1061 - write_mos_reg(serial, dummy, SP2_REG, 0x02); 1052 + write_mos_reg(serial, dummy, MOS7720_SP1_REG, 0x02); 1053 + write_mos_reg(serial, dummy, MOS7720_SP2_REG, 0x02); 1062 1054 1063 - write_mos_reg(serial, port_number, IER, 0x00); 1064 - write_mos_reg(serial, port_number, FCR, 0x00); 1055 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1056 + write_mos_reg(serial, port_number, MOS7720_FCR, 0x00); 1065 1057 1066 - write_mos_reg(serial, port_number, FCR, 0xcf); 1058 + write_mos_reg(serial, port_number, MOS7720_FCR, 0xcf); 1067 1059 mos7720_port->shadowLCR = 0x03; 1068 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1060 + write_mos_reg(serial, port_number, MOS7720_LCR, 1061 + mos7720_port->shadowLCR); 1069 1062 mos7720_port->shadowMCR = 0x0b; 1070 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1063 + write_mos_reg(serial, port_number, MOS7720_MCR, 1064 + mos7720_port->shadowMCR); 1071 1065 1072 - write_mos_reg(serial, port_number, SP_CONTROL_REG, 0x00); 1073 - read_mos_reg(serial, dummy, SP_CONTROL_REG, &data); 1066 + write_mos_reg(serial, port_number, MOS7720_SP_CONTROL_REG, 0x00); 1067 + read_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, &data); 1074 1068 data = data | (port->port_number + 1); 1075 - write_mos_reg(serial, dummy, SP_CONTROL_REG, data); 1069 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, data); 1076 1070 mos7720_port->shadowLCR = 0x83; 1077 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1078 - write_mos_reg(serial, port_number, THR, 0x0c); 1079 - write_mos_reg(serial, port_number, IER, 0x00); 1071 + write_mos_reg(serial, port_number, MOS7720_LCR, 1072 + mos7720_port->shadowLCR); 1073 + write_mos_reg(serial, port_number, MOS7720_THR, 0x0c); 1074 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1080 1075 mos7720_port->shadowLCR = 0x03; 1081 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1082 - write_mos_reg(serial, port_number, IER, 0x0c); 1076 + write_mos_reg(serial, port_number, MOS7720_LCR, 1077 + mos7720_port->shadowLCR); 1078 + write_mos_reg(serial, port_number, MOS7720_IER, 0x0c); 1083 1079 1084 1080 response = usb_submit_urb(port->read_urb, GFP_KERNEL); 1085 1081 if (response) ··· 1156 1144 usb_kill_urb(port->write_urb); 1157 1145 usb_kill_urb(port->read_urb); 1158 1146 1159 - write_mos_reg(serial, port->port_number, MCR, 0x00); 1160 - write_mos_reg(serial, port->port_number, IER, 0x00); 1147 + write_mos_reg(serial, port->port_number, MOS7720_MCR, 0x00); 1148 + write_mos_reg(serial, port->port_number, MOS7720_IER, 0x00); 1161 1149 1162 1150 mos7720_port->open = 0; 1163 1151 } ··· 1181 1169 data = mos7720_port->shadowLCR & ~UART_LCR_SBC; 1182 1170 1183 1171 mos7720_port->shadowLCR = data; 1184 - write_mos_reg(serial, port->port_number, LCR, mos7720_port->shadowLCR); 1172 + write_mos_reg(serial, port->port_number, MOS7720_LCR, 1173 + mos7720_port->shadowLCR); 1185 1174 } 1186 1175 1187 1176 /* ··· 1310 1297 /* if we are implementing RTS/CTS, toggle that line */ 1311 1298 if (tty->termios.c_cflag & CRTSCTS) { 1312 1299 mos7720_port->shadowMCR &= ~UART_MCR_RTS; 1313 - write_mos_reg(port->serial, port->port_number, MCR, 1300 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1314 1301 mos7720_port->shadowMCR); 1315 1302 } 1316 1303 } ··· 1340 1327 /* if we are implementing RTS/CTS, toggle that line */ 1341 1328 if (tty->termios.c_cflag & CRTSCTS) { 1342 1329 mos7720_port->shadowMCR |= UART_MCR_RTS; 1343 - write_mos_reg(port->serial, port->port_number, MCR, 1330 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1344 1331 mos7720_port->shadowMCR); 1345 1332 } 1346 1333 } ··· 1365 1352 dev_dbg(&port->dev, "Sending Setting Commands ..........\n"); 1366 1353 port_number = port->port_number; 1367 1354 1368 - write_mos_reg(serial, port_number, IER, 0x00); 1369 - write_mos_reg(serial, port_number, FCR, 0x00); 1370 - write_mos_reg(serial, port_number, FCR, 0xcf); 1355 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1356 + write_mos_reg(serial, port_number, MOS7720_FCR, 0x00); 1357 + write_mos_reg(serial, port_number, MOS7720_FCR, 0xcf); 1371 1358 mos7720_port->shadowMCR = 0x0b; 1372 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1373 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x00); 1359 + write_mos_reg(serial, port_number, MOS7720_MCR, 1360 + mos7720_port->shadowMCR); 1361 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 0x00); 1374 1362 1375 1363 /*********************************************** 1376 1364 * Set for higher rates * 1377 1365 ***********************************************/ 1378 1366 /* writing baud rate verbatum into uart clock field clearly not right */ 1379 1367 if (port_number == 0) 1380 - sp_reg = SP1_REG; 1368 + sp_reg = MOS7720_SP1_REG; 1381 1369 else 1382 - sp_reg = SP2_REG; 1370 + sp_reg = MOS7720_SP2_REG; 1383 1371 write_mos_reg(serial, dummy, sp_reg, baud * 0x10); 1384 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x03); 1372 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 0x03); 1385 1373 mos7720_port->shadowMCR = 0x2b; 1386 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1374 + write_mos_reg(serial, port_number, MOS7720_MCR, 1375 + mos7720_port->shadowMCR); 1387 1376 1388 1377 /*********************************************** 1389 1378 * Set DLL/DLM 1390 1379 ***********************************************/ 1391 1380 mos7720_port->shadowLCR = mos7720_port->shadowLCR | UART_LCR_DLAB; 1392 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1393 - write_mos_reg(serial, port_number, DLL, 0x01); 1394 - write_mos_reg(serial, port_number, DLM, 0x00); 1381 + write_mos_reg(serial, port_number, MOS7720_LCR, 1382 + mos7720_port->shadowLCR); 1383 + write_mos_reg(serial, port_number, MOS7720_DLL, 0x01); 1384 + write_mos_reg(serial, port_number, MOS7720_DLM, 0x00); 1395 1385 mos7720_port->shadowLCR = mos7720_port->shadowLCR & ~UART_LCR_DLAB; 1396 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1386 + write_mos_reg(serial, port_number, MOS7720_LCR, 1387 + mos7720_port->shadowLCR); 1397 1388 1398 1389 return 0; 1399 1390 } ··· 1505 1488 1506 1489 /* Enable access to divisor latch */ 1507 1490 mos7720_port->shadowLCR = mos7720_port->shadowLCR | UART_LCR_DLAB; 1508 - write_mos_reg(serial, number, LCR, mos7720_port->shadowLCR); 1491 + write_mos_reg(serial, number, MOS7720_LCR, mos7720_port->shadowLCR); 1509 1492 1510 1493 /* Write the divisor */ 1511 - write_mos_reg(serial, number, DLL, (__u8)(divisor & 0xff)); 1512 - write_mos_reg(serial, number, DLM, (__u8)((divisor & 0xff00) >> 8)); 1494 + write_mos_reg(serial, number, MOS7720_DLL, (__u8)(divisor & 0xff)); 1495 + write_mos_reg(serial, number, MOS7720_DLM, 1496 + (__u8)((divisor & 0xff00) >> 8)); 1513 1497 1514 1498 /* Disable access to divisor latch */ 1515 1499 mos7720_port->shadowLCR = mos7720_port->shadowLCR & ~UART_LCR_DLAB; 1516 - write_mos_reg(serial, number, LCR, mos7720_port->shadowLCR); 1500 + write_mos_reg(serial, number, MOS7720_LCR, mos7720_port->shadowLCR); 1517 1501 1518 1502 return status; 1519 1503 } ··· 1618 1600 1619 1601 1620 1602 /* Disable Interrupts */ 1621 - write_mos_reg(serial, port_number, IER, 0x00); 1622 - write_mos_reg(serial, port_number, FCR, 0x00); 1623 - write_mos_reg(serial, port_number, FCR, 0xcf); 1603 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1604 + write_mos_reg(serial, port_number, MOS7720_FCR, 0x00); 1605 + write_mos_reg(serial, port_number, MOS7720_FCR, 0xcf); 1624 1606 1625 1607 /* Send the updated LCR value to the mos7720 */ 1626 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1608 + write_mos_reg(serial, port_number, MOS7720_LCR, 1609 + mos7720_port->shadowLCR); 1627 1610 mos7720_port->shadowMCR = 0x0b; 1628 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1611 + write_mos_reg(serial, port_number, MOS7720_MCR, 1612 + mos7720_port->shadowMCR); 1629 1613 1630 1614 /* set up the MCR register and send it to the mos7720 */ 1631 1615 mos7720_port->shadowMCR = UART_MCR_OUT2; ··· 1639 1619 /* To set hardware flow control to the specified * 1640 1620 * serial port, in SP1/2_CONTROL_REG */ 1641 1621 if (port_number) 1642 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x01); 1622 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 1623 + 0x01); 1643 1624 else 1644 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x02); 1625 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 1626 + 0x02); 1645 1627 1646 1628 } else 1647 1629 mos7720_port->shadowMCR &= ~(UART_MCR_XONANY); 1648 1630 1649 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1631 + write_mos_reg(serial, port_number, MOS7720_MCR, 1632 + mos7720_port->shadowMCR); 1650 1633 1651 1634 /* Determine divisor based on baud rate */ 1652 1635 baud = tty_get_baud_rate(tty); ··· 1662 1639 if (baud >= 230400) { 1663 1640 set_higher_rates(mos7720_port, baud); 1664 1641 /* Enable Interrupts */ 1665 - write_mos_reg(serial, port_number, IER, 0x0c); 1642 + write_mos_reg(serial, port_number, MOS7720_IER, 0x0c); 1666 1643 return; 1667 1644 } 1668 1645 ··· 1673 1650 if (cflag & CBAUD) 1674 1651 tty_encode_baud_rate(tty, baud, baud); 1675 1652 /* Enable Interrupts */ 1676 - write_mos_reg(serial, port_number, IER, 0x0c); 1653 + write_mos_reg(serial, port_number, MOS7720_IER, 0x0c); 1677 1654 1678 1655 if (port->read_urb->status != -EINPROGRESS) { 1679 1656 status = usb_submit_urb(port->read_urb, GFP_KERNEL); ··· 1748 1725 1749 1726 count = mos7720_chars_in_buffer(tty); 1750 1727 if (count == 0) { 1751 - read_mos_reg(port->serial, port_number, LSR, &data); 1728 + read_mos_reg(port->serial, port_number, MOS7720_LSR, &data); 1752 1729 if ((data & (UART_LSR_TEMT | UART_LSR_THRE)) 1753 1730 == (UART_LSR_TEMT | UART_LSR_THRE)) { 1754 1731 dev_dbg(&port->dev, "%s -- Empty\n", __func__); ··· 1805 1782 mcr &= ~UART_MCR_LOOP; 1806 1783 1807 1784 mos7720_port->shadowMCR = mcr; 1808 - write_mos_reg(port->serial, port->port_number, MCR, 1785 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1809 1786 mos7720_port->shadowMCR); 1810 1787 1811 1788 return 0; ··· 1850 1827 } 1851 1828 1852 1829 mos7720_port->shadowMCR = mcr; 1853 - write_mos_reg(port->serial, port->port_number, MCR, 1830 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1854 1831 mos7720_port->shadowMCR); 1855 1832 1856 1833 return 0; ··· 1965 1942 } 1966 1943 #endif 1967 1944 /* LSR For Port 1 */ 1968 - read_mos_reg(serial, 0, LSR, &data); 1945 + read_mos_reg(serial, 0, MOS7720_LSR, &data); 1969 1946 dev_dbg(&dev->dev, "LSR:%x\n", data); 1970 1947 1971 1948 return 0;
+1
drivers/usb/serial/option.c
··· 1765 1765 { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d03, 0xff, 0x00, 0x00) }, 1766 1766 { USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x3e01, 0xff, 0xff, 0xff) }, /* D-Link DWM-152/C1 */ 1767 1767 { USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x3e02, 0xff, 0xff, 0xff) }, /* D-Link DWM-156/C1 */ 1768 + { USB_DEVICE_INTERFACE_CLASS(0x2020, 0x4000, 0xff) }, /* OLICARD300 - MT6225 */ 1768 1769 { USB_DEVICE(INOVIA_VENDOR_ID, INOVIA_SEW858) }, 1769 1770 { USB_DEVICE(VIATELECOM_VENDOR_ID, VIATELECOM_PRODUCT_CDS7) }, 1770 1771 { } /* Terminating entry */
+1
drivers/usb/serial/usb-serial.c
··· 1306 1306 tty_unregister_driver(usb_serial_tty_driver); 1307 1307 put_tty_driver(usb_serial_tty_driver); 1308 1308 bus_unregister(&usb_serial_bus_type); 1309 + idr_destroy(&serial_minors); 1309 1310 } 1310 1311 1311 1312