tools headers cpufeatures: Sync with the kernel sources

To pick the changes from:

5e85c4ebf206e50c ("x86: KVM: Advertise AVX-IFMA CPUID to user space")
af2872f622547656 ("x86: KVM: Advertise AMX-FP16 CPUID to user space")
6a19d7aa5821522e ("x86: KVM: Advertise CMPccXADD CPUID to user space")
aaa65d17eec372c6 ("x86/tsx: Add a feature bit for TSX control MSR support")
b1599915f09157e9 ("x86/cpufeatures: Move X86_FEATURE_CALL_DEPTH from bit 18 to bit 19 of word 11, to leave space for WIP X86_FEATURE_SGX_EDECCSSA bit")
16a7fe3728a8b832 ("KVM/VMX: Allow exposing EDECCSSA user leaf function to KVM guest")
80e4c1cd42fff110 ("x86/retbleed: Add X86_FEATURE_CALL_DEPTH")
7df548840c496b01 ("x86/bugs: Add "unknown" reporting for MMIO Stale Data")

This only causes these perf files to be rebuilt:

CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Cc: Adrian Hunter <[e-mail]>
Cc: Borislav Petkov <[e-mail]>
Cc: Chang S. Bae <[e-mail]>
Cc: Dave Hansen <[e-mail]>
Cc: Ian Rogers <[e-mail]>
Cc: Ingo Molnar <[e-mail]>
Cc: Jiaxi Chen <[e-mail]>
Cc: Jiri Olsa <[e-mail]>
Cc: Kai Huang <[e-mail]>
Cc: Namhyung Kim <[e-mail]>
Cc: Pawan Gupta <[e-mail]>
Cc: Peter Zijlstra <[e-mail]>
Cc: Thomas Gleixner <[e-mail]>
Link: https://lore.kernel.org/lkml/[e-mail]/
Signed-off-by: Arnaldo Carvalho de Melo <[e-mail]>

tools/arch/x86/include/asm/cpufeatures.h

···
 #define X86_FEATURE_UNRET		(11*32+15) /* "" AMD BTB untrain return */
 #define X86_FEATURE_USE_IBPB_FW		(11*32+16) /* "" Use IBPB during runtime firmware calls */
 #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
+#define X86_FEATURE_SGX_EDECCSSA	(11*32+18) /* "" SGX EDECCSSA user leaf function */
+#define X86_FEATURE_CALL_DEPTH		(11*32+19) /* "" Call depth tracking for RSB stuffing */
+#define X86_FEATURE_MSR_TSX_CTRL	(11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */
+#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */
+#define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */