ARM: S5PC100: Clenaup map.h file

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

+82 -109
+82 -109
arch/arm/mach-s5pc100/include/mach/map.h
··· 1 1 /* linux/arch/arm/mach-s5pc100/include/mach/map.h 2 2 * 3 + * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 + * http://www.samsung.com/ 5 + * 3 6 * Copyright 2009 Samsung Electronics Co. 4 7 * Byungho Min <bhmin@samsung.com> 5 8 * ··· 19 16 #include <plat/map-base.h> 20 17 #include <plat/map-s5p.h> 21 18 22 - /* 23 - * map-base.h has already defined virtual memory address 24 - * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) 25 - * S3C_VA_SYS S3C_ADDR(0x00100000) system control 26 - * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) 27 - * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block 28 - * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog 29 - * S3C_VA_UART S3C_ADDR(0x01000000) UART 30 - * 31 - * S5PC100 specific virtual memory address can be defined here 32 - * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO 33 - * 34 - */ 19 + #define S5PC100_PA_SDRAM 0x20000000 35 20 36 - #define S5PC100_PA_ONENAND_BUF (0xB0000000) 37 - #define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M) 21 + #define S5PC100_PA_ONENAND 0xE7100000 22 + #define S5PC100_PA_ONENAND_BUF 0xB0000000 38 23 39 - /* Chip ID */ 24 + #define S5PC100_PA_CHIPID 0xE0000000 40 25 41 - #define S5PC100_PA_CHIPID (0xE0000000) 42 - #define S5P_PA_CHIPID S5PC100_PA_CHIPID 26 + #define S5PC100_PA_SYSCON 0xE0100000 43 27 44 - #define S5PC100_PA_SYSCON (0xE0100000) 45 - #define S5P_PA_SYSCON S5PC100_PA_SYSCON 28 + #define S5PC100_PA_OTHERS 0xE0200000 46 29 47 - #define S5PC100_PA_OTHERS (0xE0200000) 48 - #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) 30 + #define S5PC100_PA_GPIO 0xE0300000 49 31 50 - #define S5PC100_PA_GPIO (0xE0300000) 51 - #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) 32 + #define S5PC100_PA_VIC0 0xE4000000 33 + #define S5PC100_PA_VIC1 0xE4100000 34 + #define S5PC100_PA_VIC2 0xE4200000 52 35 53 - /* Interrupt */ 54 - #define S5PC100_PA_VIC0 (0xE4000000) 55 - #define S5PC100_PA_VIC1 (0xE4100000) 56 - #define S5PC100_PA_VIC2 (0xE4200000) 57 - #define S5PC100_VA_VIC S3C_VA_IRQ 58 - #define S5PC100_VA_VIC_OFFSET 0x10000 59 - #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 36 + #define S5PC100_PA_SROMC 0xE7000000 60 37 61 - #define S5PC100_PA_SROMC (0xE7000000) 62 - #define S5P_PA_SROMC S5PC100_PA_SROMC 38 + #define S5PC100_PA_CFCON 0xE7800000 63 39 64 - #define S5PC100_PA_ONENAND (0xE7100000) 40 + #define S5PC100_PA_MDMA 0xE8100000 41 + #define S5PC100_PA_PDMA0 0xE9000000 42 + #define S5PC100_PA_PDMA1 0xE9200000 65 43 66 - #define S5PC100_PA_CFCON (0xE7800000) 44 + #define S5PC100_PA_TIMER 0xEA000000 45 + #define S5PC100_PA_SYSTIMER 0xEA100000 46 + #define S5PC100_PA_WATCHDOG 0xEA200000 47 + #define S5PC100_PA_RTC 0xEA300000 67 48 68 - /* DMA */ 69 - #define S5PC100_PA_MDMA (0xE8100000) 70 - #define S5PC100_PA_PDMA0 (0xE9000000) 71 - #define S5PC100_PA_PDMA1 (0xE9200000) 49 + #define S5PC100_PA_UART 0xEC000000 72 50 73 - /* Timer */ 74 - #define S5PC100_PA_TIMER (0xEA000000) 75 - #define S5P_PA_TIMER S5PC100_PA_TIMER 51 + #define S5PC100_PA_IIC0 0xEC100000 52 + #define S5PC100_PA_IIC1 0xEC200000 76 53 77 - #define S5PC100_PA_SYSTIMER (0xEA100000) 54 + #define S5PC100_PA_SPI0 0xEC300000 55 + #define S5PC100_PA_SPI1 0xEC400000 56 + #define S5PC100_PA_SPI2 0xEC500000 78 57 79 - #define S5PC100_PA_WATCHDOG (0xEA200000) 80 - #define S5PC100_PA_RTC (0xEA300000) 58 + #define S5PC100_PA_USB_HSOTG 0xED200000 59 + #define S5PC100_PA_USB_HSPHY 0xED300000 81 60 82 - #define S5PC100_PA_UART (0xEC000000) 61 + #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 83 62 84 - #define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) 85 - #define S5P_PA_UART1 (S5PC100_PA_UART + 0x400) 86 - #define S5P_PA_UART2 (S5PC100_PA_UART + 0x800) 87 - #define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00) 88 - #define S5P_SZ_UART SZ_256 63 + #define S5PC100_PA_FB 0xEE000000 89 64 90 - #define S5PC100_PA_IIC0 (0xEC100000) 91 - #define S5PC100_PA_IIC1 (0xEC200000) 65 + #define S5PC100_PA_FIMC0 0xEE200000 66 + #define S5PC100_PA_FIMC1 0xEE300000 67 + #define S5PC100_PA_FIMC2 0xEE400000 92 68 93 - /* SPI */ 94 - #define S5PC100_PA_SPI0 0xEC300000 95 - #define S5PC100_PA_SPI1 0xEC400000 96 - #define S5PC100_PA_SPI2 0xEC500000 69 + #define S5PC100_PA_I2S0 0xF2000000 70 + #define S5PC100_PA_I2S1 0xF2100000 71 + #define S5PC100_PA_I2S2 0xF2200000 97 72 98 - /* USB HS OTG */ 99 - #define S5PC100_PA_USB_HSOTG (0xED200000) 100 - #define S5PC100_PA_USB_HSPHY (0xED300000) 73 + #define S5PC100_PA_AC97 0xF2300000 101 74 102 - #define S5PC100_PA_FB (0xEE000000) 75 + #define S5PC100_PA_PCM0 0xF2400000 76 + #define S5PC100_PA_PCM1 0xF2500000 103 77 104 - #define S5PC100_PA_FIMC0 (0xEE200000) 105 - #define S5PC100_PA_FIMC1 (0xEE300000) 106 - #define S5PC100_PA_FIMC2 (0xEE400000) 78 + #define S5PC100_PA_SPDIF 0xF2600000 107 79 108 - #define S5PC100_PA_I2S0 (0xF2000000) 109 - #define S5PC100_PA_I2S1 (0xF2100000) 110 - #define S5PC100_PA_I2S2 (0xF2200000) 80 + #define S5PC100_PA_TSADC 0xF3000000 111 81 112 - #define S5PC100_PA_AC97 0xF2300000 82 + #define S5PC100_PA_KEYPAD 0xF3100000 113 83 114 - /* PCM */ 115 - #define S5PC100_PA_PCM0 0xF2400000 116 - #define S5PC100_PA_PCM1 0xF2500000 84 + /* Compatibiltiy Defines */ 117 85 118 - #define S5PC100_PA_SPDIF 0xF2600000 86 + #define S3C_PA_FB S5PC100_PA_FB 87 + #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) 88 + #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) 89 + #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) 90 + #define S3C_PA_IIC S5PC100_PA_IIC0 91 + #define S3C_PA_IIC1 S5PC100_PA_IIC1 92 + #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD 93 + #define S3C_PA_ONENAND S5PC100_PA_ONENAND 94 + #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF 95 + #define S3C_PA_RTC S5PC100_PA_RTC 96 + #define S3C_PA_TSADC S5PC100_PA_TSADC 97 + #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 98 + #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 99 + #define S3C_PA_WDT S5PC100_PA_WATCHDOG 119 100 120 - #define S5PC100_PA_TSADC (0xF3000000) 101 + #define S5P_PA_CHIPID S5PC100_PA_CHIPID 102 + #define S5P_PA_FIMC0 S5PC100_PA_FIMC0 103 + #define S5P_PA_FIMC1 S5PC100_PA_FIMC1 104 + #define S5P_PA_FIMC2 S5PC100_PA_FIMC2 105 + #define S5P_PA_SDRAM S5PC100_PA_SDRAM 106 + #define S5P_PA_SROMC S5PC100_PA_SROMC 107 + #define S5P_PA_SYSCON S5PC100_PA_SYSCON 108 + #define S5P_PA_TIMER S5PC100_PA_TIMER 121 109 122 - /* KEYPAD */ 123 - #define S5PC100_PA_KEYPAD (0xF3100000) 110 + #define SAMSUNG_PA_ADC S5PC100_PA_TSADC 111 + #define SAMSUNG_PA_CFCON S5PC100_PA_CFCON 112 + #define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD 124 113 125 - #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 114 + #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) 126 115 127 - #define S5PC100_PA_SDRAM (0x20000000) 128 - #define S5P_PA_SDRAM S5PC100_PA_SDRAM 116 + #define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M) 129 117 130 - /* compatibiltiy defines. */ 131 - #define S3C_PA_UART S5PC100_PA_UART 132 - #define S3C_PA_IIC S5PC100_PA_IIC0 133 - #define S3C_PA_IIC1 S5PC100_PA_IIC1 134 - #define S3C_PA_FB S5PC100_PA_FB 135 - #define S3C_PA_G2D S5PC100_PA_G2D 136 - #define S3C_PA_G3D S5PC100_PA_G3D 137 - #define S3C_PA_JPEG S5PC100_PA_JPEG 138 - #define S3C_PA_ROTATOR S5PC100_PA_ROTATOR 139 - #define S5P_VA_VIC0 S5PC1XX_VA_VIC(0) 140 - #define S5P_VA_VIC1 S5PC1XX_VA_VIC(1) 141 - #define S5P_VA_VIC2 S5PC1XX_VA_VIC(2) 142 - #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 143 - #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 144 - #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) 145 - #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) 146 - #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) 147 - #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD 148 - #define S3C_PA_WDT S5PC100_PA_WATCHDOG 149 - #define S3C_PA_TSADC S5PC100_PA_TSADC 150 - #define S3C_PA_ONENAND S5PC100_PA_ONENAND 151 - #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF 152 - #define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF 153 - #define S3C_PA_RTC S5PC100_PA_RTC 118 + /* UART */ 154 119 155 - #define SAMSUNG_PA_ADC S5PC100_PA_TSADC 156 - #define SAMSUNG_PA_CFCON S5PC100_PA_CFCON 157 - #define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD 120 + #define S3C_PA_UART S5PC100_PA_UART 158 121 159 - #define S5P_PA_FIMC0 S5PC100_PA_FIMC0 160 - #define S5P_PA_FIMC1 S5PC100_PA_FIMC1 161 - #define S5P_PA_FIMC2 S5PC100_PA_FIMC2 122 + #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) 123 + #define S5P_PA_UART0 S5P_PA_UART(0) 124 + #define S5P_PA_UART1 S5P_PA_UART(1) 125 + #define S5P_PA_UART2 S5P_PA_UART(2) 126 + #define S5P_PA_UART3 S5P_PA_UART(3) 162 127 163 - #endif /* __ASM_ARCH_C100_MAP_H */ 128 + #define S5P_SZ_UART SZ_256 129 + 130 + #endif /* __ASM_ARCH_MAP_H */