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m32r: Simplify ei_handler code

Simplify and clean up messy ei_handler code in arch/m32r/kernel/entry.S.
- Remove ifdef's for CONFIG_CHIP_* configulations.
- Rearrange the M32700 workaround code.
- Remove the messy platform-dependent interrupt check routines and
consolidate them to common INT0/INT1/INT2 check routines for all
platforms with cascaded interrupt controllers.

Signed-off-by: Hitoshi Yamamoto <hitoshiy@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>

Hirokazu Takata 5171b100 e070fb74

+39 -202
unified split
+39 -202
arch/m32r/kernel/entry.S
··· 290 */ 291 ENTRY(ei_handler) 292 #if defined(CONFIG_CHIP_M32700) 293 - SWITCH_TO_KERNEL_STACK 294 ; WORKAROUND: force to clear SM bit and use the kernel stack (SPI). 295 #endif 296 SAVE_ALL 297 mv r1, sp ; arg1(regs) 298 - #if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 299 - || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ 300 - || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) 301 - 302 - ; GET_ICU_STATUS; 303 seth r0, #shigh(M32R_ICU_ISTS_ADDR) 304 ld r0, @(low(M32R_ICU_ISTS_ADDR),r0) 305 push r0 ··· 310 ;; IRQ exist check 311 #if defined(CONFIG_CHIP_M32700) 312 /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */ 313 - beqz r0, 3f ; if (!irq_num) goto exit 314 - #else 315 beqz r0, 1f ; if (!irq_num) goto exit 316 - #endif /* WORKAROUND */ 317 ;; IPI check 318 cmpi r0, #(M32R_IRQ_IPI0<<2) ; ISN < IPI0 check 319 bc 2f ··· 334 1: 335 addi sp, #4 336 bra ret_to_intr 337 - #if defined(CONFIG_CHIP_M32700) 338 - /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */ 339 - .fillinsn 340 - 3: 341 - ld24 r14, #0x00070000 342 - seth r0, #shigh(M32R_ICU_IMASK_ADDR) 343 - st r14, @(low(M32R_ICU_IMASK_ADDR), r0) 344 - addi sp, #4 345 - bra ret_to_intr 346 - #endif /* WORKAROUND */ 347 - ;; do_IRQ 348 .fillinsn 349 2: 350 srli r0, #2 351 - #if defined(CONFIG_PLAT_USRV) 352 - add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 353 - bnez r2, 9f 354 - ; read ICU status register of PLD 355 - seth r0, #high(PLD_ICUISTS) 356 - or3 r0, r0, #low(PLD_ICUISTS) 357 - lduh r0, @r0 358 - slli r0, #21 359 - srli r0, #27 ; ISN 360 - addi r0, #(M32700UT_PLD_IRQ_BASE) 361 - .fillinsn 362 - 9: 363 - #elif defined(CONFIG_PLAT_M32700UT) 364 - add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 365 - bnez r2, check_int0 366 - ; read ICU status register of PLD 367 - seth r0, #high(PLD_ICUISTS) 368 - or3 r0, r0, #low(PLD_ICUISTS) 369 - lduh r0, @r0 370 - slli r0, #21 371 - srli r0, #27 ; ISN 372 - addi r0, #(M32700UT_PLD_IRQ_BASE) 373 - bra check_end 374 - .fillinsn 375 - check_int0: 376 - add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt 377 - bnez r2, check_int2 378 - ; read ICU status of LAN-board 379 - seth r0, #high(M32700UT_LAN_ICUISTS) 380 - or3 r0, r0, #low(M32700UT_LAN_ICUISTS) 381 - lduh r0, @r0 382 - slli r0, #21 383 - srli r0, #27 ; ISN 384 - add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE) 385 - bra check_end 386 - .fillinsn 387 - check_int2: 388 - add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt 389 - bnez r2, check_end 390 - ; read ICU status of LCD-board 391 - seth r0, #high(M32700UT_LCD_ICUISTS) 392 - or3 r0, r0, #low(M32700UT_LCD_ICUISTS) 393 - lduh r0, @r0 394 - slli r0, #21 395 - srli r0, #27 ; ISN 396 - add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE) 397 - bra check_end 398 - .fillinsn 399 - check_end: 400 - #elif defined(CONFIG_PLAT_OPSPUT) 401 - add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 402 - bnez r2, check_int0 403 - ; read ICU status register of PLD 404 - seth r0, #high(PLD_ICUISTS) 405 - or3 r0, r0, #low(PLD_ICUISTS) 406 - lduh r0, @r0 407 - slli r0, #21 408 - srli r0, #27 ; ISN 409 - addi r0, #(OPSPUT_PLD_IRQ_BASE) 410 - bra check_end 411 - .fillinsn 412 - check_int0: 413 - add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt 414 - bnez r2, check_int2 415 - ; read ICU status of LAN-board 416 - seth r0, #high(OPSPUT_LAN_ICUISTS) 417 - or3 r0, r0, #low(OPSPUT_LAN_ICUISTS) 418 - lduh r0, @r0 419 - slli r0, #21 420 - srli r0, #27 ; ISN 421 - add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE) 422 - bra check_end 423 - .fillinsn 424 - check_int2: 425 - add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt 426 - bnez r2, check_end 427 - ; read ICU status of LCD-board 428 - seth r0, #high(OPSPUT_LCD_ICUISTS) 429 - or3 r0, r0, #low(OPSPUT_LCD_ICUISTS) 430 - lduh r0, @r0 431 - slli r0, #21 432 - srli r0, #27 ; ISN 433 - add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE) 434 - bra check_end 435 - .fillinsn 436 - check_end: 437 - #endif /* CONFIG_PLAT_OPSPUT */ 438 - bl do_IRQ ; r0(irq), r1(regs) 439 - #else /* not CONFIG_SMP */ 440 srli r0, #22 ; r0(irq) 441 - #if defined(CONFIG_PLAT_USRV) 442 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 443 - bnez r2, 1f 444 - ; read ICU status register of PLD 445 - seth r0, #high(PLD_ICUISTS) 446 - or3 r0, r0, #low(PLD_ICUISTS) 447 - lduh r0, @r0 448 slli r0, #21 449 srli r0, #27 ; ISN 450 - addi r0, #(M32700UT_PLD_IRQ_BASE) 451 - .fillinsn 452 - 1: 453 - #elif defined(CONFIG_PLAT_M32700UT) 454 - add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 455 - bnez r2, check_int0 456 - ; read ICU status register of PLD 457 - seth r0, #high(PLD_ICUISTS) 458 - or3 r0, r0, #low(PLD_ICUISTS) 459 - lduh r0, @r0 460 - slli r0, #21 461 - srli r0, #27 ; ISN 462 - addi r0, #(M32700UT_PLD_IRQ_BASE) 463 bra check_end 464 .fillinsn 465 - check_int0: 466 - add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt 467 - bnez r2, check_int2 468 - ; read ICU status of LAN-board 469 - seth r0, #high(M32700UT_LAN_ICUISTS) 470 - or3 r0, r0, #low(M32700UT_LAN_ICUISTS) 471 - lduh r0, @r0 472 slli r0, #21 473 - srli r0, #27 ; ISN 474 - add3 r0, r0, #(M32700UT_LAN_PLD_IRQ_BASE) 475 bra check_end 476 .fillinsn 477 - check_int2: 478 - add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt 479 - bnez r2, check_end 480 - ; read ICU status of LCD-board 481 - seth r0, #high(M32700UT_LCD_ICUISTS) 482 - or3 r0, r0, #low(M32700UT_LCD_ICUISTS) 483 - lduh r0, @r0 484 slli r0, #21 485 - srli r0, #27 ; ISN 486 - add3 r0, r0, #(M32700UT_LCD_PLD_IRQ_BASE) 487 - bra check_end 488 .fillinsn 489 check_end: 490 - #elif defined(CONFIG_PLAT_OPSPUT) 491 - add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 492 - bnez r2, check_int0 493 - ; read ICU status register of PLD 494 - seth r0, #high(PLD_ICUISTS) 495 - or3 r0, r0, #low(PLD_ICUISTS) 496 - lduh r0, @r0 497 - slli r0, #21 498 - srli r0, #27 ; ISN 499 - addi r0, #(OPSPUT_PLD_IRQ_BASE) 500 - bra check_end 501 - .fillinsn 502 - check_int0: 503 - add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt 504 - bnez r2, check_int2 505 - ; read ICU status of LAN-board 506 - seth r0, #high(OPSPUT_LAN_ICUISTS) 507 - or3 r0, r0, #low(OPSPUT_LAN_ICUISTS) 508 - lduh r0, @r0 509 - slli r0, #21 510 - srli r0, #27 ; ISN 511 - add3 r0, r0, #(OPSPUT_LAN_PLD_IRQ_BASE) 512 - bra check_end 513 - .fillinsn 514 - check_int2: 515 - add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt 516 - bnez r2, check_end 517 - ; read ICU status of LCD-board 518 - seth r0, #high(OPSPUT_LCD_ICUISTS) 519 - or3 r0, r0, #low(OPSPUT_LCD_ICUISTS) 520 - lduh r0, @r0 521 - slli r0, #21 522 - srli r0, #27 ; ISN 523 - add3 r0, r0, #(OPSPUT_LCD_PLD_IRQ_BASE) 524 - bra check_end 525 - .fillinsn 526 - check_end: 527 - #elif defined(CONFIG_PLAT_M32104UT) 528 - add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 529 - bnez r2, check_end 530 - ; read ICU status register of PLD 531 - seth r0, #high(PLD_ICUISTS) 532 - or3 r0, r0, #low(PLD_ICUISTS) 533 - lduh r0, @r0 534 - slli r0, #21 535 - srli r0, #27 ; ISN 536 - addi r0, #(M32104UT_PLD_IRQ_BASE) 537 - bra check_end 538 - .fillinsn 539 - check_end: 540 - #endif /* CONFIG_PLAT_M32104UT */ 541 bl do_IRQ 542 - #endif /* CONFIG_SMP */ 543 pop r14 544 seth r0, #shigh(M32R_ICU_IMASK_ADDR) 545 st r14, @(low(M32R_ICU_IMASK_ADDR),r0) 546 - #else 547 - #error no chip configuration 548 - #endif 549 ret_to_intr: 550 bra ret_from_intr 551
··· 290 */ 291 ENTRY(ei_handler) 292 #if defined(CONFIG_CHIP_M32700) 293 ; WORKAROUND: force to clear SM bit and use the kernel stack (SPI). 294 + SWITCH_TO_KERNEL_STACK 295 #endif 296 SAVE_ALL 297 mv r1, sp ; arg1(regs) 298 + ; GET_ICU_STATUS; 299 seth r0, #shigh(M32R_ICU_ISTS_ADDR) 300 ld r0, @(low(M32R_ICU_ISTS_ADDR),r0) 301 push r0 ··· 314 ;; IRQ exist check 315 #if defined(CONFIG_CHIP_M32700) 316 /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */ 317 + bnez r0, 0f 318 + ld24 r14, #0x00070000 319 + seth r0, #shigh(M32R_ICU_IMASK_ADDR) 320 + st r14, @(low(M32R_ICU_IMASK_ADDR),r0) 321 + bra 1f 322 + .fillinsn 323 + 0: 324 + #endif /* CONFIG_CHIP_M32700 */ 325 beqz r0, 1f ; if (!irq_num) goto exit 326 ;; IPI check 327 cmpi r0, #(M32R_IRQ_IPI0<<2) ; ISN < IPI0 check 328 bc 2f ··· 333 1: 334 addi sp, #4 335 bra ret_to_intr 336 .fillinsn 337 2: 338 srli r0, #2 339 + #else /* not CONFIG_SMP */ 340 srli r0, #22 ; r0(irq) 341 + #endif /* not CONFIG_SMP */ 342 + 343 + #if defined(CONFIG_PLAT_HAS_INT1ICU) 344 add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt 345 + bnez r2, 3f 346 + seth r0, #shigh(M32R_INT1ICU_ISTS) 347 + lduh r0, @(low(M32R_INT1ICU_ISTS),r0) ; bit10-6 : ISN 348 slli r0, #21 349 srli r0, #27 ; ISN 350 + addi r0, #(M32R_INT1ICU_IRQ_BASE) 351 bra check_end 352 .fillinsn 353 + 3: 354 + #endif /* CONFIG_PLAT_HAS_INT1ICU */ 355 + #if defined(CONFIG_PLAT_HAS_INT0ICU) 356 + add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt 357 + bnez r2, 4f 358 + seth r0, #shigh(M32R_INT0ICU_ISTS) 359 + lduh r0, @(low(M32R_INT0ICU_ISTS),r0) ; bit10-6 : ISN 360 slli r0, #21 361 + srli r0, #27 ; ISN 362 + addi r0, #(M32R_INT0ICU_IRQ_BASE) 363 bra check_end 364 .fillinsn 365 + 4: 366 + #endif /* CONFIG_PLAT_HAS_INT0ICU */ 367 + #if defined(CONFIG_PLAT_HAS_INT2ICU) 368 + add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt 369 + bnez r2, 5f 370 + seth r0, #shigh(M32R_INT2ICU_ISTS) 371 + lduh r0, @(low(M32R_INT2ICU_ISTS),r0) ; bit10-6 : ISN 372 slli r0, #21 373 + srli r0, #27 ; ISN 374 + addi r0, #(M32R_INT2ICU_IRQ_BASE) 375 + ; bra check_end 376 .fillinsn 377 + 5: 378 + #endif /* CONFIG_PLAT_HAS_INT2ICU */ 379 check_end: 380 bl do_IRQ 381 pop r14 382 seth r0, #shigh(M32R_ICU_IMASK_ADDR) 383 st r14, @(low(M32R_ICU_IMASK_ADDR),r0) 384 ret_to_intr: 385 bra ret_from_intr 386