dt-bindings: clock: sprd,sc9860-clk: Allow "reg" for gate clocks

The gate bindings have an artificial split between a "syscon" and clock
provider node. Allow "reg" properties so this split can be removed.

Reviewed-by: Chunyan Zhang <[e-mail]>
Link: https://patch.msgid.link/[e-mail]
Signed-off-by: Rob Herring (Arm) <[e-mail]>

Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml

···
         - reg
       properties:
         sprd,syscon: false
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - sprd,sc9860-agcp-gate
-              - sprd,sc9860-aon-gate
-              - sprd,sc9860-apahb-gate
-              - sprd,sc9860-apapb-gate
-              - sprd,sc9860-cam-gate
-              - sprd,sc9860-disp-gate
-              - sprd,sc9860-pll
-              - sprd,sc9860-pmu-gate
-              - sprd,sc9860-vsp-gate
-    then:
-      required:
-        - sprd,syscon
-      properties:
-        reg: false
 
 additionalProperties: false
 
···
     soc {
       #address-cells = <2>;
       #size-cells = <2>;
-
-      pmu-gate {
-        compatible = "sprd,sc9860-pmu-gate";
-        clocks = <&ext_26m>;
-        #clock-cells = <1>;
-        sprd,syscon = <&pmu_regs>;
-      };
 
       clock-controller@20000000 {
         compatible = "sprd,sc9860-ap-clk";