clk: si5351: Add DT property to enable PLL reset

Add optional output clock DT property to enable PLL reset when a clock
output is enabled.

Cc: Sebastian Hesselbarth <[e-mail]>
Cc: Rabeeh Khoury <[e-mail]>
Cc: Russell King <[e-mail]>
Signed-off-by: Sergej Sawazki <[e-mail]>
Signed-off-by: Stephen Boyd <[e-mail]>

Documentation/devicetree/bindings/clock/silabs,si5351.txt

···
 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
   divider.
 - silabs,pll-master: boolean, multisynth can change pll frequency.
+- silabs,pll-reset: boolean, clock output can reset its pll.
 - silabs,disable-state : clock output disable state, shall be
   0 = clock output is driven LOW when disabled
   1 = clock output is driven HIGH when disabled

drivers/clk/clk-si5351.c

···
 
 		pdata->clkout[num].pll_master =
 			of_property_read_bool(child, "silabs,pll-master");
+
+		pdata->clkout[num].pll_reset =
+			of_property_read_bool(child, "silabs,pll-reset");
 	}
 	client->dev.platform_data = pdata;
 

include/linux/platform_data/si5351.h

···
  * @multisynth_src: multisynth source clock
  * @clkout_src: clkout source clock
  * @pll_master: if true, clkout can also change pll rate
+ * @pll_reset: if true, clkout can reset its pll
  * @drive: output drive strength
  * @rate: initial clkout rate, or default if 0
  */
···
 	enum si5351_drive_strength drive;
 	enum si5351_disable_state disable_state;
 	bool pll_master;
+	bool pll_reset;
 	unsigned long rate;
 };