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dt-bindings: clock: qcom: add DISPCC clocks on SM4450
Add device tree bindings for the display clock controller on
Qualcomm SM4450 platform.
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-3-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Ajit Pandey
and committed by
Bjorn Andersson
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8400291e
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Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <quic_ajipan@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
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properties:
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compatible:
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const: qcom,sm4450-dispcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Display AHB clock source from GCC
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- description: sleep clock source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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clock-controller@af00000 {
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compatible = "qcom,sm4450-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&dsi0_phy_pll_out_byteclk>,
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<&dsi0_phy_pll_out_dsiclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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include/dt-bindings/clock/qcom,sm4450-dispcc.h
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include/dt-bindings/clock/qcom,sm4450-dispcc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
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/* DISP_CC clocks */
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#define DISP_CC_MDSS_AHB1_CLK 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_ESC0_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK_SRC 8
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#define DISP_CC_MDSS_MDP1_CLK 9
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#define DISP_CC_MDSS_MDP_CLK 10
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#define DISP_CC_MDSS_MDP_CLK_SRC 11
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#define DISP_CC_MDSS_MDP_LUT1_CLK 12
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#define DISP_CC_MDSS_MDP_LUT_CLK 13
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
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#define DISP_CC_MDSS_PCLK0_CLK 15
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
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#define DISP_CC_MDSS_ROT1_CLK 17
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#define DISP_CC_MDSS_ROT_CLK 18
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#define DISP_CC_MDSS_ROT_CLK_SRC 19
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#define DISP_CC_MDSS_RSCC_AHB_CLK 20
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
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#define DISP_CC_MDSS_VSYNC1_CLK 22
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#define DISP_CC_MDSS_VSYNC_CLK 23
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
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#define DISP_CC_PLL0 25
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#define DISP_CC_PLL1 26
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#define DISP_CC_SLEEP_CLK 27
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#define DISP_CC_SLEEP_CLK_SRC 28
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#define DISP_CC_XO_CLK 29
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#define DISP_CC_XO_CLK_SRC 30
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#define DISP_CC_MDSS_CORE_INT2_GDSC 1
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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#endif