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ARM: dts: sunxi: h3-h5: Move pinctrl of mmc0 from dts to dtsi

Most of the boards use the mmc0 pins and their attributes defined in
mmc0_pins_a. Let's default to those by moving the pinctrl attributes
to the dtsi file. This makes it easier to modify device trees in the
future as there is only one place to change the pinctrl attributes.

Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

authored by

Joonas Kylmälä and committed by
Maxime Ripard 50caa756 f8d5fe8f

+2 -32
-2
arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
··· 60 60 }; 61 61 62 62 &mmc0 { 63 - pinctrl-names = "default"; 64 - pinctrl-0 = <&mmc0_pins_a>; 65 63 vmmc-supply = <&reg_vcc3v3>; 66 64 bus-width = <4>; 67 65 /*
-2
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
··· 112 112 }; 113 113 114 114 &mmc0 { 115 - pinctrl-names = "default"; 116 - pinctrl-0 = <&mmc0_pins_a>; 117 115 vmmc-supply = <&reg_vcc3v3>; 118 116 bus-width = <4>; 119 117 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
··· 136 136 }; 137 137 138 138 &mmc0 { 139 - pinctrl-names = "default"; 140 - pinctrl-0 = <&mmc0_pins_a>; 141 139 vmmc-supply = <&reg_vcc3v3>; 142 140 bus-width = <4>; 143 141 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
··· 150 150 }; 151 151 152 152 &mmc0 { 153 - pinctrl-names = "default"; 154 - pinctrl-0 = <&mmc0_pins_a>; 155 153 vmmc-supply = <&reg_vcc_io>; 156 154 bus-width = <4>; 157 155 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
··· 80 80 }; 81 81 82 82 &mmc0 { 83 - pinctrl-names = "default"; 84 - pinctrl-0 = <&mmc0_pins_a>; 85 83 vmmc-supply = <&reg_vcc3v3>; 86 84 bus-width = <4>; 87 85 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
··· 96 96 &mmc0 { 97 97 bus-width = <4>; 98 98 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 99 - pinctrl-names = "default"; 100 - pinctrl-0 = <&mmc0_pins_a>; 101 99 status = "okay"; 102 100 vmmc-supply = <&reg_vcc3v3>; 103 101 };
-2
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
··· 132 132 }; 133 133 134 134 &mmc0 { 135 - pinctrl-names = "default"; 136 - pinctrl-0 = <&mmc0_pins_a>; 137 135 vmmc-supply = <&reg_vcc3v3>; 138 136 bus-width = <4>; 139 137 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
··· 106 106 }; 107 107 108 108 &mmc0 { 109 - pinctrl-names = "default"; 110 - pinctrl-0 = <&mmc0_pins_a>; 111 109 vmmc-supply = <&reg_vcc3v3>; 112 110 bus-width = <4>; 113 111 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
··· 106 106 }; 107 107 108 108 &mmc0 { 109 - pinctrl-names = "default"; 110 - pinctrl-0 = <&mmc0_pins_a>; 111 109 vmmc-supply = <&reg_vcc3v3>; 112 110 bus-width = <4>; 113 111 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
··· 128 128 }; 129 129 130 130 &mmc0 { 131 - pinctrl-names = "default"; 132 - pinctrl-0 = <&mmc0_pins_a>; 133 131 vmmc-supply = <&reg_vcc3v3>; 134 132 bus-width = <4>; 135 133 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+2
arch/arm/boot/dts/sunxi-h3-h5.dtsi
··· 141 141 mmc0: mmc@1c0f000 { 142 142 /* compatible and clocks are in per SoC .dtsi file */ 143 143 reg = <0x01c0f000 0x1000>; 144 + pinctrl-names = "default"; 145 + pinctrl-0 = <&mmc0_pins_a>; 144 146 resets = <&ccu RST_BUS_MMC0>; 145 147 reset-names = "ahb"; 146 148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-2
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
··· 151 151 }; 152 152 153 153 &mmc0 { 154 - pinctrl-names = "default"; 155 - pinctrl-0 = <&mmc0_pins_a>; 156 154 vmmc-supply = <&reg_vcc3v3>; 157 155 bus-width = <4>; 158 156 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
··· 126 126 }; 127 127 128 128 &mmc0 { 129 - pinctrl-names = "default"; 130 - pinctrl-0 = <&mmc0_pins_a>; 131 129 vmmc-supply = <&reg_vcc3v3>; 132 130 bus-width = <4>; 133 131 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
··· 160 160 }; 161 161 162 162 &mmc0 { 163 - pinctrl-names = "default"; 164 - pinctrl-0 = <&mmc0_pins_a>; 165 163 vmmc-supply = <&reg_vcc3v3>; 166 164 bus-width = <4>; 167 165 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
··· 167 167 }; 168 168 169 169 &mmc0 { 170 - pinctrl-names = "default"; 171 - pinctrl-0 = <&mmc0_pins_a>; 172 170 vmmc-supply = <&reg_vcc3v3>; 173 171 bus-width = <4>; 174 172 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-2
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
··· 74 74 }; 75 75 76 76 &mmc0 { 77 - pinctrl-names = "default"; 78 - pinctrl-0 = <&mmc0_pins_a>; 79 77 vmmc-supply = <&reg_vcc3v3>; 80 78 bus-width = <4>; 81 79 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;