drm/amdgpu: Add additional DCE6 SCL registers

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 6 months ago 50729632 b2ec5ca9

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

dce

dce_6_0_d.h

dce_6_0_sh_mask.h

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h

··· 4115 4115 #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 4116 4116 #define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 4117 4117 #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 4118 + #define mmSCL0_SCL_SCALER_ENABLE 0x1B42 4118 4119 #define mmSCL0_SCL_CONTROL 0x1B44 4119 4120 #define mmSCL0_SCL_DEBUG 0x1B6A 4120 4121 #define mmSCL0_SCL_DEBUG2 0x1B69 ··· 4145 4144 #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 4146 4145 #define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 4147 4146 #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 4147 + #define mmSCL1_SCL_SCALER_ENABLE 0x1E42 4148 4148 #define mmSCL1_SCL_CONTROL 0x1E44 4149 4149 #define mmSCL1_SCL_DEBUG 0x1E6A 4150 4150 #define mmSCL1_SCL_DEBUG2 0x1E69 ··· 4175 4173 #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 4176 4174 #define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 4177 4175 #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 4176 + #define mmSCL2_SCL_SCALER_ENABLE 0x4142 4178 4177 #define mmSCL2_SCL_CONTROL 0x4144 4179 4178 #define mmSCL2_SCL_DEBUG 0x416A 4180 4179 #define mmSCL2_SCL_DEBUG2 0x4169 ··· 4205 4202 #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 4206 4203 #define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 4207 4204 #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 4205 + #define mmSCL3_SCL_SCALER_ENABLE 0x4442 4208 4206 #define mmSCL3_SCL_CONTROL 0x4444 4209 4207 #define mmSCL3_SCL_DEBUG 0x446A 4210 4208 #define mmSCL3_SCL_DEBUG2 0x4469 ··· 4235 4231 #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 4236 4232 #define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 4237 4233 #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 4234 + #define mmSCL4_SCL_SCALER_ENABLE 0x4742 4238 4235 #define mmSCL4_SCL_CONTROL 0x4744 4239 4236 #define mmSCL4_SCL_DEBUG 0x476A 4240 4237 #define mmSCL4_SCL_DEBUG2 0x4769 ··· 4265 4260 #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 4266 4261 #define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 4267 4262 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 4263 + #define mmSCL5_SCL_SCALER_ENABLE 0x4A42 4268 4264 #define mmSCL5_SCL_CONTROL 0x4A44 4269 4265 #define mmSCL5_SCL_DEBUG 0x4A6A 4270 4266 #define mmSCL5_SCL_DEBUG2 0x4A69 ··· 4293 4287 #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 4294 4288 #define mmSCL_COEF_RAM_SELECT 0x1B40 4295 4289 #define mmSCL_COEF_RAM_TAP_DATA 0x1B41 4290 + #define mmSCL_SCALER_ENABLE 0x1B42 4296 4291 #define mmSCL_CONTROL 0x1B44 4297 4292 #define mmSCL_DEBUG 0x1B6A 4298 4293 #define mmSCL_DEBUG2 0x1B69

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h

··· 8650 8650 #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 8651 8651 #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L 8652 8652 #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 8653 + #define SCL_SCALER_ENABLE__SCL_SCALE_EN_MASK 0x00000001L 8654 + #define SCL_SCALER_ENABLE__SCL_SCALE_EN__SHIFT 0x00000000 8653 8655 #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L 8654 8656 #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 8655 8657 #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L