tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge branch 'fixes' into next

Ulf Hansson 506f4399 ade8e9d3

+30 -34
+19 -32
drivers/mmc/host/sdhci-of-arasan.c
··· 30 30 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 31 31 32 32 #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 33 + #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF 34 + 33 35 #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC 36 + #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F 34 37 35 38 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 36 39 #define VENDOR_ENHANCED_STROBE BIT(0) ··· 603 600 u8 tap_delay, tap_max = 0; 604 601 int ret; 605 602 606 - /* 607 - * This is applicable for SDHCI_SPEC_300 and above 608 - * ZynqMP does not set phase for <=25MHz clock. 609 - * If degrees is zero, no need to do anything. 610 - */ 611 - if (host->version < SDHCI_SPEC_300 || 612 - host->timing == MMC_TIMING_LEGACY || 613 - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) 603 + /* This is applicable for SDHCI_SPEC_300 and above */ 604 + if (host->version < SDHCI_SPEC_300) 614 605 return 0; 615 606 616 607 switch (host->timing) { ··· 634 637 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay); 635 638 if (ret) 636 639 pr_err("Error setting Output Tap Delay\n"); 640 + 641 + /* Release DLL Reset */ 642 + zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE); 637 643 638 644 return ret; 639 645 } ··· 668 668 u8 tap_delay, tap_max = 0; 669 669 int ret; 670 670 671 - /* 672 - * This is applicable for SDHCI_SPEC_300 and above 673 - * ZynqMP does not set phase for <=25MHz clock. 674 - * If degrees is zero, no need to do anything. 675 - */ 676 - if (host->version < SDHCI_SPEC_300 || 677 - host->timing == MMC_TIMING_LEGACY || 678 - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) 671 + /* This is applicable for SDHCI_SPEC_300 and above */ 672 + if (host->version < SDHCI_SPEC_300) 679 673 return 0; 674 + 675 + /* Assert DLL Reset */ 676 + zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT); 680 677 681 678 switch (host->timing) { 682 679 case MMC_TIMING_MMC_HS: ··· 730 733 struct sdhci_host *host = sdhci_arasan->host; 731 734 u8 tap_delay, tap_max = 0; 732 735 733 - /* 734 - * This is applicable for SDHCI_SPEC_300 and above 735 - * Versal does not set phase for <=25MHz clock. 736 - * If degrees is zero, no need to do anything. 737 - */ 738 - if (host->version < SDHCI_SPEC_300 || 739 - host->timing == MMC_TIMING_LEGACY || 740 - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) 736 + /* This is applicable for SDHCI_SPEC_300 and above */ 737 + if (host->version < SDHCI_SPEC_300) 741 738 return 0; 742 739 743 740 switch (host->timing) { ··· 764 773 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); 765 774 regval |= SDHCI_OTAPDLY_ENABLE; 766 775 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); 776 + regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK; 767 777 regval |= tap_delay; 768 778 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); 769 779 } ··· 796 804 struct sdhci_host *host = sdhci_arasan->host; 797 805 u8 tap_delay, tap_max = 0; 798 806 799 - /* 800 - * This is applicable for SDHCI_SPEC_300 and above 801 - * Versal does not set phase for <=25MHz clock. 802 - * If degrees is zero, no need to do anything. 803 - */ 804 - if (host->version < SDHCI_SPEC_300 || 805 - host->timing == MMC_TIMING_LEGACY || 806 - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) 807 + /* This is applicable for SDHCI_SPEC_300 and above */ 808 + if (host->version < SDHCI_SPEC_300) 807 809 return 0; 808 810 809 811 switch (host->timing) { ··· 832 846 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); 833 847 regval |= SDHCI_ITAPDLY_ENABLE; 834 848 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); 849 + regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK; 835 850 regval |= tap_delay; 836 851 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); 837 852 regval &= ~SDHCI_ITAPDLY_CHGWIN;
+11 -2
drivers/mmc/host/sdhci-pci-core.c
··· 665 665 } 666 666 } 667 667 668 + static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 669 + unsigned int timing) 670 + { 671 + /* Set UHS timing to SDR25 for High Speed mode */ 672 + if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 673 + timing = MMC_TIMING_UHS_SDR25; 674 + sdhci_set_uhs_signaling(host, timing); 675 + } 676 + 668 677 #define INTEL_HS400_ES_REG 0x78 669 678 #define INTEL_HS400_ES_BIT BIT(0) 670 679 ··· 730 721 .enable_dma = sdhci_pci_enable_dma, 731 722 .set_bus_width = sdhci_set_bus_width, 732 723 .reset = sdhci_reset, 733 - .set_uhs_signaling = sdhci_set_uhs_signaling, 724 + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 734 725 .hw_reset = sdhci_pci_hw_reset, 735 726 }; 736 727 ··· 740 731 .enable_dma = sdhci_pci_enable_dma, 741 732 .set_bus_width = sdhci_set_bus_width, 742 733 .reset = sdhci_cqhci_reset, 743 - .set_uhs_signaling = sdhci_set_uhs_signaling, 734 + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 744 735 .hw_reset = sdhci_pci_hw_reset, 745 736 .irq = sdhci_cqhci_irq, 746 737 };