tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'clk-fixes' into clk-next

* clk-fixes:
clk: rockchip: rk3368: fix some clock gates
clk: rockchip: rk3036: rename emac ext source clock
clk: rockchip: rk3036: fix the div offset for emac clock
clk: rockchip: rk3036: fix uarts clock error
clk: rockchip: rk3036: fix the FLAGs for clock mux

Stephen Boyd 4fcad2ea 9849fadf

+27 -27
+1 -1
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
··· 30 30 clock-output-names: 31 31 - "xin24m" - crystal input - required, 32 32 - "ext_i2s" - external I2S clock - optional, 33 - - "ext_gmac" - external GMAC clock - optional 33 + - "rmii_clkin" - external EMAC clock - optional 34 34 35 35 Example: Clock controller node: 36 36
+13 -13
drivers/clk/rockchip/clk-rk3036.c
··· 133 133 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 134 134 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 135 135 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 136 - PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" }; 136 + PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" }; 137 137 PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" }; 138 138 139 139 static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = { ··· 224 224 RK2928_CLKGATE_CON(2), 2, GFLAGS), 225 225 226 226 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, 227 - RK2928_CLKSEL_CON(2), 4, 1, DFLAGS, 227 + RK2928_CLKSEL_CON(2), 4, 1, MFLAGS, 228 228 RK2928_CLKGATE_CON(1), 0, GFLAGS), 229 229 COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED, 230 - RK2928_CLKSEL_CON(2), 5, 1, DFLAGS, 230 + RK2928_CLKSEL_CON(2), 5, 1, MFLAGS, 231 231 RK2928_CLKGATE_CON(1), 1, GFLAGS), 232 232 COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED, 233 - RK2928_CLKSEL_CON(2), 6, 1, DFLAGS, 233 + RK2928_CLKSEL_CON(2), 6, 1, MFLAGS, 234 234 RK2928_CLKGATE_CON(2), 4, GFLAGS), 235 235 COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED, 236 - RK2928_CLKSEL_CON(2), 7, 1, DFLAGS, 236 + RK2928_CLKSEL_CON(2), 7, 1, MFLAGS, 237 237 RK2928_CLKGATE_CON(2), 5, GFLAGS), 238 238 239 239 MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, ··· 242 242 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 243 243 RK2928_CLKGATE_CON(1), 8, GFLAGS), 244 244 COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0, 245 - RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 246 - RK2928_CLKGATE_CON(1), 8, GFLAGS), 245 + RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, 246 + RK2928_CLKGATE_CON(1), 10, GFLAGS), 247 247 COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0, 248 - RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 249 - RK2928_CLKGATE_CON(1), 8, GFLAGS), 248 + RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, 249 + RK2928_CLKGATE_CON(1), 12, GFLAGS), 250 250 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 251 251 RK2928_CLKSEL_CON(17), 0, 252 252 RK2928_CLKGATE_CON(1), 9, GFLAGS, ··· 279 279 RK2928_CLKGATE_CON(3), 2, GFLAGS), 280 280 281 281 COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0, 282 - RK2928_CLKSEL_CON(12), 8, 2, DFLAGS, 282 + RK2928_CLKSEL_CON(12), 8, 2, MFLAGS, 283 283 RK2928_CLKGATE_CON(2), 11, GFLAGS), 284 284 DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0, 285 285 RK2928_CLKSEL_CON(11), 0, 7, DFLAGS), 286 286 287 287 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 288 - RK2928_CLKSEL_CON(12), 10, 2, DFLAGS, 288 + RK2928_CLKSEL_CON(12), 10, 2, MFLAGS, 289 289 RK2928_CLKGATE_CON(2), 13, GFLAGS), 290 290 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 291 291 RK2928_CLKSEL_CON(11), 8, 7, DFLAGS), ··· 344 344 RK2928_CLKGATE_CON(10), 5, GFLAGS), 345 345 346 346 COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, 347 - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS), 347 + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), 348 348 MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, 349 349 RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), 350 350 351 351 COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0, 352 - RK2928_CLKSEL_CON(21), 9, 5, DFLAGS, 352 + RK2928_CLKSEL_CON(21), 4, 5, DFLAGS, 353 353 RK2928_CLKGATE_CON(2), 6, GFLAGS), 354 354 355 355 MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
+13 -13
drivers/clk/rockchip/clk-rk3368.c
··· 780 780 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS), 781 781 782 782 /* pclk_pd_alive gates */ 783 - GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 8, GFLAGS), 784 - GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 7, GFLAGS), 785 - GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 12, GFLAGS), 786 - GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 11, GFLAGS), 787 - GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 3, GFLAGS), 788 - GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 2, GFLAGS), 789 - GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 1, GFLAGS), 783 + GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS), 784 + GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS), 785 + GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS), 786 + GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS), 787 + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS), 788 + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS), 789 + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS), 790 790 791 791 /* 792 792 * pclk_vio gates ··· 796 796 GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS), 797 797 798 798 /* pclk_pd_pmu gates */ 799 - GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 0, GFLAGS), 800 - GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS), 801 - GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 3, GFLAGS), 802 - GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS), 803 - GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 1, GFLAGS), 804 - GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS), 799 + GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS), 800 + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS), 801 + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS), 802 + GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS), 803 + GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS), 804 + GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS), 805 805 806 806 /* timer gates */ 807 807 GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),