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dt-bindings: clock: qcom: Document the X1E80100 Display Clock Controller
Add bindings documentation for the X1E80100 Display Clock Controller.
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-2-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Rajendra Nayak
and committed by
Bjorn Andersson
4f70a09b
c984dde8
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Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
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See also:
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- include/dt-bindings/clock/qcom,sm8550-dispcc.h
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- include/dt-bindings/clock/qcom,sm8650-dispcc.h
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- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,sm8550-dispcc
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- qcom,sm8650-dispcc
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- qcom,x1e80100-dispcc
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clocks:
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items:
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include/dt-bindings/clock/qcom,x1e80100-dispcc.h
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include/dt-bindings/clock/qcom,x1e80100-dispcc.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
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#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
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/* DISP_CC clocks */
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#define DISP_CC_MDSS_ACCU_CLK 0
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#define DISP_CC_MDSS_AHB1_CLK 1
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#define DISP_CC_MDSS_AHB_CLK 2
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#define DISP_CC_MDSS_AHB_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_CLK 4
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
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#define DISP_CC_MDSS_BYTE1_CLK 8
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
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#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
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#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
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#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
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#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
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#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
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#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
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#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
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#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
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#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
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#define DISP_CC_MDSS_DPTX1_LINK_CLK 25
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#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26
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#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27
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#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32
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#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33
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#define DISP_CC_MDSS_DPTX2_AUX_CLK 34
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#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35
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#define DISP_CC_MDSS_DPTX2_LINK_CLK 36
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#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37
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#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38
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#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43
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#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44
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#define DISP_CC_MDSS_DPTX3_AUX_CLK 45
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#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46
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#define DISP_CC_MDSS_DPTX3_LINK_CLK 47
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#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48
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#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49
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#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52
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#define DISP_CC_MDSS_ESC0_CLK 53
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#define DISP_CC_MDSS_ESC0_CLK_SRC 54
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#define DISP_CC_MDSS_ESC1_CLK 55
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#define DISP_CC_MDSS_ESC1_CLK_SRC 56
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#define DISP_CC_MDSS_MDP1_CLK 57
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#define DISP_CC_MDSS_MDP_CLK 58
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#define DISP_CC_MDSS_MDP_CLK_SRC 59
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#define DISP_CC_MDSS_MDP_LUT1_CLK 60
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#define DISP_CC_MDSS_MDP_LUT_CLK 61
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62
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#define DISP_CC_MDSS_PCLK0_CLK 63
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 64
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#define DISP_CC_MDSS_PCLK1_CLK 65
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 66
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#define DISP_CC_MDSS_RSCC_AHB_CLK 67
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68
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#define DISP_CC_MDSS_VSYNC1_CLK 69
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#define DISP_CC_MDSS_VSYNC_CLK 70
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 71
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#define DISP_CC_PLL0 72
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#define DISP_CC_PLL1 73
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#define DISP_CC_SLEEP_CLK 74
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#define DISP_CC_SLEEP_CLK_SRC 75
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#define DISP_CC_XO_CLK 76
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#define DISP_CC_XO_CLK_SRC 77
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#define MDSS_INT2_GDSC 1
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#endif