commit 4f4e65d2484811210a2826fa9d59712c7fcf1b49

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (25 commits)
OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timer
PM debug: Fix warning when no CONFIG_DEBUG_FS
OMAP3: PM: DSS PM_WKEN to refill DMA
OMAP: timekeeping: time should not stop during suspend
OMAP3: PM: Force write last pad config register into save area
OMAP: omap3_pm_get_suspend_state() error ignored in pwrdm_suspend_get()
OMAP3: PM: Enable wake-up from McBSP2, 3 and 4 modules
OMAP3: PM debug: fix build error when !CONFIG_DEBUG_FS
OMAP3: PM: Removing redundant and potentially dangerous PRCM configration
OMAP3: Fixed ARM aux ctrl register save/restore
OMAP3: CPUidle: Fixed timer resolution
OMAP3: PM: Remove duplicate code blocks
OMAP3: PM: Disable interrupt controller AUTOIDLE before WFI
OMAP3: PM: Enable system control module autoidle
OMAP3: PM: Ack pending interrupts before entering suspend
omap: Enable GPMC clock in gpmc_init
OMAP1 clock: fix for "BUG: spinlock lockup on CPU#0"
OMAP4: clocks: Fix the clksel_rate struct DPLL divs
OMAP4: PRCM: Fix the base address for CHIRONSS reg defines
OMAP: dma_chan[lch_head].flag & OMAP_DMA_ACTIVE tested twice in omap_dma_unlink_lch()
...

Linus Torvalds 16 years ago 4f4e65d2 f6760aa0

+229 -131

23 changed files

expand all

unified split

arch

arm

mach-omap1

clock.c

mach-omap2

clock34xx_data.c

clock44xx_data.c

cpuidle34xx.c

gpmc.c

id.c

irq.c

mux.c

mux.h

omap_hwmod.c

pm-debug.c

pm.h

pm34xx.c

prcm.c

prm.h

prm44xx.h

sleep34xx.S

plat-omap

common.c

dma.c

dmtimer.c

include

plat

cpu.h

irqs.h

omap_hwmod.h

+3 -3

arch/arm/mach-omap1/clock.c

··· 214 214 struct mpu_rate * ptr; 215 215 unsigned long dpll1_rate, ref_rate; 216 216 217 - dpll1_rate = clk_get_rate(ck_dpll1_p); 218 - ref_rate = clk_get_rate(ck_ref_p); 217 + dpll1_rate = ck_dpll1_p->rate; 218 + ref_rate = ck_ref_p->rate; 219 219 220 220 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 221 221 if (ptr->xtal != ref_rate) ··· 306 306 long highest_rate; 307 307 unsigned long ref_rate; 308 308 309 - ref_rate = clk_get_rate(ck_ref_p); 309 + ref_rate = ck_ref_p->rate; 310 310 311 311 highest_rate = -EINVAL; 312 312

-4

arch/arm/mach-omap2/clock34xx_data.c

··· 671 671 .name = "dpll4_m3x2_ck", 672 672 .ops = &clkops_omap2_dflt_wait, 673 673 .parent = &dpll4_m3_ck, 674 - .init = &omap2_init_clksel_parent, 675 674 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 676 675 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 677 676 .flags = INVERT_ENABLE, ··· 810 811 .name = "dpll4_m6x2_ck", 811 812 .ops = &clkops_omap2_dflt_wait, 812 813 .parent = &dpll4_m6_ck, 813 - .init = &omap2_init_clksel_parent, 814 814 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 815 815 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 816 816 .flags = INVERT_ENABLE, ··· 1045 1047 .name = "iva2_ck", 1046 1048 .ops = &clkops_omap2_dflt_wait, 1047 1049 .parent = &dpll2_m2_ck, 1048 - .init = &omap2_init_clksel_parent, 1049 1050 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1050 1051 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1051 1052 .clkdm_name = "iva2_clkdm", ··· 1118 1121 .name = "gfx_l3_ck", 1119 1122 .ops = &clkops_omap2_dflt_wait, 1120 1123 .parent = &l3_ick, 1121 - .init = &omap2_init_clksel_parent, 1122 1124 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1123 1125 .enable_bit = OMAP_EN_GFX_SHIFT, 1124 1126 .recalc = &followparent_recalc,

+31 -31

arch/arm/mach-omap2/clock44xx_data.c

··· 346 346 }; 347 347 348 348 static const struct clksel_rate div31_1to31_rates[] = { 349 - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 350 - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 351 - { .div = 3, .val = 2, .flags = RATE_IN_4430 }, 352 - { .div = 4, .val = 3, .flags = RATE_IN_4430 }, 353 - { .div = 5, .val = 4, .flags = RATE_IN_4430 }, 354 - { .div = 6, .val = 5, .flags = RATE_IN_4430 }, 355 - { .div = 7, .val = 6, .flags = RATE_IN_4430 }, 356 - { .div = 8, .val = 7, .flags = RATE_IN_4430 }, 357 - { .div = 9, .val = 8, .flags = RATE_IN_4430 }, 358 - { .div = 10, .val = 9, .flags = RATE_IN_4430 }, 359 - { .div = 11, .val = 10, .flags = RATE_IN_4430 }, 360 - { .div = 12, .val = 11, .flags = RATE_IN_4430 }, 361 - { .div = 13, .val = 12, .flags = RATE_IN_4430 }, 362 - { .div = 14, .val = 13, .flags = RATE_IN_4430 }, 363 - { .div = 15, .val = 14, .flags = RATE_IN_4430 }, 364 - { .div = 16, .val = 15, .flags = RATE_IN_4430 }, 365 - { .div = 17, .val = 16, .flags = RATE_IN_4430 }, 366 - { .div = 18, .val = 17, .flags = RATE_IN_4430 }, 367 - { .div = 19, .val = 18, .flags = RATE_IN_4430 }, 368 - { .div = 20, .val = 19, .flags = RATE_IN_4430 }, 369 - { .div = 21, .val = 20, .flags = RATE_IN_4430 }, 370 - { .div = 22, .val = 21, .flags = RATE_IN_4430 }, 371 - { .div = 23, .val = 22, .flags = RATE_IN_4430 }, 372 - { .div = 24, .val = 23, .flags = RATE_IN_4430 }, 373 - { .div = 25, .val = 24, .flags = RATE_IN_4430 }, 374 - { .div = 26, .val = 25, .flags = RATE_IN_4430 }, 375 - { .div = 27, .val = 26, .flags = RATE_IN_4430 }, 376 - { .div = 28, .val = 27, .flags = RATE_IN_4430 }, 377 - { .div = 29, .val = 28, .flags = RATE_IN_4430 }, 378 - { .div = 30, .val = 29, .flags = RATE_IN_4430 }, 379 - { .div = 31, .val = 30, .flags = RATE_IN_4430 }, 349 + { .div = 1, .val = 1, .flags = RATE_IN_4430 }, 350 + { .div = 2, .val = 2, .flags = RATE_IN_4430 }, 351 + { .div = 3, .val = 3, .flags = RATE_IN_4430 }, 352 + { .div = 4, .val = 4, .flags = RATE_IN_4430 }, 353 + { .div = 5, .val = 5, .flags = RATE_IN_4430 }, 354 + { .div = 6, .val = 6, .flags = RATE_IN_4430 }, 355 + { .div = 7, .val = 7, .flags = RATE_IN_4430 }, 356 + { .div = 8, .val = 8, .flags = RATE_IN_4430 }, 357 + { .div = 9, .val = 9, .flags = RATE_IN_4430 }, 358 + { .div = 10, .val = 10, .flags = RATE_IN_4430 }, 359 + { .div = 11, .val = 11, .flags = RATE_IN_4430 }, 360 + { .div = 12, .val = 12, .flags = RATE_IN_4430 }, 361 + { .div = 13, .val = 13, .flags = RATE_IN_4430 }, 362 + { .div = 14, .val = 14, .flags = RATE_IN_4430 }, 363 + { .div = 15, .val = 15, .flags = RATE_IN_4430 }, 364 + { .div = 16, .val = 16, .flags = RATE_IN_4430 }, 365 + { .div = 17, .val = 17, .flags = RATE_IN_4430 }, 366 + { .div = 18, .val = 18, .flags = RATE_IN_4430 }, 367 + { .div = 19, .val = 19, .flags = RATE_IN_4430 }, 368 + { .div = 20, .val = 20, .flags = RATE_IN_4430 }, 369 + { .div = 21, .val = 21, .flags = RATE_IN_4430 }, 370 + { .div = 22, .val = 22, .flags = RATE_IN_4430 }, 371 + { .div = 23, .val = 23, .flags = RATE_IN_4430 }, 372 + { .div = 24, .val = 24, .flags = RATE_IN_4430 }, 373 + { .div = 25, .val = 25, .flags = RATE_IN_4430 }, 374 + { .div = 26, .val = 26, .flags = RATE_IN_4430 }, 375 + { .div = 27, .val = 27, .flags = RATE_IN_4430 }, 376 + { .div = 28, .val = 28, .flags = RATE_IN_4430 }, 377 + { .div = 29, .val = 29, .flags = RATE_IN_4430 }, 378 + { .div = 30, .val = 30, .flags = RATE_IN_4430 }, 379 + { .div = 31, .val = 31, .flags = RATE_IN_4430 }, 380 380 { .div = 0 }, 381 381 }; 382 382

+1 -1

arch/arm/mach-omap2/cpuidle34xx.c

··· 137 137 local_irq_enable(); 138 138 local_fiq_enable(); 139 139 140 - return (u32)timespec_to_ns(&ts_idle)/1000; 140 + return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC; 141 141 } 142 142 143 143 /**

arch/arm/mach-omap2/gpmc.c

··· 534 534 BUG(); 535 535 } 536 536 537 + clk_enable(gpmc_l3_clk); 538 + 537 539 l = gpmc_read_reg(GPMC_REVISION); 538 540 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 539 541 /* Set smart idle mode and automatic L3 clock gating */

+23 -18

arch/arm/mach-omap2/id.c

··· 188 188 u16 hawkeye; 189 189 u8 rev; 190 190 191 + omap_chip.oc = CHIP_IS_OMAP3430; 192 + 191 193 /* 192 194 * We cannot access revision registers on ES1.0. 193 195 * If the processor type is Cortex-A8 and the revision is 0x0 ··· 198 196 cpuid = read_cpuid(CPUID_ID); 199 197 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 200 198 omap_revision = OMAP3430_REV_ES1_0; 199 + omap_chip.oc |= CHIP_IS_OMAP3430ES1; 201 200 return; 202 201 } 203 202 ··· 219 216 case 0: /* Take care of early samples */ 220 217 case 1: 221 218 omap_revision = OMAP3430_REV_ES2_0; 219 + omap_chip.oc |= CHIP_IS_OMAP3430ES2; 222 220 break; 223 221 case 2: 224 222 omap_revision = OMAP3430_REV_ES2_1; 223 + omap_chip.oc |= CHIP_IS_OMAP3430ES2; 225 224 break; 226 225 case 3: 227 226 omap_revision = OMAP3430_REV_ES3_0; 227 + omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; 228 228 break; 229 229 case 4: 230 + omap_revision = OMAP3430_REV_ES3_1; 231 + omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 232 + break; 233 + case 7: 230 234 /* FALLTHROUGH */ 231 235 default: 232 236 /* Use the latest known revision as default */ 233 - omap_revision = OMAP3430_REV_ES3_1; 237 + omap_revision = OMAP3430_REV_ES3_1_2; 238 + 239 + /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */ 240 + omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 234 241 } 235 242 break; 236 243 case 0xb868: ··· 248 235 * 249 236 * Set the device to be OMAP3505 here. Actual device 250 237 * is identified later based on the features. 238 + * 239 + * REVISIT: AM3505/AM3517 should have their own CHIP_IS 251 240 */ 252 241 omap_revision = OMAP3505_REV(rev); 242 + omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 253 243 break; 254 244 case 0xb891: 255 245 /* FALLTHROUGH */ 256 246 default: 257 247 /* Unknown default to latest silicon rev as default*/ 258 248 omap_revision = OMAP3630_REV_ES1_0; 249 + omap_chip.oc |= CHIP_IS_OMAP3630ES1; 259 250 } 260 251 } 261 252 ··· 377 360 omap3_check_revision(); 378 361 omap3_check_features(); 379 362 omap3_cpuinfo(); 363 + return; 380 364 } else if (cpu_is_omap44xx()) { 381 365 omap4_check_revision(); 382 366 return; ··· 392 374 if (cpu_is_omap243x()) { 393 375 /* Currently only supports 2430ES2.1 and 2430-all */ 394 376 omap_chip.oc |= CHIP_IS_OMAP2430; 377 + return; 395 378 } else if (cpu_is_omap242x()) { 396 379 /* Currently only supports 2420ES2.1.1 and 2420-all */ 397 380 omap_chip.oc |= CHIP_IS_OMAP2420; 398 - } else if (cpu_is_omap3505() || cpu_is_omap3517()) { 399 - omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1; 400 - } else if (cpu_is_omap343x()) { 401 - omap_chip.oc = CHIP_IS_OMAP3430; 402 - if (omap_rev() == OMAP3430_REV_ES1_0) 403 - omap_chip.oc |= CHIP_IS_OMAP3430ES1; 404 - else if (omap_rev() >= OMAP3430_REV_ES2_0 && 405 - omap_rev() <= OMAP3430_REV_ES2_1) 406 - omap_chip.oc |= CHIP_IS_OMAP3430ES2; 407 - else if (omap_rev() == OMAP3430_REV_ES3_0) 408 - omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; 409 - else if (omap_rev() == OMAP3430_REV_ES3_1) 410 - omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 411 - else if (omap_rev() == OMAP3630_REV_ES1_0) 412 - omap_chip.oc |= CHIP_IS_OMAP3630ES1; 413 - } else { 414 - pr_err("Uninitialized omap_chip, please fix!\n"); 381 + return; 415 382 } 383 + 384 + pr_err("Uninitialized omap_chip, please fix!\n"); 416 385 } 417 386 418 387 /*

+18

arch/arm/mach-omap2/irq.c

··· 274 274 } 275 275 /* MIRs are saved and restore with other PRCM registers */ 276 276 } 277 + 278 + void omap3_intc_suspend(void) 279 + { 280 + /* A pending interrupt would prevent OMAP from entering suspend */ 281 + omap_ack_irq(0); 282 + } 283 + 284 + void omap3_intc_prepare_idle(void) 285 + { 286 + /* Disable autoidle as it can stall interrupt controller */ 287 + intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); 288 + } 289 + 290 + void omap3_intc_resume_idle(void) 291 + { 292 + /* Re-enable autoidle */ 293 + intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG); 294 + } 277 295 #endif /* CONFIG_ARCH_OMAP3 */

+15 -12

arch/arm/mach-omap2/mux.c

··· 51 51 static unsigned long mux_phys; 52 52 static void __iomem *mux_base; 53 53 54 - static inline u16 omap_mux_read(u16 reg) 54 + u16 omap_mux_read(u16 reg) 55 55 { 56 56 if (cpu_is_omap24xx()) 57 57 return __raw_readb(mux_base + reg); ··· 59 59 return __raw_readw(mux_base + reg); 60 60 } 61 61 62 - static inline void omap_mux_write(u16 val, u16 reg) 62 + void omap_mux_write(u16 val, u16 reg) 63 63 { 64 64 if (cpu_is_omap24xx()) 65 65 __raw_writeb(val, mux_base + reg); 66 66 else 67 67 __raw_writew(val, mux_base + reg); 68 + } 69 + 70 + void omap_mux_write_array(struct omap_board_mux *board_mux) 71 + { 72 + while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { 73 + omap_mux_write(board_mux->value, board_mux->reg_offset); 74 + board_mux++; 75 + } 68 76 } 69 77 70 78 #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) ··· 841 833 kfree(options); 842 834 } 843 835 844 - static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux) 845 - { 846 - while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { 847 - omap_mux_write(board_mux->value, board_mux->reg_offset); 848 - board_mux++; 849 - } 850 - } 851 - 852 836 static int __init omap_mux_copy_names(struct omap_mux *src, 853 837 struct omap_mux *dst) 854 838 { ··· 998 998 omap_mux_package_fixup(package_subset, superset); 999 999 if (package_balls) 1000 1000 omap_mux_package_init_balls(package_balls, superset); 1001 - omap_mux_set_cmdline_signals(); 1002 - omap_mux_set_board_signals(board_mux); 1003 1001 #endif 1004 1002 1005 1003 omap_mux_init_list(superset); 1004 + 1005 + #ifdef CONFIG_OMAP_MUX 1006 + omap_mux_set_cmdline_signals(); 1007 + omap_mux_write_array(board_mux); 1008 + #endif 1006 1009 1007 1010 return 0; 1008 1011 }

+24

arch/arm/mach-omap2/mux.h

··· 147 147 void omap_mux_set_gpio(u16 val, int gpio); 148 148 149 149 /** 150 + * omap_mux_read() - read mux register 151 + * @mux_offset: Offset of the mux register 152 + * 153 + */ 154 + u16 omap_mux_read(u16 mux_offset); 155 + 156 + /** 157 + * omap_mux_write() - write mux register 158 + * @val: New mux register value 159 + * @mux_offset: Offset of the mux register 160 + * 161 + * This should be only needed for dynamic remuxing of non-gpio signals. 162 + */ 163 + void omap_mux_write(u16 val, u16 mux_offset); 164 + 165 + /** 166 + * omap_mux_write_array() - write an array of mux registers 167 + * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR 168 + * 169 + * This should be only needed for dynamic remuxing of non-gpio signals. 170 + */ 171 + void omap_mux_write_array(struct omap_board_mux *board_mux); 172 + 173 + /** 150 174 * omap3_mux_init() - initialize mux system with board specific set 151 175 * @board_mux: Board specific mux table 152 176 * @flags: OMAP package type used for the board

+2 -1

arch/arm/mach-omap2/omap_hwmod.c

··· 94 94 95 95 oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); 96 96 97 - oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; 97 + if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE)) 98 + oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; 98 99 99 100 return 0; 100 101 }

+6 -6

arch/arm/mach-omap2/pm-debug.c

··· 54 54 regs[reg_count++].val = \ 55 55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off))) 56 56 57 - static int __init pm_dbg_init(void); 58 - 59 57 void omap2_pm_dump(int mode, int resume, unsigned int us) 60 58 { 61 59 struct reg { ··· 164 166 struct dentry *pm_dbg_dir; 165 167 166 168 static int pm_dbg_init_done; 169 + 170 + static int __init pm_dbg_init(void); 167 171 168 172 enum { 169 173 DEBUG_FILE_COUNTERS = 0, ··· 488 488 489 489 static int pwrdm_suspend_get(void *data, u64 *val) 490 490 { 491 - *val = omap3_pm_get_suspend_state((struct powerdomain *)data); 491 + int ret; 492 + ret = omap3_pm_get_suspend_state((struct powerdomain *)data); 493 + *val = ret; 492 494 493 - if (*val >= 0) 495 + if (ret >= 0) 494 496 return 0; 495 497 return *val; 496 498 } ··· 606 604 } 607 605 arch_initcall(pm_dbg_init); 608 606 609 - #else 610 - void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {} 611 607 #endif

+6 -2

arch/arm/mach-omap2/pm.h

··· 32 32 #ifdef CONFIG_PM_DEBUG 33 33 extern void omap2_pm_dump(int mode, int resume, unsigned int us); 34 34 extern int omap2_pm_debug; 35 + #else 36 + #define omap2_pm_dump(mode, resume, us) do {} while (0); 37 + #define omap2_pm_debug 0 38 + #endif 39 + 40 + #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 35 41 extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); 36 42 extern int pm_dbg_regset_save(int reg_set); 37 43 extern int pm_dbg_regset_init(int reg_set); 38 44 #else 39 - #define omap2_pm_dump(mode, resume, us) do {} while (0); 40 - #define omap2_pm_debug 0 41 45 #define pm_dbg_update_time(pwrdm, prev) do {} while (0); 42 46 #define pm_dbg_regset_save(reg_set) do {} while (0); 43 47 #define pm_dbg_regset_init(reg_set) do {} while (0);

+26 -21

arch/arm/mach-omap2/pm34xx.c

··· 26 26 #include <linux/err.h> 27 27 #include <linux/gpio.h> 28 28 #include <linux/clk.h> 29 + #include <linux/delay.h> 29 30 30 31 #include <plat/sram.h> 31 32 #include <plat/clockdomain.h> ··· 127 126 /* wait for the save to complete */ 128 127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 129 128 & PADCONF_SAVE_DONE)) 130 - ; 129 + udelay(1); 130 + 131 + /* 132 + * Force write last pad into memory, as this can fail in some 133 + * cases according to erratas 1.157, 1.185 134 + */ 135 + omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), 136 + OMAP343X_CONTROL_MEM_WKUP + 0x2a0); 137 + 131 138 /* Save the Interrupt controller context */ 132 139 omap_intc_save_context(); 133 140 /* Save the GPMC context */ ··· 401 392 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 402 393 omap3_enable_io_chain(); 403 394 } 395 + omap3_intc_prepare_idle(); 404 396 405 397 /* 406 398 * On EMU/HS devices ROM code restores a SRDC value ··· 448 438 OMAP3430_GR_MOD, 449 439 OMAP3_PRM_VOLTCTRL_OFFSET); 450 440 } 441 + omap3_intc_resume_idle(); 451 442 452 443 /* PER */ 453 444 if (per_next_state < PWRDM_POWER_ON) { ··· 589 578 } 590 579 591 580 omap_uart_prepare_suspend(); 581 + omap3_intc_suspend(); 582 + 592 583 omap_sram_idle(); 593 584 594 585 restore: ··· 848 835 CM_AUTOIDLE); 849 836 } 850 837 838 + omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); 839 + 851 840 /* 852 841 * Set all plls to autoidle. This is needed until autoidle is 853 842 * enabled by clockfw ··· 890 875 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 891 876 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 892 877 878 + /* Enable PM_WKEN to support DSS LPR */ 879 + prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, 880 + OMAP3430_DSS_MOD, PM_WKEN); 881 + 893 882 /* Enable wakeups in PER */ 894 883 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 895 884 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 896 - OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, 885 + OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | 886 + OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 887 + OMAP3430_EN_MCBSP4, 897 888 OMAP3430_PER_MOD, PM_WKEN); 898 889 /* and allow them to wake up MPU */ 899 890 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 900 891 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 901 - OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, 892 + OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | 893 + OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 894 + OMAP3430_EN_MCBSP4, 902 895 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 903 - 904 - /* Don't attach IVA interrupts */ 905 - prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 906 - prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 907 - prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 908 - prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 909 - 910 - /* Clear any pending 'reset' flags */ 911 - prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); 912 - prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); 913 - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); 914 - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); 915 - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); 916 - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); 917 - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); 918 - 919 - /* Clear any pending PRCM interrupts */ 920 - prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 921 896 922 897 /* Don't attach IVA interrupts */ 923 898 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);

-11

arch/arm/mach-omap2/prcm.c

··· 44 44 u32 iva2_cm_clksel2; 45 45 u32 cm_sysconfig; 46 46 u32 sgx_cm_clksel; 47 - u32 wkup_cm_clksel; 48 47 u32 dss_cm_clksel; 49 48 u32 cam_cm_clksel; 50 49 u32 per_cm_clksel; ··· 52 53 u32 pll_cm_autoidle2; 53 54 u32 pll_cm_clksel4; 54 55 u32 pll_cm_clksel5; 55 - u32 pll_cm_clken; 56 56 u32 pll_cm_clken2; 57 57 u32 cm_polctrl; 58 58 u32 iva2_cm_fclken; ··· 75 77 u32 usbhost_cm_iclken; 76 78 u32 iva2_cm_autiidle2; 77 79 u32 mpu_cm_autoidle2; 78 - u32 pll_cm_autoidle; 79 80 u32 iva2_cm_clkstctrl; 80 81 u32 mpu_cm_clkstctrl; 81 82 u32 core_cm_clkstctrl; ··· 271 274 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); 272 275 prcm_context.sgx_cm_clksel = 273 276 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); 274 - prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); 275 277 prcm_context.dss_cm_clksel = 276 278 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); 277 279 prcm_context.cam_cm_clksel = ··· 287 291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); 288 292 prcm_context.pll_cm_clksel5 = 289 293 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); 290 - prcm_context.pll_cm_clken = 291 - cm_read_mod_reg(PLL_MOD, CM_CLKEN); 292 294 prcm_context.pll_cm_clken2 = 293 295 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); 294 296 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); ··· 332 338 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 333 339 prcm_context.mpu_cm_autoidle2 = 334 340 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); 335 - prcm_context.pll_cm_autoidle = 336 - cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); 337 341 prcm_context.iva2_cm_clkstctrl = 338 342 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); 339 343 prcm_context.mpu_cm_clkstctrl = ··· 423 431 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); 424 432 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, 425 433 CM_CLKSEL); 426 - cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL); 427 434 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, 428 435 CM_CLKSEL); 429 436 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, ··· 439 448 OMAP3430ES2_CM_CLKSEL4); 440 449 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, 441 450 OMAP3430ES2_CM_CLKSEL5); 442 - cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN); 443 451 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, 444 452 OMAP3430ES2_CM_CLKEN2); 445 453 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); ··· 477 487 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, 478 488 CM_AUTOIDLE2); 479 489 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); 480 - cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE); 481 490 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, 482 491 CM_CLKSTCTRL); 483 492 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);

arch/arm/mach-omap2/prm.h

··· 24 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 25 25 #define OMAP44XX_PRM_REGADDR(module, reg) \ 26 26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) 27 + #define OMAP44XX_CHIRONSS_REGADDR(module, reg) \ 28 + OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg)) 27 29 28 30 #include "prm44xx.h" 29 31

+16 -16

arch/arm/mach-omap2/prm44xx.h

··· 386 386 387 387 388 388 /* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ 389 - #define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) 389 + #define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) 390 390 391 391 /* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ 392 - #define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) 392 + #define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) 393 393 394 394 /* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ 395 - #define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) 396 - #define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) 397 - #define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) 398 - #define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) 399 - #define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) 400 - #define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) 401 - #define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) 395 + #define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) 396 + #define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) 397 + #define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) 398 + #define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) 399 + #define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) 400 + #define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) 401 + #define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) 402 402 403 403 /* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ 404 - #define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) 405 - #define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) 406 - #define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) 407 - #define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) 408 - #define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) 409 - #define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) 410 - #define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) 404 + #define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) 405 + #define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) 406 + #define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) 407 + #define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) 408 + #define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) 409 + #define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) 410 + #define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) 411 411 #endif

+9 -4

arch/arm/mach-omap2/sleep34xx.S

··· 245 245 mov r1, #0 @ set task id for ROM code in r1 246 246 mov r2, #4 @ set some flags in r2, r6 247 247 mov r6, #0xff 248 - adr r3, write_aux_control_params @ r3 points to parameters 248 + ldr r4, scratchpad_base 249 + ldr r3, [r4, #0xBC] @ r3 points to parameters 249 250 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 250 251 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 251 252 .word 0xE1600071 @ call SMI monitor (smi #1) ··· 254 253 b logic_l1_restore 255 254 l2_inv_api_params: 256 255 .word 0x1, 0x00 257 - write_aux_control_params: 258 - .word 0x1, 0x72 259 256 l2_inv_gp: 260 257 /* Execute smi to invalidate L2 cache */ 261 258 mov r12, #0x1 @ set up to invalide L2 262 259 smi: .word 0xE1600070 @ Call SMI monitor (smieq) 263 260 /* Write to Aux control register to set some bits */ 264 - mov r0, #0x72 261 + ldr r4, scratchpad_base 262 + ldr r3, [r4,#0xBC] 263 + ldr r0, [r3,#4] 265 264 mov r12, #0x3 266 265 .word 0xE1600070 @ Call SMI monitor (smieq) 267 266 logic_l1_restore: ··· 272 271 273 272 ldr r4, scratchpad_base 274 273 ldr r3, [r4,#0xBC] 274 + adds r3, r3, #8 275 275 ldmia r3!, {r4-r6} 276 276 mov sp, r4 277 277 msr spsr_cxsf, r5 ··· 389 387 save_context_wfi: 390 388 /*b save_context_wfi*/ @ enable to debug save code 391 389 mov r8, r0 /* Store SDRAM address in r8 */ 390 + mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 391 + mov r4, #0x1 @ Number of parameters for restore call 392 + stmia r8!, {r4-r5} 392 393 /* Check what that target sleep state is:stored in r1*/ 393 394 /* 1 - Only L1 and logic lost */ 394 395 /* 2 - Only L2 lost */

+26

arch/arm/plat-omap/common.c

··· 172 172 clocksource_32k.mult, clocksource_32k.shift); 173 173 } 174 174 175 + /** 176 + * read_persistent_clock - Return time from a persistent clock. 177 + * 178 + * Reads the time from a source which isn't disabled during PM, the 179 + * 32k sync timer. Convert the cycles elapsed since last read into 180 + * nsecs and adds to a monotonically increasing timespec. 181 + */ 182 + static struct timespec persistent_ts; 183 + static cycles_t cycles, last_cycles; 184 + void read_persistent_clock(struct timespec *ts) 185 + { 186 + unsigned long long nsecs; 187 + cycles_t delta; 188 + struct timespec *tsp = &persistent_ts; 189 + 190 + last_cycles = cycles; 191 + cycles = clocksource_32k.read(&clocksource_32k); 192 + delta = cycles - last_cycles; 193 + 194 + nsecs = clocksource_cyc2ns(delta, 195 + clocksource_32k.mult, clocksource_32k.shift); 196 + 197 + timespec_add_ns(tsp, nsecs); 198 + *ts = *tsp; 199 + } 200 + 175 201 static int __init omap_init_clocksource_32k(void) 176 202 { 177 203 static char err[] __initdata = KERN_ERR

+1 -1

arch/arm/plat-omap/dma.c

··· 1183 1183 } 1184 1184 1185 1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1186 - (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 1186 + (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) { 1187 1187 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1188 1188 "before unlinking\n"); 1189 1189 dump_stack();

+13

arch/arm/plat-omap/dmtimer.c

··· 551 551 if (l & OMAP_TIMER_CTRL_ST) { 552 552 l &= ~0x1; 553 553 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 554 + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ 555 + defined(CONFIG_ARCH_OMAP4) 556 + /* Readback to make sure write has completed */ 557 + omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 558 + /* 559 + * Wait for functional clock period x 3.5 to make sure that 560 + * timer is stopped 561 + */ 562 + udelay(3500000 / clk_get_rate(timer->fclk) + 1); 563 + /* Ack possibly pending interrupt */ 564 + omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, 565 + OMAP_TIMER_INT_OVERFLOW); 566 + #endif 554 567 } 555 568 } 556 569 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);

arch/arm/plat-omap/include/plat/cpu.h

··· 434 434 #define OMAP3430_REV_ES2_1 0x34302034 435 435 #define OMAP3430_REV_ES3_0 0x34303034 436 436 #define OMAP3430_REV_ES3_1 0x34304034 437 + #define OMAP3430_REV_ES3_1_2 0x34305034 437 438 438 439 #define OMAP3630_REV_ES1_0 0x36300034 439 440

arch/arm/plat-omap/include/plat/irqs.h

··· 499 499 extern int omap_irq_pending(void); 500 500 void omap_intc_save_context(void); 501 501 void omap_intc_restore_context(void); 502 + void omap3_intc_suspend(void); 503 + void omap3_intc_prepare_idle(void); 504 + void omap3_intc_resume_idle(void); 502 505 #endif 503 506 504 507 #include <mach/hardware.h>

arch/arm/plat-omap/include/plat/omap_hwmod.h

··· 227 227 #define SYSC_HAS_SIDLEMODE (1 << 5) 228 228 #define SYSC_HAS_MIDLEMODE (1 << 6) 229 229 #define SYSS_MISSING (1 << 7) 230 + #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ 230 231 231 232 /* omap_hwmod_sysconfig.clockact flags */ 232 233 #define CLOCKACT_TEST_BOTH 0x0