tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/nve0/copy: add initial support for the async copy engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+164
+1
drivers/gpu/drm/nouveau/Makefile
+1
drivers/gpu/drm/nouveau/Makefile
···
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nouveau-y += core/engine/bsp/nv84.o
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nouveau-y += core/engine/copy/nva3.o
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nouveau-y += core/engine/copy/nvc0.o
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nouveau-y += core/engine/copy/nve0.o
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nouveau-y += core/engine/crypt/nv84.o
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nouveau-y += core/engine/crypt/nv98.o
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nouveau-y += core/engine/disp/nv04.o
+156
drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
+156
drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
···
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <core/os.h>
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#include <core/enum.h>
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#include <core/class.h>
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#include <core/engctx.h>
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#include <engine/copy.h>
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struct nve0_copy_priv {
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struct nouveau_copy base;
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};
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struct nve0_copy_chan {
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struct nouveau_copy_chan base;
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};
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/*******************************************************************************
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* Copy object classes
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******************************************************************************/
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static struct nouveau_oclass
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nve0_copy_sclass[] = {
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{ 0xa0b5, &nouveau_object_ofuncs },
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{},
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};
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/*******************************************************************************
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* PCOPY context
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******************************************************************************/
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static int
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nve0_copy_context_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nve0_copy_chan *priv;
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int ret;
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ret = nouveau_copy_context_create(parent, engine, oclass, NULL, 256,
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256, NVOBJ_FLAG_ZERO_ALLOC, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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return 0;
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}
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static struct nouveau_ofuncs
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nve0_copy_context_ofuncs = {
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.ctor = nve0_copy_context_ctor,
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.dtor = _nouveau_copy_context_dtor,
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.init = _nouveau_copy_context_init,
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.fini = _nouveau_copy_context_fini,
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.rd32 = _nouveau_copy_context_rd32,
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.wr32 = _nouveau_copy_context_wr32,
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};
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static struct nouveau_oclass
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nve0_copy_cclass = {
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.handle = NV_ENGCTX(COPY0, 0xc0),
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.ofuncs = &nve0_copy_context_ofuncs,
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};
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/*******************************************************************************
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* PCOPY engine/subdev functions
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******************************************************************************/
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static int
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nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nve0_copy_priv *priv;
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int ret;
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if (nv_rd32(parent, 0x022500) & 0x00000100)
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return -ENODEV;
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ret = nouveau_copy_create(parent, engine, oclass, true, 0, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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+
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nv_subdev(priv)->unit = 0x00000040;
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nv_engine(priv)->cclass = &nve0_copy_cclass;
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nv_engine(priv)->sclass = nve0_copy_sclass;
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return 0;
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}
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static int
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nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nve0_copy_priv *priv;
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int ret;
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if (nv_rd32(parent, 0x022500) & 0x00000200)
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return -ENODEV;
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ret = nouveau_copy_create(parent, engine, oclass, true, 1, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00000080;
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nv_engine(priv)->cclass = &nve0_copy_cclass;
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nv_engine(priv)->sclass = nve0_copy_sclass;
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return 0;
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}
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struct nouveau_oclass
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nve0_copy0_oclass = {
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.handle = NV_ENGINE(COPY0, 0xe0),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nve0_copy0_ctor,
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.dtor = _nouveau_copy_dtor,
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.init = _nouveau_copy_init,
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.fini = _nouveau_copy_fini,
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},
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};
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struct nouveau_oclass
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nve0_copy1_oclass = {
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.handle = NV_ENGINE(COPY1, 0xe0),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nve0_copy1_ctor,
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.dtor = _nouveau_copy_dtor,
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.init = _nouveau_copy_init,
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.fini = _nouveau_copy_fini,
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},
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};
+2
drivers/gpu/drm/nouveau/core/include/engine/copy.h
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drivers/gpu/drm/nouveau/core/include/engine/copy.h
+5
drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
+5
drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
···
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#include <engine/software.h>
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#include <engine/graph.h>
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#include <engine/disp.h>
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#include <engine/copy.h>
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int
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nve0_identify(struct nouveau_device *device)
···
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
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break;
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case 0xe7:
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device->cname = "GK107";
···
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
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break;
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default:
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nv_fatal(device, "unknown Kepler chipset\n");